JP5735077B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a silicon carbide (SiC) substrate and a method for manufacturing a vertical semiconductor device using the same, and more particularly to a technique for reducing forward resistance.

  In a semiconductor device, a vertical semiconductor device in which a current path in an element flows from a first main surface to a second main surface of the element is known. The performance of this type of semiconductor device is mainly determined by the element structure formed in the epitaxial layer formed on the substrate surface, and the substrate holds the epitaxial layer and plays the role of maintaining the strength.

  For example, in a conventional Schottky barrier silicon carbide (SiC) diode, an n-type SiC substrate, a SiC homoepitaxial growth film formed on the surface, a Schottky barrier anode electrode formed thereon, and an n-type SiC The cathode electrode is formed on the back surface of the substrate 1.

  In the case of a vertical semiconductor device, the resistance of the drift layer is determined by the IV characteristics between the anode and the cathode, so the resistance component is (surface contact resistance a) + (drift layer resistance b) + (substrate resistance c) + ( Determined by back contact resistance d). That is, the breakdown voltage of the device is held only by the drift layer resistance b, but the forward resistance is added to the drift layer resistance b by (surface contact resistance a) + (substrate resistance c) + (back surface contact resistance d). . Therefore, it is particularly necessary to reduce (substrate resistance c) + (back surface contact resistance d) formed on the back surface.

  Attempts have been made to reduce the substrate thin film or to increase the concentration of impurities on the back surface of the substrate in order to reduce contact resistance. However, since there is a concern that a thin substrate breaks during the semiconductor process after processing in the former, it is necessary to reduce the thickness after forming the upper structure. The latter increase in concentration usually requires annealing at 1500 ° C. or higher in order to activate the ion-implanted impurities. For this reason, the step of using the electrode material and the material having a melting point of 1500 ° C. or less needs to be performed after the annealing, and the substrate cannot be thinned and highly concentrated. Therefore, priority was given to one of the effects, and the other approach was not considered in particular.

  On the other hand, a proposal has been made to use a substrate having a high-concentration layer formed on the back surface in order to reduce contact resistance, and to form an electrode material on the high-concentration layer (see Patent Document 1).

JP 2003-86816 A

However, even in the technique of Patent Document 1, the resistance of the substrate itself cannot be omitted. Since a commercially available SiC wafer has a thickness of about 400 μm and a resistivity of about 0.020 Ωcm, the substrate alone has a resistance of 0.8 mΩcm ² . Since the forward direction of a 1200 V class SiC diode is several mΩcm ² , the effect is great if the substrate resistance can be omitted. In addition, the contact resistance is usually 0.1 mΩcm ² when there is no increase in the concentration of the substrate, and there is a variation. Therefore, it is essential to reduce the contact resistance.

  The present invention has been made in view of such problems, and an object thereof is to provide a low-resistance thin SiC semiconductor substrate and a semiconductor device using the same.

In order to achieve the above object, a first method of manufacturing a semiconductor device according to the present invention includes a second method of epitaxial growth on a first conductivity type silicon carbide substrate having a first impurity concentration at a film formation temperature of 1550 to 1600 ° C. Forming a first conductivity type or second conductivity type first silicon carbide layer having an impurity concentration of 2 μm, and an absolute value of the impurity concentration on the first silicon carbide layer is the second impurity concentration. A step of forming a second conductivity type second silicon carbide layer having the third impurity concentration so as to have a relationship of> first impurity concentration> third impurity concentration; and Forming a semiconductor element on the upper surface of the silicon layer; removing the back surface of the silicon carbide substrate after forming the semiconductor element to expose the first silicon carbide layer; and exposing the first Forming an electrode on one silicon carbide layer Characterized by comprising

According to a second method of manufacturing a semiconductor device of the present invention, the first conductivity type silicon carbide substrate having the first impurity concentration has the second impurity concentration by ion implantation at a substrate temperature of 400 ° C. or higher . A step of forming a first silicon carbide layer of a conductivity type or a second conductivity type, and an absolute value of an impurity concentration on the first silicon carbide layer is the second impurity concentration> the first impurity concentration. > A step of forming a second silicon carbide layer of the first conductivity type having the third impurity concentration so as to have a relationship of the third impurity concentration, and a semiconductor element on the upper surface of the second silicon carbide layer Forming the semiconductor element, removing the back surface of the silicon carbide substrate to expose the first silicon carbide layer, and forming an electrode on the exposed first silicon carbide layer And a step of forming

  According to the present invention, it is possible to provide a low-resistance thin silicon carbide (SiC) semiconductor substrate and a semiconductor device using the same.

The schematic diagram which shows the cross section which shows the semiconductor substrate of 1st Embodiment, and the semiconductor element formed in the upper part, and the concentration profile of a semiconductor substrate. 1 is a cross-sectional view of a semiconductor device (Schottky barrier diode) according to a first embodiment. Sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing which shows the process of following FIG. Sectional drawing of the semiconductor device (pn diode) which concerns on 2nd Embodiment. The schematic diagram which shows the layer structure and density | concentration profile of the semiconductor substrate which concern on 2nd Embodiment. Sectional drawing of the semiconductor device (vertical MOSFET) concerning 3rd Embodiment. The schematic diagram for demonstrating the parasitic resistance of a vertical MOSFET. A sectional view of a semiconductor device (vertical IGBT) concerning a 45th embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to the embodiments described below, and can be applied in various ways. In the following embodiments, the first conductivity type will be described as n-type, and the second conductivity type will be described as p-type.

(First embodiment)
1 and 2 are cross-sectional views of a semiconductor device (Schottky barrier diode) according to a first embodiment of the present invention. FIG. 1 shows a state immediately before a final configuration in which a semiconductor element is formed on a SiC semiconductor substrate. FIG. 2 shows the final form of the semiconductor device. The graph attached to the left end of FIG. 1 shows the impurity concentration distribution of the semiconductor substrate (SiC substrate and SiC semiconductor layer). In the figure, 1 is an n ⁺ type SiC bulk substrate, 2 is an n ⁻ type SiC epitaxial growth layer, 3 is an anode electrode, 4 is a cathode electrode, and 5 is an n ⁺⁺ type formed near the main surface of the n ⁺ type SiC bulk substrate. An SiC ultra-high concentration layer 6 is an n-type SiC buffer layer formed between the n ⁺⁺ type SiC ultra-high concentration layer 5 and the n ⁻ -type SiC epitaxial growth layer 2.

As shown at the left end of FIG. 1, the relationship of the concentration of each semiconductor layer is as follows: n ⁺⁺ type ultra-high concentration layer 5, n ⁺ type bulk substrate 1, n type buffer layer 6, n ⁻ type epitaxial layer 2 Also the n ^- -type epitaxial layer selectively termination structure 70 in an upper portion of the 2 is formed, the n ^- -type on the epitaxial growth layer 2, selectively anode electrode in contact with the inner end of the termination structure 70 3 is formed.

Next, as shown in FIG. 2, the back surface of the n ⁺ -type SiC bulk substrate 1 is ground in a state where the upper protective tape (not shown) is covered in the state shown in FIG. At this time, it is important not to cause characteristic deterioration in the upper structure of the semiconductor device. Further, the grinding end point is set to be in the n ⁺⁺ type ultra-high concentration layer 5. Next, an ohmic electrode 4 as a cathode electrode is formed on the surface thus ground. The state (FIG. 2) where the upper protective tape is finally removed is the final form of the first embodiment.

Next, consider the operation of the semiconductor device. In the above embodiment, a case where a voltage is applied so that the anode electrode 3 is in the positive direction with respect to the cathode electrode 4 is taken as an example. At this time, a forward current flows from the anode electrode 3 toward the cathode electrode 4, but since the semiconductor substrate is thin, the current path between the substrates can be shortened, and the forward resistance can be reduced. The on-voltage defined by a certain current density value (for example, 100 A / cm ² , 500 A / cm ^2, etc.) in the forward IV characteristics can also be reduced. Therefore, this structure is very effective particularly when applied to a system having a switching function.

  Further, when a voltage is applied so that the anode electrode 3 is in the negative direction with respect to the cathode electrode 4, it is not the bulk substrate 1 but the drift layer, that is, the epitaxial growth layer 2, that maintains the breakdown voltage. There is no deterioration in breakdown voltage due to thinning.

Next, a method for manufacturing the semiconductor device of this embodiment will be described. First, a SiC ingot is manufactured by a SiC bulk substrate manufacturing method including a sublimation method, and then a SiC bulk substrate is manufactured by mechanical polishing and chemical mechanical polishing (CMP). The doping concentration in the SiC bulk substrate is about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ , and here it is 8 × 10 ¹⁸ / cm ³ . In principle, it is possible to add more impurities than this, but it is not suitable for devices because crystal defects such as stacking faults are likely to occur and the quality of the crystals is reduced.

Thereafter, as shown in FIG. 1, the SiC ultra-high concentration layer 5 is formed on the SiC bulk substrate 1 by supplying silane, propane, and hydrogen as raw materials to the reaction tube with an epitaxial growth apparatus. At this time, normally, N is supplied as an impurity material so as to have a concentration of about 1 × 10 ¹⁴ to 1 × 10 ¹⁷ / cm ^{3. In} the present invention, however, the amount is larger than that of the SiC bulk substrate 1 in order to reduce the resistance. N ₂ is supplied so as to contain N, and for example, the impurity concentration of the SiC ultra-high concentration layer 5 is set to 1 × 10 ²⁰ to 1 × 10 ²² / cm ³ . In this embodiment, it is 1 × 10 ^{21 /} cm ³ . The film forming temperature is set to about 1550 to 1600 ° C., and the ultra high concentration film 5 of several μm is formed by growing for about 1 hour.

  The upper limit of the thickness of the ultra-high concentration layer 5 is not particularly limited, and the growth time may be increased with the same raw material supply amount, pressure, and temperature. It is preferable that the ultra-high concentration layer 5 is thick because the margin of the grinding end point is increased in the subsequent grinding step. On the other hand, since it is necessary to make the film thickness of the ultra-high concentration layer 5 as thin as possible in order to produce a low resistance substrate, it is considered that the thickness is preferably 2 μm or more and 50 μm or less after grinding.

  In this manner, a first-stage semiconductor substrate having the ultra-high concentration layer 5 intended to reduce the resistance in the vertical device forward direction is completed on the main surface side of the SiC bulk substrate 1.

Subsequently, in the same furnace, an SiC buffer layer 6 is formed on the ultra-high concentration layer film 5 in order to maintain lattice matching with the SiC epitaxial layer 2 which is a low concentration layer to be formed later. The impurity concentration of the buffer layer 6 is about 8 × 10 ¹⁷ to 2 × 10 ¹⁸ / cm ³ between the impurity concentration of the epitaxial layer 2 and the impurity concentration of the ultra-high-concentration layer film 5 determined by device requirements, and the thickness is 0.3 to 1 μm. Here, the impurity concentration is 1 × 10 ¹⁸ / cm ³ and the thickness is 0.5 μm.

In the epitaxial growth technique, the impurity concentration can be sharply changed without changing the crystal quality simply by changing the supply amount of N ₂ gas, but the impurities in the buffer layer can be reduced gradually by reducing the supply amount of N ₂ gas. The concentration may be inclined so that the substrate 1 side has a high impurity concentration and the epitaxial layer 2 side has a low impurity concentration.

Subsequently, the epitaxial layer 2 serving as a drift layer is formed on the buffer layer 6. The impurity concentration and thickness of the drift layer 2 are determined by the device design. In the case of 600V and 1200V Schottky barrier diodes, the concentration of the drift layer 2 is about 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ³ . The thickness of the drift layer is about 4 to 10 μm, but here the impurity concentration is 8 × 10 ¹⁵ / cm ³ and the thickness of the drift layer 2 is 8 μm. The buffer layer 6 may be omitted when there is no crystal problem in the drift layer 2 grown thereafter.

  As described above, the second-stage semiconductor substrate having the ultra-high concentration layer 5 and the SiC epitaxial layer 2 for reducing the resistance in the vertical device forward direction on the main surface side of the SiC bulk substrate 1 is completed.

Next, a method for manufacturing a low-resistance semiconductor device using the second stage semiconductor substrate will be described. As shown in FIG. 4, a RESURF region 7 having a p ⁻ type impurity concentration is formed on the surface of the n ⁻ type epitaxial layer 2 of the semiconductor substrate having the ultra-high concentration layer 5. An edge termination layer 8 having a p ⁺ -type impurity concentration may be formed at the end of a Schottky electrode contact hole to be formed later.

A p ⁻ type guard ring 9 is formed on the surface of the n ⁻ type epitaxial layer 2 so as to surround the p ⁻ type RESURF region 7 and functions as a breakdown voltage structure. In this case, the effect can be enhanced if the guard ring 9 has a plurality of layers.

The RESURF region 7 and the guard ring 9 have substantially the same impurity concentration, and the concentration is, for example, 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ³ . Further, an n ⁺ type channel stopper 10 for fixing the potential of the semiconductor is disposed at the terminal end of the element, and this concentration is, for example, 1 × 10 ¹⁹ to 2 × 10 ²⁰ / cm ³ , and here, 5 × 10 ¹⁹ / cm ³ .

Subsequently, as shown in FIG. 5, the insulating film 12 is formed on the entire surface of the n ⁻ -type epitaxial layer 2, and the contact hole for the first electrode is formed so that the end portion is on the resurf region 7. . As the material of the insulating film 12, SiO ₂ or SiN is often used, but here it is SiO ₂ .

Next, a first electrode (anode electrode) 3 is provided so as to be in contact with the surface of the n ⁻ type epitaxial layer 2 opened in the contact hole. As the electrode material of the anode electrode, a material that can be Schottky bonded to n-type SiC, for example, Ti, Ni, Au, Mo, or the like is used. In the present embodiment, Ti is taken as an example.

  A metal field plate 11 electrically connected to the first electrode is formed on the first electrode. The metal field plate 11 also extends over the insulating film 12 and faces the epitaxial layer 2 through the insulating film 12. As the material of the metal field plate, the outermost surface is a material that can be easily wire-bonded, for example, Al or Au. Here, Al is taken as an example.

Further, when the adhesion at the interface between the Schottky electrode 3 and the epitaxial layer 2 is not very good, a material that increases the adhesion may be sandwiched between the Schottky electrode 3 and the metal field plate 11. Since the electric field tends to concentrate at the field plate edge when a reverse electric field is applied, the termination structure 70 including the p ⁻ -type resurf region 7 and the p ⁻ -type guard ring 9 is disposed below the field plate edge. Suitable for pressure resistance.

  Thereafter, as shown in FIG. 6, the surface is protected with a tape material 13 or the like, and the back surface of the SiC bulk substrate 1 is ground. Since the bulk substrate 1 usually has a thickness of about several hundreds of micrometers, it is efficient to perform mechanical polishing up to a thickness of 100 micrometers. However, care must be taken not to damage the element surface by focusing on increasing the polishing rate. Thereafter, the grinding speed is changed to the thickness of the grinding substrate, the type of grinding and the like are changed, and finally grinding is performed to several μm. The stop point is to confirm that the ultra-high concentration layer 5 is exposed on the surface by a film thickness monitor and CV measurement using a dummy substrate.

  Thereafter, after simple cleaning, as shown in FIG. 7, the cathode electrode 4 is formed on the back surface high-concentration layer 5 at room temperature contact with the substrate holding tape 13 attached. Since Ti can be contacted to the C surface of the n-type SiC at room temperature, the cathode electrode 4 can be sufficiently formed even at room temperature. In order to further reduce the contact resistance of the cathode electrode, an ohmic electrode may be formed with a Ti / Ni / Au laminated structure (not shown).

  Thereafter, as shown in FIG. 8, the completed element is attached to a low-resistance substrate 14 such as a DBC (direct bonded copper) substrate to reinforce the mechanical strength of the semiconductor device made of a thin SiC semiconductor layer. Thereafter, the upper tape material 13 is peeled off and a passivation material (not shown) as a pressure-resistant structure is formed on the upper portion, thereby completing the semiconductor device according to the first embodiment.

In the first embodiment, the semiconductor substrate is an n ⁺ type high impurity concentration substrate, but the conductivity type and concentration of the semiconductor substrate are not limited to this, and there is no problem even if it is p type or insulating type. . After the semiconductor device is completed, the semiconductor substrate is polished and only the ultra-high concentration layer 5 remains, and the surface of the ultra-high concentration layer 5 becomes a contact surface with the back ohmic electrode, so that the impurity concentration of the semiconductor substrate is low. Even a high resistance layer has no problem.

  However, since a buffer layer and an epitaxial layer are formed on the substrate, crystal defects such as micropipes, etch pits, spiral dislocations, edge dislocations, and stacking faults are used so that the epitaxial growth film serving as a drift layer is of high quality. A high crystal quality is required.

(First Modification of Manufacturing Method of First Embodiment)
Although the ultra-high concentration layer 5 in the above-described embodiment is formed by epitaxial growth, it may be formed by ion implantation. Hereinafter, a method of forming by ion implantation will be described with reference to FIG.

  First, an n-type ion species such as nitrogen (N) or phosphorus (P) is implanted from the main surface side of the manufactured SiC bulk substrate 1. Since high concentration ion implantation is performed, it is preferable to perform implantation at a high temperature of 400 ° C. or more in consideration of crystal damage to the bulk substrate 1, which is 500 ° C. here. When the substrate temperature is controlled by the heater temperature, it is necessary to set the heater temperature higher in consideration of the heat transfer rate to the substrate and the thermal conductivity of the substrate itself. Usually, there is a difference of about 100 ° C. between the heater temperature and the substrate temperature.

Since ion implantation needs to be performed as deeply as possible, the highest ion implantation energy currently available: 8 MeV is used. The dose is about 1 × 10 ¹⁸ / cm ² and the concentration is about 1 × 10 ²¹ to 1 × 10 ²² / cm ³ . The profile is a box profile in which the high concentration region is arranged from the surface side.

Thereafter, the buffer layer 6 and the drift layer 2 are formed by an epitaxial CVD apparatus. At this time, since there is a possibility of bunching or crystal damage on the substrate surface that has been highly implanted by ion implantation, the formation of the buffer layer 6 is started after etching the SiC surface with hydrogen before growth. Good. Further, during the growth of the buffer layer 6, the N ₂ gas supply amount is gradually decreased, so that the impurity concentration in the buffer layer 6 is inclined, so that the substrate side has a high impurity concentration and the epitaxial layer side has a low impurity concentration. It may be. Subsequently, the epitaxial layer 2 serving as a drift layer is formed thereon, and thereafter, a device may be manufactured as in the first embodiment.

  The ion-implanted layer implanted from the main surface of the SiC substrate 1 is activated through an epitaxial CVD process without performing activation annealing. The maximum implantation energy of the current ion implantation is 8 MeV. When P ion implantation is performed in the SiC substrate 1 using this energy, the depth of the formed ultra-high concentration layer 5 is about 2.5 to 3.5 μm. It is. When the back surface is polished, the remaining thickness of the substrate needs to be about 2.5 to 3 μm. If the maximum ion implantation energy is further increased, the corresponding ion species penetrates deeper into the SiC substrate, so that the degree of freedom of the stop point is increased during back surface polishing and the back surface polishing process is increased.

  As described above, according to the first embodiment, a low-resistance SiC substrate and a semiconductor device using the same can be provided. In the first embodiment, the case where SiC is used as the semiconductor material has been described, but it goes without saying that the same effect can be obtained by adapting not only to SiC but also to GaN, diamond, and the like.

(Second modification of the manufacturing method of the first embodiment)
As the substrate thinning method in the above-described embodiment, processing may be performed by reactive dry etching instead of polishing. A gas system is a fluoride system such as SF _6, and the back surface of SiC is etched at a relatively high rate of about 50 μm in 5 minutes by etching the back surface of SiC in high-density plasma. Can do. Further, because of the ionic reaction, damage to the treated surface can be reduced. It is also possible to use a material that is compatible with the semiconductor process, such as a resist, as the surface protective material at that time. If it is a resist, it can be easily removed.

  As described above, according to the first embodiment, a Schottky barrier diode using a low-resistance SiC layer can be realized.

(Second Embodiment)
FIG. 9 is a cross-sectional view of a pn diode according to the second embodiment of the present invention. FIG. 10 is a cross-sectional view showing the layer structure of a semiconductor substrate used for this diode, and the concentration profile of the component layers is shown at the left end. For ease of understanding, the same parts as those in the first embodiment are denoted by the same reference numerals.

In the pn diode of the second embodiment, a p ⁺⁺ type SiC ultra-high concentration layer 15 is provided on the upper surface side of the SiC substrate 1. Therefore, as shown in FIG. 10, the concentration profile has a reverse polarity in the ultra-high concentration layer 15 portion.

As shown in FIG. 9, an n ⁻ type SiC drift layer 2 is formed on the upper portion of the super high concentration layer 15 via an n type SiC buffer layer 6, and an ohmic junction is formed on the surface of the n ⁻ type drift layer 2. A first electrode (cathode electrode) 3 is selectively formed. A second electrode (anode) electrode 4 that forms an ohmic junction is disposed on the back surface (surface opposite to the main surface) of the p ⁺⁺ type ultra-high concentration layer 15 that is exposed by polishing the SiC substrate 1. Functions as a pn diode.

In addition, a p-type ion implantation layer 7 is disposed on the surface of the n ⁻ -type drift layer 2 as a breakdown voltage structure disposed so as to overlap the end portion of the first electrode 3. An edge termination layer (8) may be formed in the p-type ion implantation layer as in the first embodiment. A guard ring (9) and a channel stopper (10) can also be formed.

A method for manufacturing the pn diode will be briefly described with reference to FIGS. 3 to 8 of the first embodiment. First, a p ⁺⁺ type high-concentration layer 5 is grown on the 4H—SiC semiconductor substrate 1 by several μm to several tens μm by CVD epitaxial growth. At this time, boron (B) or aluminum (Al) is used as the dopant. Thereafter, the n-type buffer layer 6 and the n ⁻ -type drift layer 2 are formed. The drift layer 2 differs depending on the target value of the breakdown voltage, but in the 1200 V system, the drift layer concentration is 6 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ³ and the thickness is about 6 to 10 μm.

After that, as in FIG. 4, an n ⁺ channel stopper 10 is formed by ion implantation of p ⁻ and p ^{+ by} ion implantation of Al or B and ion implantation of phosphorus (P) or nitrogen (N). To do. A surface field oxide film is formed after activation annealing, a first electrode is formed using an electrode material that becomes an ohmic electrode after opening a contact hole, for example, Ni, and a p ⁺⁺ type high concentration layer is formed on the back surface. The second electrode is formed using an electrode material that is in ohmic contact with the electrode 15, for example, Ti. Thereafter, an ohmic junction is formed by sintering at a temperature of 950 ° C. or higher in an inert gas atmosphere such as Ar and N ₂ .

  Thereafter, the pad electrode 11 on the surface is formed. The pad electrode 11 on the surface is, for example, Ti / Al. Ti / Al, Ti / Au, Ti / NI / Au, etc. can also be used for the back electrode. The surface pad electrode 11 is patterned by etching Al and Ti through a resist.

  Thereafter, the front surface is protected with a tape material 13 or the like, and the back surface is mechanically ground. Usually, since the substrate has a thickness of about several hundred μm, it is preferable to efficiently perform the polishing up to a thickness of 100 μm by mechanical polishing. Thereafter, grinding is finally performed to several μm by changing the speed of mechanical grinding, the kind of grinding, etc. according to the thickness of the grinding substrate. The stop point is to confirm that the ultra-high concentration layer 15 is exposed on the surface by a film thickness monitor and CV measurement using a dummy substrate.

  Thereafter, after simple cleaning, the second electrode 4 is formed on the back surface of the ultra-high concentration layer 5 with the substrate holding tape 13 attached. At this time, since the second electrode 4 plays a role of holding the substrate in addition to the anode contact, it is preferable to have a thickness of about several tens to 100 μm by electroplating or the like. In the case of a composite material such as Ti / Al, Ti / Al may be formed first by vapor deposition or the like, and then Al may be formed thereon by electroplating. Thereafter, after the tape material 13 is peeled off, heat treatment at 950 ° C. or higher is performed in order to lower the contact resistance of the first and second electrodes.

In this case, the resistance for the p ⁺⁺ type layer (super high concentration layer 15), which is usually the substrate resistance, can reduce the resistance between the anode and the cathode because the p ⁺⁺ type layer is ultra high concentration and extremely thin. The on-resistance of the element can be reduced. On the other hand, the breakdown voltage does not change because only the n ⁻ -type drift layer 2 carries a reverse electric field. Further, the pn diodes of the n ⁺⁺ type ultra-high concentration layer 5 and the p ⁻ type drift layer (2) may be reversed. Alternatively, a pin diode of a p ⁺ type layer formed on the n ⁺⁺ type ultra high concentration layer 5, the n ⁻ type drift layer 2 and the n ⁻ type drift layer 2 may be used.

  Further, similarly to the second modification of the manufacturing method of the first embodiment, reactive ion etching may be used as the backside thinning method.

  As described above, according to the second embodiment, a pn diode using a low-resistance SiC layer can be provided.

(Third embodiment)
FIG. 11 is a fragmentary cross-sectional view of a vertical MOSFET according to the third embodiment of the present invention. An ultrahigh concentration n ⁺⁺ type layer 5 is provided on the main surface side of the SiC substrate 1 (not shown) of the first embodiment, and an n ⁻ type drift layer 2 is formed thereon via an n type buffer layer 6. ing. A gate electrode 17 is formed on the surface of the n ⁻ -type drift layer 2 via a source electrode 3 that selectively forms an ohmic junction and a gate insulating film 16 that is a thin oxide film or a high dielectric film. A drain electrode 4 serving as an ohmic junction is formed on the back surface of the n ⁺⁺ type ultra-high concentration layer 5 exposed by polishing the SiC substrate 1.

Further, on the main surface side of the n ⁻ type drift layer 2, a p ⁻ type region 18 that is in contact with the gate electrode 17 through the gate insulating film 16 and is selectively provided below the source electrode 3, and the p ⁻ type region 18. The n ⁺ -type source contact region 19 is provided so as to be in contact with the gate electrode 17 through the source electrode 3 and the gate insulating film 16 and functions as a vertical MOSFET as a whole.

In the case of a vertical MOSFET, as shown in the schematic diagram for one element in FIG. 12, main resistance components include a source contact resistance R _sc , a channel resistance R _ch , a JFET resistance RJ _JFET , a drift resistance R _drift , and a substrate resistance R There are _sub , and the JFET resistance changes depending on the channel length. When the channel length is 2.5 μm, the contribution of the substrate resistance is about 20%. Therefore, the substrate resistance can be reduced by the present invention, which greatly contributes to a reduction in device loss.

A manufacturing method of the vertical MOSFET according to the third embodiment will be described with reference to FIGS. 3 to 8 of the first embodiment. First, as in FIG. 3, an ultrahigh concentration n ⁺⁺ type layer 5 having a thickness of several to several tens of μm is formed on a high crystal quality 4H—SiC substrate 1 by epitaxial growth. For example, nitrogen (N) is used as the impurity at this time. Subsequently, an n-type buffer layer and an n ⁻ -type drift layer are formed by epitaxial growth.

For example, N is used as the impurity element of the n-type buffer layer 6 and the n ⁻ -type drift layer 2, and the impurity concentration is, for example, about 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ^{3 in} the case of the n-type buffer layer 6. In the case of the n ⁻ -type drift layer 2, it is about 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ^{3 in} the case of a design withstand voltage of 1200V. In the case of the drift layer 2, the impurity concentration can be adjusted according to the design breakdown voltage. The thickness of the buffer layer 6 is about 0.3 to 1.0 μm, and the thickness of the n ⁻ -type drift layer 2 is about 5 to 15 μm.

Subsequently, a p ⁻ type epitaxial layer (not shown) having an impurity concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ³ and a thickness of about 0.6 μm is formed on the entire surface of the drift layer 2. Al or B is used as the p-type impurity species of SiC.

Then, p ^- -type epitaxial layer top surface, for example of silicon oxide film to form an ion implantation mask (not shown), p ^- N or P -type epitaxial layer performs selective counter ion implanted as the ion species, p ^- An n ⁻ -type layer 20 (FIG. 11) that penetrates a part of the epitaxial layer and is connected to the drift layer 2 is formed. The ion implantation species P can reduce the resistance, but it may be N or P + N. At this time, multi-stage ion implantation with the highest energy of about 400 keV is performed, and the dose is adjusted so that the impurity concentration is about 1 × 10 ^{16 to} 3 × 10 ¹⁷ / cm ³ . At this time, the n-type region 20 implanted with the highest energy penetrates the p ⁻ -type epitaxial layer and contacts the n-type drift layer 2.

After the ion implantation mask is removed, an ion implantation mask (not shown) is formed again, and an n ⁺ source contact 19 having an impurity concentration of about 1 × 10 ^{18 to} 3 × 10 ¹⁹ / cm ³ and a depth of about 0.3 μm is formed. The depth needs to be located inside the p ⁻ -type epitaxial region 18. Thereafter, the implanted ion species are placed in the crystal lattice and processed at a high temperature of about 1600 ° C. for several minutes in order to activate them.

  Thereafter, a silicon oxide film having a thickness of about 30 to 50 μm to be the gate oxide film 16 is formed thereon by wet oxidation and POA (post oxidation annealing) in a hydrogen atmosphere. A polysilicon gate electrode 17 is formed thereon by CVD, for example, a silicon oxide film having a thickness of about 1 μm is further formed thereon by CVD, and a gate electrode is formed by patterning with a resist. The silicon oxide film can be left only in the place. Thereafter, a source electrode layer is formed and patterned to form the source electrode 3 on the source region.

  Thereafter, similarly to FIG. 6, the surface is protected with a tape material 13 or the like, and the back surface is mechanically ground. Depending on the thickness of the grinding substrate, the machine grinding speed and type of grinding are changed to finally grind to several μm. The stop point is to confirm that the ultra-high concentration layer 5 is exposed on the surface by CV measurement using a film thickness monitor and a dummy substrate.

  After simple cleaning, the drain electrode 4 is formed on the back surface of the ultra-high concentration layer 5 with the substrate holding tape 13 attached. At this time, since the drain electrode plays a role of holding the substrate in addition to the drain contact, it is preferable to add a thickness of about several tens to 100 μm by electroplating or the like. Electrode materials suitable for p-type contacts are Ti and Ti / Al, but in the case of composite materials such as Ti / Al, Ti / Al is first deposited by vapor deposition and then Al is applied to the top. It may be formed by plating. Thereafter, after the tape material 13 is peeled off, heat treatment at 950 ° C. or higher is performed in order to lower the contact resistance of the source electrode 3 and the drain electrode 4.

  In the third embodiment, the n-type and p-type may be reversed to form a p-type MOSFET. Furthermore, the ultra-high concentration layer 5 may be formed not by epitaxial growth but by ion implantation from the main surface side. In that case, it is necessary to use the ultra-high concentration layer 5 formed by ion implantation as a stop point for back surface polishing. Thinning may be performed by reactive ion etching (RIE).

Further, the p ⁻ type layer 18 on the n ⁻ type drift layer 2 may be formed not by epitaxial growth but by ion implantation. That is, an n ⁻ -type drift layer is formed by adding 0.6 μm to the above thickness, and then p ⁻ ion implantation is selectively performed, whereby the p ⁻ -type layer 18 is manufactured. Thereafter, an n ⁺ type source contact 19 is formed, and then the source electrode 3 is formed.

  As described above, according to the third embodiment, a vertical MOSFET using a low-resistance SiC layer can be formed.

(Fourth embodiment)
FIG. 13 is a cross-sectional view of a main part of an IGBT according to the fourth embodiment of the present invention. The IGBT is similar in shape to the MOSFET of the third embodiment, but uses a substrate as shown in FIG. 10 of the second embodiment.

That is, a p ⁺⁺ type ultra-high concentration layer 15 is provided on the main surface side of the SiC substrate 1, and an n ⁻ type drift layer 2 is formed thereon via an n type field stop layer 6. A gate electrode 17 is selectively formed on the surface of the n ⁻ -type drift layer 2 via an emitter electrode 3 that forms an ohmic junction and a gate insulating film 16 made of a thin silicon oxide film or a high dielectric film. A collector electrode 4 serving as an ohmic junction is formed on the p ⁺⁺ type ultra-high concentration layer exposed by polishing the substrate.

Further, on the main surface side of the n ⁻ type drift layer 2, the p ⁻ type region 18 selectively provided so as to be in contact with the emitter electrode 3 and the gate electrode 17 through the gate insulating film 16, and the p ^The n ⁺ type emitter contact 19 is provided on the inner surface of the ⁻ type region 18 so as to be in contact with the gate electrode 17 through the emitter electrode 3 and the gate insulating film 16, and functions as a vertical IGBT as a whole element To do.

Similarly to FIG. 12 of the vertical MOSFET, the vertical IGBT has emitter contact resistance R _sc , channel resistance R _ch , JFET resistance R _JFET , drift resistance R _drift , and substrate resistance R _sub as main resistance components. Although the JFET resistance varies depending on the length, the substrate resistance contributes about 20% when the channel length is about 2.5 nm. Therefore, the substrate resistance can be reduced by this embodiment, which greatly contributes to the reduction of the loss of the device.

  Furthermore, since a p-type SiC thin film substrate cannot be produced at present, the SiC-IGBT has a breakdown voltage of only about 5 to 10 kV. However, according to the present invention, an IGBT having a low breakdown voltage of, for example, 600 V can be manufactured. An IGBT can also be fabricated by adding an n-type field stop layer to the back surface of the semiconductor substrate with a field stop structure.

  In the case of a punch-through type IGBT, since the p-type substrate is usually thick, carriers are excessively injected at the time of turn-on, resulting in a slow switching. realizable.

Next, the manufacturing method of IGBT of this embodiment is demonstrated using FIGS. 3-8 of 1st Embodiment. First, as in FIG. 3, p ⁺ having a thickness of several to several tens of μm and an impurity concentration of about 1 × 10 ¹⁷ to 1 × 10 ²¹ / cm ³ by epitaxial growth on a high crystal quality 4H—SiC substrate 1. ^{A +} -type layer (15 in this embodiment, not 5) is produced. For example, aluminum (Al) or boron (B) is used as the impurity at this time. Subsequently, the n-type field stop layer 6 and the n ⁻ -type drift layer 2 are formed by epitaxial growth.

For example, N is used as the impurity species of the n-type field stop layer 6 and the n ⁻ -type drift layer 2, and the impurity concentration is, for example, about 1 × 10 ^{15 to} 5 × 10 ¹⁷ cm ^{3 in} the case of the n-type field stop layer 6. In the case of an n-type drift layer, it is about 1 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ^{3 in} the case of a design withstand voltage of 600V. In the case of the drift layer 2, impurities can be adjusted according to the design withstand voltage.

The thickness of the buffer layer 6 is about 0.3 to 1.0 μm, and the thickness of the n ⁻ -type drift layer 2 is about 5 to 15 μm.

Further, a p ⁻ type epitaxial layer (not shown) having an impurity concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ / cm ³ and a thickness of about 0.6 μm is formed on the entire surface of the drift layer 2. Al and B are used as the p-type impurity species in the epitaxial layer. Then, p ^- type on the upper surface of the epitaxial layer, to form, for example, an ion implantation mask of a silicon oxide film (not shown), performs selective counter ion implanted N and P as the ion species, p ^- one type epitaxial layer An n ⁻ -type layer 20 that penetrates the portion and is connected to the drift layer 2 is formed. The ion implantation species P can reduce the resistance, but may be N or P + N. At this time, the multistage ion implantation with the maximum energy of about 400 keV is performed, and the dose is adjusted so that the impurity concentration is about 1 × 10 ^{16 to} 3 × 10 ¹⁷ / cm ³ . At this time, the n ⁻ type region 20 implanted with the highest energy penetrates the p ⁻ type epitaxial layer and is connected to the n ⁻ type drift layer 2.

After removing the ion implantation mask, an ion implantation mask is formed again, and an n ⁺ -type emitter contact 19 having an impurity concentration of about 1 × 10 ^{18 to} 3 × 10 ¹⁹ / cm ³ and a depth of about 0.3 μm is formed (FIG. 13). ). The depth needs to be located inside the p ⁻ -type epitaxial region 18. Thereafter, the implanted ion species are placed in the crystal lattice and processed at a high temperature of about 1600 ° C. for several minutes in order to activate them.

  Thereafter, a silicon oxide layer having a thickness of about 30 to 50 μm to be the gate oxide film 16 is formed on the upper portion by wet oxidation, and POA is performed in a hydrogen atmosphere. A polysilicon gate electrode 17 is formed thereon by CVD, for example. A silicon oxide film (not shown) having a thickness of about 1 μm is further formed on the gate electrode 17 by CVD, and a silicon oxide layer is left so as to cover the gate electrode 17 by patterning with a resist. Thereafter, an electrode layer is formed and patterned to form the emitter electrode 3 on the emitter contact 20 (FIG. 13).

  Thereafter, similarly to FIG. 6, the front surface is protected with a tape material 13 and the like, and the back surface is mechanically ground. Depending on the thickness of the grinding substrate, the machine grinding speed and type of grinding are changed to finally grind to several μm. The stop point is to confirm that the ultra-high concentration layer 15 is exposed on the surface by a film thickness monitor and CV measurement using a dummy substrate. Thereafter, after simple cleaning, the collector electrode 4 is formed on the ultra-high concentration layer 15 with the substrate holding tape 13 attached. At this time, the collector electrode 4 serves not only as a collector contact but also as a holding substrate. Therefore, it is preferable to add a thickness of about several tens to 100 μm by electroplating or the like.

  Suitable metals for the collector electrode 4 are Ti and Ti / Al. However, in the case of a composite material such as Ti / Al, the Ti / Al film is first formed by vapor deposition or the like, and then Al is applied to the upper portion of the electric field. It may be formed by plating. Thereafter, after the tape material 13 is peeled off, heat treatment at 950 ° C. or higher is performed in order to reduce the contact resistance of the electrode. A vertical IGBT is thus completed.

  As described above, according to the fourth embodiment, a vertical IGBT using a low-resistance SiC layer can be formed.

The ultra-high-concentration layer 5 or 15 contains an impurity having a concentration of 1 × 10 ¹⁹ / cm ³ or more, which is an impurity concentration that can be introduced without lowering the crystal quality in normal single crystal growth. Can be proved by examining the impurity concentration of N and P, which are SiC n-type impurities, by an analysis method such as SIMS.

  Also, when ion implantation is performed from the main surface of the device with the highest actual acceleration energy by ion implantation, the profile has a maximum concentration of several μm from the main surface side of the substrate, but it has been found that a tail is further drawn. Yes. In this case, the crystal damage introduced by ion implantation (observable by TEM observation) also enters from the main surface side of the substrate toward the opposite side of the main surface. It does not affect the buffer layer and the drift layer that hold.

  There is also a method in which after the substrate is thinned, ions are implanted from the opposite direction to the main surface and annealed by laser annealing. In the case of this method, the tail and crystal damage of the ion-implanted layer enter the buffer layer and the drift layer side, which causes a problem of suppressing the breakdown voltage.

  On the other hand, when ion implantation is performed so that all of the ion implantation portion including the tail portion enters the substrate, the impurity concentration on the main surface side cannot be increased, and the on-resistance is not sufficiently lowered. The problem arises.

  The present invention has been described above through the embodiments. However, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.

1 ... SiC bulk substrate 2 ... Drift layer (epitaxial layer)
DESCRIPTION OF SYMBOLS 3 ... 1st electrode 4 ... 2nd electrode 5 ... n-type super high concentration layer 6 ... Buffer layer, field stop layer 7 ... RESURF layer 8 ... Edge termination layer 9 ... Guard ring 10 ... Channel stopper 11 ... Metal field plate DESCRIPTION OF SYMBOLS 12 ... Insulating film 13 ... Tape material 14 ... Low resistance substrate 15 ... p-type super high concentration layer 16 ... Gate insulating film 17 ... Gate electrode 18 ... p-type area | region 19 ... n ⁺ contact 20 ... n < ^- > type | mold area | region 70 ... Termination structure

Claims (7)

A first conductivity type or second conductivity type first silicon carbide layer having a second impurity concentration by epitaxial growth at a film formation temperature of 1550 to 1600 ° C. on a first conductivity type silicon carbide substrate having a first impurity concentration. Forming a step;
On the first silicon carbide layer, the third impurity concentration is set such that the absolute value of the impurity concentration has a relationship of the second impurity concentration> the first impurity concentration> the third impurity concentration. Forming a first conductivity type second silicon carbide layer comprising:
Forming a semiconductor element on the upper surface of the second silicon carbide layer;
Removing the back surface of the silicon carbide substrate after forming the semiconductor element to expose the first silicon carbide layer;
Forming an electrode on the exposed first silicon carbide layer;
A method for manufacturing a semiconductor device, comprising: A first conductivity type or second conductivity type first silicon carbide layer having a second impurity concentration by ion implantation at a substrate temperature of 400 ° C. or higher is applied to a first conductivity type silicon carbide substrate having a first impurity concentration. Forming, and
On the first silicon carbide layer, the third impurity concentration is set such that the absolute value of the impurity concentration has a relationship of the second impurity concentration> the first impurity concentration> the third impurity concentration. Forming a first conductivity type second silicon carbide layer comprising:
Forming a semiconductor element on the upper surface of the second silicon carbide layer;
Removing the back surface of the silicon carbide substrate after forming the semiconductor element to expose the first silicon carbide layer;
Forming an electrode on the exposed first silicon carbide layer;
A method for manufacturing a semiconductor device, comprising:   3. The method of manufacturing a semiconductor device according to claim 1, wherein the first silicon carbide layer is formed with a thickness of 2 μm to 50 μm. The method for manufacturing a semiconductor device according to claim 1, wherein the second impurity concentration is 1 × 10 ²⁰ to 1 × 10 ²² / cm ³ .   The method for manufacturing a semiconductor device according to claim 1, wherein the deletion for exposing the first silicon carbide layer is performed by polishing.   6. The method of manufacturing a semiconductor device according to claim 5, wherein after the polishing for exposing the first silicon carbide layer, the damaged layer is removed by reactive dry etching.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the deletion for exposing the first silicon carbide layer is performed by reactive dry etching.