JP2004022878A - Semiconductor device and its manufacturing process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing process in which ON resistance is further decreased using an SiC substrate. <P>SOLUTION: The semiconductor device is polished to have a thickness of 200 μm or less and comprises the SiC substrate 11a having an upper surface of a (000-1)C face, an epitaxial growth layer 12, a Schottky electrode 14 and an upper electrode 16 provided sequentially on the upper surface of the SiC substrate 11a, and an ohmic electrode 15 and a lower electrode 17 provided sequentially on the Si face, i.e. the rear surface of the SiC substrate 11a. Since the SiC substrate 11a is thinner than a conventional substrate, on-resistance is greatly decreased in operation. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device using a substrate made of silicon carbide and a method of manufacturing the same, and more particularly, to a semiconductor power device having a high withstand voltage and used with a large current and a method of manufacturing the same.
[0002]
[Prior art]
A rectifying element and a switching element using silicon (Si) have been widely used as a power device driven at a high current with a high withstand voltage. However, with the recent development of technology, the physical property limit of Si has become a problem.
[0003]
For example, a pn diode made of Si is used as a rectifying element that requires a withstand voltage of a certain level or more, but has a disadvantage that switching loss is large. For this reason, a Schottky diode with smaller switching loss is expected as a substitute for a pn diode. However, it is difficult for a Schottky diode using Si to obtain a desired breakdown voltage due to a limit of the physical properties of Si, so that its practical use has been limited. Therefore, silicon carbide (silicon carbide, SiC) has attracted attention as a material for manufacturing a semiconductor device having high withstand voltage and small switching loss.
[0004]
SiC has a high insulation resistance due to its large band gap as compared with Si, and is a semiconductor having stable properties even at high temperatures. From such characteristics, SiC is expected to be applied not only to switching elements but also to power devices, environment-resistant elements, high-frequency devices, high-temperature operating devices, and the like. Hereinafter, a Schottky diode in which an SiC epitaxial growth layer is provided on a SiC substrate will be described as an example of a conventional semiconductor device proposed so far.
[0005]
FIG. 8 is a sectional view showing the structure of a conventional Schottky diode. As shown in the figure, a conventional Schottky diode is provided on an SiC substrate 181, an epitaxial growth layer 182 containing an n-type impurity, provided on an upper surface of the SiC substrate 181, and provided on an epitaxial growth layer 182 and Ni ( A Schottky electrode 184 made of nickel), an upper electrode 186 provided on the Schottky electrode 184 and having a laminated structure of Ti (titanium) and Au (gold), and an upper portion of the epitaxial growth layer 182 by ion implantation. , B (boron) or the like. In the conventional Schottky diode, an ohmic electrode 185 made of Ni is provided on the back surface of the SiC substrate 181, and a lower electrode 187 having a laminated structure of Ti and Au is provided on the back surface of the ohmic electrode 185. I have. As the SiC substrate 181, for example, a 4H-SiC substrate having a thickness of about 400 μm and an n-type ({0 0 0 1) off surface as an upper surface is used. The upper electrode 186 and the lower electrode 187 are necessary for providing wiring such as aluminum on the anode electrode of the semiconductor device or for fixing the semiconductor device to the lead frame using solder. Has nothing to do. By selecting an appropriate film thickness and impurity concentration of the epitaxial growth layer 182 made of SiC, a rectifier having a forward current of several amperes or more, a reverse breakdown voltage of 600 V or more, and sometimes 1000 V or more can be obtained. In a vertical semiconductor device as shown in FIG. 8, it is common to provide electrodes on the upper surface of the epitaxial growth layer 182 and on the rear surface of the SiC substrate 181 in order to increase the drive current.
[0006]
Next, a method of manufacturing a conventional Schottky electrode and a resin-sealed semiconductor device having the Schottky electrode will be described.
[0007]
9A to 9C and 10A to 10C are cross-sectional views illustrating a method for manufacturing a resin-encapsulated semiconductor device including a conventional Schottky diode.
[0008]
First, in the step shown in FIG. 9A, a SiC substrate 181 (4H-SiC substrate) containing an n-type impurity having a thickness of about 400 μm and a diameter of 2 inches is prepared. Next, an epitaxial growth layer 182 made of SiC containing an n-type impurity is formed on the upper surface of the SiC substrate 181 by a CVD method or the like.
[0009]
Next, in the step shown in FIG.₂After forming a mask made of, p-type impurity ions such as boron are implanted. Next, after removing the mask, the substrate is subjected to a high heat treatment at 1500 ° C. or higher to activate the implanted ions. By this process, an impurity implantation region 183 is formed. This impurity implantation region 183 functions as a guard ring for preventing electric field concentration.
[0010]
Next, in the step shown in FIG. 9C, for example, Ni is deposited on the entire back surface of the SiC substrate 181 and subsequently, a heat treatment at about 1000 ° C. is performed to form an ohmic electrode 185.
[0011]
Next, in the step shown in FIG. 10A, Ni is deposited on the upper surface of the epitaxial growth layer 185 and then patterned to form a Schottky electrode 184 whose both ends overlap the impurity implantation region 183. Note that in FIG. 9C, the ohmic electrode 185 is formed before the Schottky electrode 184 is formed. If a heat treatment is performed after the formation of the Schottky electrode 184, the Schottky junction changes to an ohmic junction. This is because there are cases.
[0012]
Next, in a step shown in FIG. 10B, an upper electrode 186 is formed by stacking and patterning Ti and Au on the Schottky electrode 184. Then, a lower electrode 187 is formed by laminating Ti and Au on the back surface of the ohmic electrode 185.
[0013]
Thereafter, the wafer-shaped substrate is divided to produce a semiconductor chip as shown in FIG.
[0014]
Next, in the step shown in FIG. 10C, after the semiconductor chip is fixed to the upper surface of the lead frame using the solder 201, the upper electrode 186 and the anode 204 of the lead frame are connected by the metal wire 203. Next, by sealing the upper surfaces of the semiconductor chip, the wires 203 and the lead frame 202 with the resin 205, a resin-sealed semiconductor device can be manufactured.
[0015]
[Problems to be solved by the invention]
The above-mentioned conventional Schottky diode has higher withstand voltage than a semiconductor device made of Si. In such a power device, since the current during driving is large, it is required to reduce the power loss.
[0016]
However, the conventional semiconductor device has a high on-resistance and cannot sufficiently exhibit the excellent characteristics of SiC. This is a problem common to not only Schottky diodes but also vertical power devices such as pn diodes and vertical MISFETs, in which current flows from the top surface to the back surface of the device or in the reverse direction.
[0017]
An object of the present invention is to provide a semiconductor device using an SiC substrate and further reducing the on-resistance, and a method for manufacturing the same.
[0018]
[Means for Solving the Problems]
The semiconductor device of the present invention includes an SiC substrate having a whole rear surface cut off, and a semiconductor layer made of a semiconductor provided on an upper surface of the SiC substrate. In operation, carriers pass through the SiC substrate and the semiconductor layer. And run vertically.
[0019]
With this structure, the thickness of the SiC substrate is reduced, so that the resistance in the vertical direction (perpendicular to the substrate surface) is significantly reduced as compared with a conventional semiconductor device.
[0020]
When the thickness of the SiC substrate is 250 μm or less, the on-resistance during operation can be reduced to a level that cannot be achieved by a semiconductor device using a conventional SiC substrate.
[0021]
More preferably, the thickness of the SiC substrate is 200 μm or less.
[0022]
An electrode made of metal is provided above the semiconductor layer, and a lower electrode made of metal is provided on the back surface of the SiC substrate in ohmic contact with the SiC substrate. A reduced vertical semiconductor device is obtained.
[0023]
The lower electrode preferably includes one material selected from aluminum, titanium, nickel, tungsten, chromium, molybdenum, and silver.
[0024]
The epitaxial growth layer is provided on the ({0} 0} 0-1) carbon surface of the SiC substrate, and the lower electrode is provided on the ({0} 0} 1) silicon surface of the SiC substrate. In particular, in the case of a Schottky diode or a pn diode, an ohmic contact with the lower electrode can be formed without performing a high heat treatment at 1000 ° C. or more.
[0025]
A method of manufacturing a semiconductor device according to the present invention includes an SiC substrate, a semiconductor layer provided on the SiC substrate, an upper electrode provided above the semiconductor layer, and an ohmic electrode provided on a back surface of the SiC substrate. A method for manufacturing a semiconductor device comprising a lower electrode serving as an electrode and
The method includes a step (a) of forming the upper electrode, and a step (b) of reducing the thickness of the SiC substrate after the step (a).
[0026]
According to this method, the semiconductor device in which the resistance of the substrate portion is reduced and the on-resistance is reduced can be manufactured.
[0027]
Since the method further includes the step (c) of forming the lower electrode after the step (b), the upper electrode is manufactured earlier than the lower electrode, so that the step of thinning the SiC substrate is performed after the formation of the upper electrode. Will be able to do it. Therefore, the number of steps when the substrate is thin can be reduced, and the risk of warpage or breakage of the substrate can be reduced. In addition, since the step of thinning the SiC substrate does not affect the alignment of the upper electrode, patterning can be favorably performed when forming the upper electrode.
[0028]
After the step (c), a step (d) of manufacturing the semiconductor chip by separating the SiC substrate and the semiconductor layer, and after the step (d), the semiconductor chip is mounted on a lead frame. And (e) forming an ohmic junction between the SiC substrate and the lower electrode by performing a heat treatment. In the step (c), the number of steps can be reduced by omitting the heat treatment step. Therefore, the manufacturing cost can be reduced and the yield of the device can be improved.
[0029]
The semiconductor layer is provided on the ({0} 0} 0-1) carbon surface of the SiC substrate, and in the step (c), the lower electrode is provided on ({0} 0} 0} 1 silicon of the SiC substrate. Since the lower electrode can be an ohmic electrode without performing a high heat treatment at 1000 ° C. or more, the upper electrode can be formed earlier than the lower electrode. As a result, the thickness of the SiC substrate can be reduced after the formation of the upper electrode.
[0030]
By further including a step (f) of forming a groove for separating each element in the semiconductor layer, element separation is surely performed, and the semiconductor chip can be easily divided into semiconductor chips by using this groove. it can. Further, since the groove is formed on the substrate, defects such as cracks generated during the manufacturing process can be stopped at the groove. That is, the yield can be improved.
[0031]
It is preferable that the depth of the groove is 1 μm or more.
[0032]
When the thickness of the SiC substrate is less than 250 μm, a semiconductor device having lower on-resistance than a conventional semiconductor device can be manufactured.
[0033]
In particular, the thickness of the SiC substrate is preferably 200 μm or less.
[0034]
BEST MODE FOR CARRYING OUT THE INVENTION
There are various resistance components of a semiconductor device, such as a contact resistance between a semiconductor layer and an electrode, a resistance of a semiconductor layer, and a resistance of a SiC substrate itself. In a conventional semiconductor device, since the thickness of the SiC substrate is as large as 400 μm, the resistance of the SiC substrate occupies a large part of the resistance component. Therefore, as a result of the study, the present inventors have aimed at reducing the resistance of the SiC substrate.
[0035]
As a direct method for reducing the resistance of the SiC substrate, it is conceivable to reduce the thickness of the SiC substrate. Although a substrate having a thickness of about 250 μm is commercially available, even if it is used, it cannot be said that the resistance value is sufficiently low. Therefore, the present inventors polished, sandblasted, and reactive ion etched the thickness of the SiC substrate. (RIE) and the like. Thus, by making the thickness of the SiC substrate less than, for example, 250 μm, the resistance value of the SiC substrate could be reduced to a required level or less. Furthermore, when the thickness of the SiC substrate was 200 μm or less, the resistance value could be further reduced significantly. Since a substrate is used in any semiconductor device, the on-resistance of almost all vertical semiconductor devices can be reduced by thinning the substrate.
[0036]
However, when a high heat treatment at 1000 ° C. or more is performed in a state where the substrate is made thin, phenomena such as displacement of a position where a photoresist is formed due to warpage of the substrate may be observed. Such a high heat treatment is necessary when forming an ohmic electrode or activating an impurity in a semiconductor device manufacturing process. Further, by making the SiC substrate thinner, breakage and unexpected cracks are more likely to occur in the substrate. Therefore, it was considered necessary to provide a method for sufficiently reducing the thickness of the SiC substrate.
[0037]
Therefore, for example, a method of reducing the thickness of the SiC substrate after high heat treatment has been studied in order to prevent the substrate from being warped and cracked in the manufacturing process of the Schottky diode.
[0038]
In this examination stage, the present inventors focused on the plane orientation of the SiC substrate. SiC substrates such as the ({0} 0} 0} 1) 4H-SiC substrate include a Si (silicon) surface and a C (carbon) surface, and the semiconductor is usually formed with the Si surface on which an epitaxial growth layer is easily formed on the upper surface. The device is manufactured. If a heat treatment at 1000 ° C. or more is performed after depositing a metal such as Ni on the Si surface, ohmic contact between the Ni and the substrate occurs. Therefore, in the conventional Schottky diode manufacturing process, the shot shown in FIG. The step of forming the key electrode had to be placed after the step of forming the ohmic electrode of FIG.
[0039]
Therefore, the inventors of the present application tried to manufacture a Schottky diode with the C surface as the upper surface and the Si surface as the lower surface. As a result, an ohmic electrode can be easily formed on the Si surface without high-temperature treatment, and a Schottky electrode can be easily formed on the C surface. Therefore, the Schottky electrode can be formed before the ohmic electrode. It turned out to be possible. According to this method, the thickness of the SiC substrate can be reduced after the Schottky electrode is formed on the substrate, and it is not necessary to raise the temperature to 1000 ° C. or more in the step of forming the ohmic electrode.
[0040]
In the following embodiments, a semiconductor device formed using this method will be described.
[0041]
(1st Embodiment)
FIG. 1 is a sectional view showing the structure of the Schottky diode according to the first embodiment of the present invention. Many such semiconductor elements may be integrated on a semiconductor chip mounted on one resin-encapsulated semiconductor device. Here, one Schottky diode will be described.
[0042]
The features of the Schottky diode of the present embodiment are that the thickness of the SiC substrate 11a is as thin as 200 μm, and that the Schottky electrode 14 is provided on the C-plane side of the SiC substrate 11a.
[0043]
As shown in FIG. 1, the Schottky diode of the present embodiment has a thickness of about 200 μm, an SiC substrate 11a containing an n-type impurity, and an n-type n-type of about 10 μm provided on the upper surface of the SiC substrate 11a. An epitaxial growth layer 12 made of SiC, an impurity implantation region 13 provided by implanting boron into the upper portion of the epitaxial growth layer 12, and an upper surface of the epitaxial growth layer 12 with both ends overlapping the impurity implantation region 13. A first electrode layer 18 provided as described above, and a second electrode layer 19 provided on the entire back surface of the SiC substrate 11a.
[0044]
As the SiC substrate, a (0 0 0 1) substrate made of 4H—SiC containing nitrogen is used, and (0 0 0-1) (read as “0001 bar”) in the (11-20) direction from the C plane. The surface with an 8 ° off angle is the upper surface, and the Si surface is the rear surface. The resistivity of the SiC substrate 11a is 0.02 Ω · cm.
[0045]
The epitaxial growth layer 12 contains 1 × 10¹⁶cm^-3It is contained at a concentration of.
[0046]
The first electrode layer 18 is in Schottky contact with the epitaxial growth layer 12 and has a thickness of about 200 nm made of Ti made of Ti, and is provided on the Schottky electrode 14 and made of Au having a thickness of about 3 μm. And an upper electrode 16. The size of the Schottky electrode 14 is, for example, 0.63 mm × 0.63 mm, and each of the Schottky electrodes 14 overlaps the impurity implantation region 13 by about 15 μm. The second electrode layer 19 is in ohmic contact with the back surface of the SiC substrate 11a and is provided on the back surface of the ohmic electrode 15 made of Al (aluminum) having a thickness of 400 nm and Au having a thickness of 400 nm. And a lower electrode 17 composed of
[0047]
Next, the resistance component of the Schottky diode of the present embodiment will be described.
[0048]
The ON resistance Ron when the Schottky diode of the present embodiment operates is
R_on= R_sub+ R_epi+ R_cont+ R_other
Is represented by Where R_subIs the resistance of the SiC substrate 11a, R_epiIs the resistance of the epitaxial growth layer 12, R_contIs the contact resistance generated between each member, R_otherAre other resistance components including the resistance of the lead frame and the wire. The contact resistance includes resistance generated by solder at the interface between the SiC substrate 11a and the ohmic electrode 15 and the interface between the lower electrode 17 and the lead frame. Note that R_subAnd R_epiIs a resistance component in the vertical direction in FIG. 1, that is, the direction perpendicular to the substrate surface.
[0049]
The dominant of the above-mentioned resistance components is R_subAnd R_epiIt is. The 4H—SiC substrate exemplified in the present embodiment exhibits anisotropy in electrical conductivity in a direction parallel to and perpendicular to the substrate surface. Considering this, R_subAnd R_epiIn the conventional Schottky diode 180 shown in FIG. 8, when the thickness of the SiC substrate is 400 μm, R_subIs about 0.7mΩcm², R_epiIs about 0.8mΩ · cm²It becomes.
[0050]
On the other hand, in the Schottky diode of the present embodiment, since the thickness of the SiC substrate is thin, when the thickness of the substrate is 200 μm, for example, R_subIs about 0.35mΩcm²It becomes. That is, by making the substrate thinner, the resistance of the portion made of SiC can be reduced by 20% or more. Further, according to the method for manufacturing a Schottky diode described later, the thickness of the SiC substrate can be reduced to 200 μm or less, so that the resistance component of the element can be further reduced.
[0051]
The breakdown voltage of the Schottky diode of the present embodiment is almost the same as the conventional one. This is because the thickness of the epitaxial growth layer 12 that determines the breakdown voltage is almost the same in the present embodiment between the Schottky diode of the present embodiment and the conventional one. Therefore, in the Schottky diode of the present embodiment, the resistance component is reduced without sacrificing the breakdown voltage. For this reason, conduction loss is also reduced.
[0052]
In the present embodiment, the example in which the epitaxial growth layer 12 is made of SiC has been described. However, the epitaxial growth layer 12 may be made of Si or another semiconductor.
[0053]
Next, a method for manufacturing the Schottky diode of the present embodiment and a semiconductor chip on which the Schottky diode is integrated will be described.
[0054]
2A to 2C and 3A to 3C are cross-sectional views illustrating a method of manufacturing the Schottky diode according to the present embodiment. However, in order to simplify the description, a step of forming an alignment key for mask alignment and a step of forming an interlayer insulating film are omitted.
[0055]
First, in the step shown in FIG. 2A, the SiC substrate 11 is prepared. Specifically, a 4H-SiC substrate having a top surface with an off angle of about 8 degrees in the (11-20) direction from the ({0 0} 0-1) C plane is prepared. Then, the upper surface of the SiC substrate 11 is sufficiently cleaned. The SiC substrate 12 is, for example, a wafer having a thickness of 400 μm and a diameter of 2 inches. In the present embodiment, one of Schottky diodes provided on the wafer will be described.
[0056]
Next, in the step shown in FIG. 2B, n-type impurities are contained on the SiC substrate 11 by a CVD method using propane gas as a carbon source gas, silane gas as a silicon source gas, and hydrogen as a carrier gas. An epitaxial growth layer 12 made of 4H—SiC is formed. The thickness of the epitaxial growth layer 12 is about 10 μm, and for example, nitrogen is used as the n-type impurity. Here, the upper surface of the epitaxial growth layer 12 is also a ({0 0 0-1) C plane.
[0057]
Subsequently, surface treatment of the epitaxial growth layer 12 is performed by keeping the upper surface of the substrate in a hydrogen atmosphere.
[0058]
Next, in the step shown in FIG. 2C, an SiO 2 layer having a thickness of about 600 nm is formed on the epitaxial growth layer 12.₂After the film is formed, a pattern is formed by photoresist, and SiO₂Etch the film. Thus, a 0.6 mm × 0.6 mm dummy mask 21 is formed on the epitaxial growth layer 12.
[0059]
Next, p-type impurities such as boron ions are implanted into the upper surface side of the epitaxial growth layer 12 using the dummy mask 21 as a mask. An implantation region 13 is formed. The ion implantation conditions at this time are as follows: the implantation angle is 0 °, the implantation temperature is 500 ° C., the implantation energy is 30 keV, and the implantation amount is 1 × 10 5^Fifteenatoms / cm².
[0060]
Thereafter, the substrate is placed in a heating furnace, and heat treatment is performed at 1100 ° C. for 90 minutes in a nitrogen atmosphere. Thereby, the impurities contained in impurity implantation region 13 are activated.
[0061]
Next, after removing the dummy mask 21 by etching using buffered hydrofluoric acid, an electrode layer composed of a Ti layer having a thickness of about 200 nm and Au having a thickness of 100 nm is formed on the epitaxial growth layer 12 in order. By forming this Au layer, the subsequent Au plating process can be easily performed. Incidentally, this Au layer becomes a part of the upper electrode 16 later. Next, after forming a photoresist pattern, Au plating is performed to deposit about 3 μm thick Au. Subsequently, after removing the resist, the unplated portion of the Au film is removed by etching, and a part of Ti is also removed by etching. Thereby, the Schottky electrode 14 made of Ti having a size of 0.63 mm × 0.63 mm and the upper electrode 16 made of Au provided on the Schottky electrode 14 are provided on the upper surface of the epitaxial growth layer 12. Are respectively formed.
[0062]
Next, in the step shown in FIG. 3B, the back surface of the SiC substrate 11 is polished until the thickness of the substrate becomes about 200 μm. The polished substrate is hereinafter referred to as a SiC substrate 11a. The polishing may be performed until the thickness of the SiC substrate becomes 200 μm or less.
[0063]
Next, in the step shown in FIG. 3C, after sufficiently cleaning the back surface of the SiC substrate 11a, an ohmic electrode 15 made of Al having a thickness of about 200 nm and an ohmic electrode 15 of about 400 nm are formed on the entire back surface of the SiC substrate 11a. And the lower electrode 17 made of Au. Subsequently, heat treatment of the substrate is performed in a nitrogen atmosphere at 300 ° C. for 5 minutes to stabilize the Schottky electrode 14 and the ohmic electrode 15.
[0064]
In the method of the present embodiment, since the ohmic electrode 15 is formed on the Si surface of the SiC substrate that is easily in ohmic contact with the metal, it is necessary to form the ohmic electrode without performing a heat treatment at 1000 ° C. or more after the electrode is formed. Can be.
[0065]
Next, the wafer-shaped substrate on which a large number of Schottky diodes are formed as shown in FIG. 3C is divided into, for example, 1 mm square semiconductor chips (not shown).
[0066]
Through the above steps, the Schottky diode of the present embodiment is manufactured.
[0067]
According to the method of manufacturing the Schottky diode of the present embodiment, the SiC substrate 11 is polished after the step of forming the Schottky electrode that requires patterning. Therefore, when the etching mask is formed, the SiC substrate 11 may be warped. Mask displacement is less likely to occur. Further, the probability that the substrate is damaged during the manufacturing process can be reduced as compared to the case where a SiC substrate having a thickness of 200 μm is used from the beginning.
[0068]
Further, in the method of manufacturing the Schottky diode according to the present embodiment, the reason why the SiC substrate 11 can be polished after the step of forming the Schottky electrode shown in FIG. 3A is that the ohmic electrode 15 is formed on the Si surface. To do that. By forming the ohmic electrode 15 on the Si surface of the SiC substrate, it becomes possible to make ohmic contact between the SiC substrate 11a and the ohmic electrode 15 without performing a high heat treatment at 1000 ° C. or higher. As a result, the ohmic electrode 15 can be formed after the formation of the Schottky electrode 14, so that the SiC substrate 11 can be polished immediately before the step of forming the ohmic electrode 15. As in the present embodiment, the contact resistance between the ohmic electrode 15 and the SiC substrate 11a may be larger in the case of processing at 300 ° C. for 5 minutes than in the case of processing the substrate at 1000 ° C. Since the size of the ohmic electrode 15 is large, the reduction in resistance due to the thinning of the SiC substrate is greater and does not pose a problem.
[0069]
As described above, in the Schottky diode manufactured by the method of the present embodiment, the resistance of the portion made of SiC is reduced by thinning the substrate. Further, since the substrate is thin, it is easy to divide the semiconductor chip from the wafer.
[0070]
In the method of manufacturing the Schottky diode according to the present embodiment, before the step of forming the ohmic electrode 15 shown in FIG. 3C, the back surface of the SiC substrate 11a is subjected to impurity implantation or surface treatment such as plasma treatment. Thereby, an ohmic junction can be more easily formed.
[0071]
In the Schottky diode of the present embodiment, an example is shown in which the epitaxial growth layer 12 is made of SiC. Instead of this, a material that can be deposited on the SiC substrate, such as Si, GaN (gallium nitride), or diamond, is used. Can be used. Further, it is not limited to the epitaxial growth layer, but may be in any crystalline state of amorphous or polycrystalline.
[0072]
In the present embodiment, the Schottky electrode is made of Ti and the ohmic electrode is made of Al. However, any metal may be used as long as it can form a Schottky junction and an ohmic junction on each surface. As a specific example of the ohmic electrode, a metal having a lower work function than Ni is preferable, and it is preferable to include aluminum, titanium, tungsten, chromium, molybdenum, silver, and these. Of course, Ni can also be used. Further, the Schottky electrode 14 may also contain other metal such as Ni, in addition to Ti.
[0073]
In this embodiment, a substrate made of a polytype such as 6H-SiC, 15R-SiC, or 3C-SiC may be used as the SiC substrate in addition to 4H-SiC.
[0074]
Further, in the present embodiment, an example has been described in which the ohmic electrode is formed on the n-type ({0 0 0Ｓｉ1)) Si surface, but the ohmic electrode can be formed without breaking the Schottky electrode and other components. For example, a plane other than the ({0 0 0 1) Si plane may be used. The conductivity type of the SiC substrate used may be not only n-type but also p-type.
[0075]
In the Schottky diode of the present embodiment, the size of each electrode or member is not particularly limited. The thickness of the SiC substrate prepared in the step shown in FIG. 2A is 400 μm, but a 250 μm-thick SiC substrate is commercially available and can be used.
[0076]
In the Schottky diode of the present embodiment, the thickness of the SiC substrate is 200 μm or less, but if the thickness is less than 250 μm, the on-resistance can be reduced as compared with the conventional Schottky diode.
[0077]
In the method of manufacturing the Schottky diode of the present embodiment, it is preferable to provide a groove extending from the epitaxial growth layer 12 including the impurity-implanted region 13 to the upper part of the SiC substrate 11.
[0078]
FIGS. 4A to 4C are cross-sectional views showing a plurality of Schottky diodes on a SiC substrate in the manufacturing process of the Schottky diode of the present embodiment. This figure shows an example in which a groove is provided between each Schottky diode at the time of the step of forming the Schottky electrode 14 shown in FIG. The groove is provided in both the direction from the front to the back of the paper and the lateral direction. When dividing the semiconductor chip into semiconductor chips, the semiconductor chip is divided from a target groove portion among a large number of grooves.
[0079]
FIG. 4A shows a step of forming the Schottky electrode 14 as in FIG. In the Schottky diode of the present embodiment, each Schottky diode formed on the wafer is element-isolated by a groove 41 reaching the upper part of the SiC substrate 11. The groove 41 may be provided by reactive ion etching (RIE), or may be a physical scribe line.
[0080]
Next, the SiC substrate 11 is polished in the step shown in FIG. Then, after the ohmic electrode 15 and the lower electrode 17 are formed in the step shown in FIG. 4C, the substrate is subjected to a heat treatment.
[0081]
After that, the substrate is divided along the groove 41 at a desired position, and a semiconductor chip having many Schottky diodes is manufactured.
[0082]
By providing the grooves 41 for separating the respective Schottky diodes as in the example shown here, good element isolation can be achieved, and the wafer can be easily divided along the grooves, so that the semiconductor chips can be easily manufactured. You can also. The step of providing the groove 41 may be performed at any time before dividing the wafer, but is preferably performed before polishing the SiC substrate. Since the groove 41 is formed before the polishing of the SiC substrate, when the substrate is damaged such as a crack, the damage can be stopped at the groove. That is, according to this method, it is possible to reduce the defective rate of the element due to cracks or the like.
[0083]
Further, the groove 41 may reach the upper part of the SiC substrate 11a, but even if it is as deep as the epitaxial growth layer 12, element isolation can be performed without any problem. However, it is preferable that the depth of the groove 41 be 1 μm or more and reach the upper part of the SiC substrate 11a in order to achieve good element isolation and easily divide the chip into chips.
[0084]
In this embodiment, the Schottky diode in which the thickness of the SiC substrate is reduced has been described. However, even in the case of other vertical devices such as a pn diode and a vertical MISFET, the on-resistance is greatly reduced by reducing the thickness of the SiC substrate. can do.
[0085]
In the Schottky diode according to the present embodiment, the SiC substrate 11 may be entirely polished by making the epitaxial growth layer 12 sufficiently thick. In general, the epitaxial growth layer has better crystallinity than the substrate, so that an improvement in breakdown voltage or the like may be expected in some cases.
[0086]
(Second embodiment)
As a second embodiment of the present invention, a resin-sealed semiconductor device on which a semiconductor chip having an element such as a Schottky diode described in the first embodiment is mounted will be described.
[0087]
FIGS. 5A to 5C are cross-sectional views illustrating a mounting process of a semiconductor chip having a Schottky diode. Here, the reference numerals of the respective members are the same as in the first embodiment.
[0088]
First, in the step shown in FIG. 5A, a semiconductor chip divided from a wafer and provided with a number of Schottky diodes is prepared.
[0089]
That is, dicing is performed after the step illustrated in FIG. 3C or FIG. 4C to prepare the semiconductor chip 10 including a number of Schottky diodes.
[0090]
Next, in a step shown in FIG. 5B, a TO-220 type lead frame 51 made of, for example, copper is prepared, and the semiconductor chip 10 is mounted on the upper surface of the lead frame 51.
[0091]
As a specific procedure, first, the lead frame 51 is placed in an inert atmosphere such as nitrogen or argon (Ar), and heated to about 300 ° C. which is equal to or higher than the melting point of gold tin (AuSn) in that state. Subsequently, after the solder 52 made of a gold-tin (AuSn) alloy is placed on the upper surface of the lead frame 51 and melted, the semiconductor chip 10 is placed on the lead frame 51 from the back side. Then, by applying an appropriate pressure from above the semiconductor chip 10, the back surface of the semiconductor chip 10 (the back surface of the lower electrode 17) and the upper surface of the lead frame 51 are bonded. At this time, since the SiC substrate 11a of the semiconductor chip 10 has excellent thermal conductivity, the heating temperature of the lead frame is easily transmitted, and the entire semiconductor chip 10 is efficiently heated. Therefore, by performing this step, it is possible to omit the heat treatment for stabilizing the ohmic electrode and the Schottky electrode described in the first embodiment.
Next, in the step shown in FIG. 5C, the upper electrode 16 and the anode 54 of the lead frame are connected by a wire 53 made of, for example, Al. After that, the upper surfaces of the semiconductor chip 10, the wires 53 and the lead frame 51 are sealed with resin. Then, by dividing the lead frame 51, a resin-sealed semiconductor device can be manufactured.
[0092]
As shown in FIG. 5 (c), the resin-encapsulated semiconductor device manufactured by the above-described process has a plurality of lead frames 51 made of metal and a large number of AuSn solders bonded on the upper surfaces of the lead frames. A semiconductor chip 10 having a Schottky diode, a wire 53 made of Al for connecting an anode 54 that is a part of the lead frame 51 and functions as an external terminal and the upper electrode 16 of the Schottky diode, An upper surface, a sealing resin 55 for sealing the semiconductor chip 10 and the wires 53 are provided.
[0093]
In the resin-encapsulated semiconductor device of the present embodiment, the thickness of the SiC substrate 11a of the semiconductor chip 10 is reduced to about 200 μm. It has been significantly reduced.
[0094]
In the present embodiment, the material of the solder is described as AuSn. However, another material may be used depending on the condition of the element structure and the use environment. In this case, in the step shown in FIG. 5B, the lead frame may be heated to a temperature higher than the melting point of the solder material and lower than the temperature at which the Schottky contact can be maintained.
[0095]
In the resin-encapsulated semiconductor device of this embodiment, the constituent materials of the ohmic electrode 15 and the Schottky electrode 14 are Ti and Al, respectively, and the upper electrode 16 and the lower electrode 17 are Au. The upper electrode 16 may be integrally formed of the same material, or the ohmic electrode 15 and the lower electrode 17 may be integrally formed of the same material. The material of the electrode is not particularly limited as long as it is a metal.
[0096]
Although a semiconductor chip having a Schottky diode was used in the resin-encapsulated semiconductor device of the present embodiment, electrodes are provided on the back surface and the top surface of the substrate, and a current is applied in a direction perpendicular to the substrate surface. Any chip having a flowing vertical semiconductor element can be used. For example, a semiconductor chip having a vertical MISFET, a pn diode, or the like can be a resin-encapsulated semiconductor device with low power loss in the same manner.
[0097]
(Third embodiment)
A pn diode using a SiC substrate will be described as a third embodiment of the present invention.
[0098]
FIG. 6 is a cross-sectional view illustrating the structure of the pn diode of the present embodiment. As shown in the figure, the pn diode 60 of the present embodiment has a thickness of 200 μm or less, an SiC substrate 21 a containing an n-type impurity, and a thickness of about 20 μm provided by epitaxial growth on the upper surface of the SiC substrate 21 a. an n-type SiC layer 61 containing an n-type impurity, and a p-type SiC layer 62 provided on a part of the n-type SiC layer 61 by epitaxial growth and made of SiC having a thickness of about 1.5 μm and containing a p-type impurity. , A first electrode layer 66 made of a metal provided on the p-type SiC layer 62 and provided on both sides of the first electrode layer 66 to cover the upper surfaces of the p-type SiC layer 62 and the n-type SiC layer 61 And an insulating film 63. In the pn diode 60 of the present embodiment, a second electrode layer 29 made of metal is provided on the entire back surface of the SiC substrate 21a. The first electrode layer 66 includes a first ohmic electrode 64 having a thickness of about 200 nm provided on the p-type SiC layer 62 and a thickness of about Au and the like provided on the first ohmic electrode 64. And an upper electrode 65 of 3 μm. The second electrode layer 29 includes a second ohmic electrode 25 made of Ni and having a thickness of about 200 nm, and a lower electrode 27 made of Au and having a thickness of about 400 nm. In the pn diode of the present embodiment, a 4H-SiC substrate having a ({0 0 0} 1) off surface as a main surface is used as the SiC substrate 21a. However, unlike the first embodiment, the ({0 0 0 1) Si surface is the upper surface.
[0099]
In the pn diode of the present embodiment, the thickness of the SiC substrate 21a is 200 μm or less, which is smaller than that of the conventional pn diode, so that the on-resistance during operation can be further reduced.
[0100]
Next, a method for manufacturing the pn diode 60 of the present embodiment will be briefly described.
[0101]
First, an SiC substrate having a thickness of about 400 μm is prepared, and an n-type SiC layer 61 and a p-type SiC layer 62 are sequentially formed on the SiC substrate by a known method such as CVD. Here, a mesa structure as shown in FIG. 6 is formed by RIE.
[0102]
Next, the insulating film 63 is formed by thermal oxidation or CVD, an opening is provided in a part of the insulating film 63, and the first electrode layer 66 is formed by a known technique such as EB vapor deposition.
[0103]
Subsequently, the SiC substrate is polished from the C surface side, which is the back surface, to a thickness of 200 μm or less. Thereafter, the second electrode layer 29 is formed on the back surface of the SiC substrate 21a by a known method such as EB deposition. Next, the substrate is subjected to a heat treatment to make the contact between the first ohmic electrode 64 and the second ohmic electrode 25 and the SiC substrate into ohmic contact.
[0104]
Also in the method for manufacturing a pn diode according to the present embodiment, the first electrode layer 66 is formed before the second electrode layer 29 similarly to the first embodiment, and immediately before the second electrode layer 29 is formed. First, the SiC substrate is polished. With this method, since the heat treatment is not performed in a state where the substrate is thin, it is possible to prevent a positional shift when the first ohmic electrode 64 is formed. Here, Al is often used as a constituent material of the first ohmic electrode 64. However, when heat treatment for obtaining ohmic contact is performed at a high temperature of 1000 ° C. or higher, Al is easily broken, and thus has a melting point higher than that of Al. It is preferable to stack a high metal on Al, for example, Al / Ti or Al / Ni is used. However, the polishing of the SiC substrate may be performed at any point during the manufacturing process. In particular, when it is not necessary to precisely position the first electrode layer 66, the SiC substrate may be polished before the formation of the first electrode layer 66.
[0105]
In the pn diode of the present embodiment, a groove may be provided between adjacent elements as in the case of the Schottky diode. In this case, it is preferable that the groove has a depth reaching the upper part of the SiC substrate 21a as in the case of the Schottky diode, but a certain effect can be obtained if the depth of the groove is 1 μm or more.
[0106]
In the pn diode of the present embodiment, the n-type SiC layer 61 and the p-type SiC 62 are made of SiC, but any material that can be formed on the SiC substrate, such as Si, GaN (gallium nitride), or diamond, is used. be able to.
[0107]
In the present embodiment, a pn diode is described as an example of an element having a reduced thickness of the SiC substrate. However, by reducing the thickness of the SiC substrate by the same method, a vertical MISFET having a reduced on-resistance during operation can be used. Can be made.
[0108]
FIG. 7 is a cross-sectional view showing a part of the structure of the vertical MOSFET in which the thickness of the SiC substrate is reduced. The same members as those of the pn diode in FIG. 6 are denoted by the same reference numerals.
[0109]
As shown in FIG. 7, a vertical MOSFET 70 according to the present invention includes a SiC substrate 21a, an n-type epitaxial growth layer 71 provided on the upper surface of the SiC substrate 21a and made of SiC containing an n-type impurity, and an n-type epitaxial growth layer 71. Implanting p-type impurity ions from the upper surface of n-type epitaxial growth layer 71 and implanting n-type impurity ions into part of p-type impurity implantation region 73 Provided on the n-type epitaxial growth layer 71 and the high-concentration n-type impurity implantation region 72 provided so that both ends overlap the p-type impurity implantation region 73 and the high-concentration n-type impurity implantation region 72.₂And a gate electrode 77 provided on the gate oxide film 76 and a high concentration n-type impurity implanted region provided on the n-type epitaxial growth layer 71 and on both sides of the gate electrode 77. A source electrode 74 in ohmic contact with the gate electrode 72, an interlayer insulating film 78 provided on the gate electrode 77, an upper electrode 75 provided on the source electrode 74, and a drain provided on the back surface of the SiC substrate 21a. An electrode 35 and a lower electrode 37 are provided. The source electrode 74 and the upper electrode 75 constitute a first electrode layer 79.
[0110]
Even in a vertical MOSFET having such a structure, a current flows in a direction substantially perpendicular to the substrate surface. Therefore, by thinning the SiC substrate 21a, the resistance is significantly reduced.
[0111]
In the present embodiment, a DI (Double-implanted) MOS having a planar structure has been described as an example, but a method of polishing the back surface of a substrate is also effective in a UMOSFET having a trench structure. This trench structure is advantageous for reducing the on-resistance.
[0112]
Also, for storage type vertical MOSFETs such as ECFETs and ACCUFETs, thinning the substrate is effective for improving the characteristics of the elements.
[0113]
【The invention's effect】
According to the semiconductor device of the present invention, since the thickness of the SiC substrate is 200 μm or less, the on-resistance of the entire device during operation is smaller than that of the conventional semiconductor device. Further, according to the method of manufacturing a semiconductor device of the present invention, the SiC substrate is polished immediately before forming an electrode on the back surface of the SiC substrate, so that a mask shift or the like due to warpage of the substrate can be prevented.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a structure of a Schottky diode according to a first embodiment of the present invention.
FIGS. 2A to 2C are cross-sectional views illustrating a method of manufacturing the Schottky diode according to the first embodiment.
FIGS. 3A to 3C are cross-sectional views illustrating a method of manufacturing the Schottky diode according to the first embodiment.
FIGS. 4A to 4C are cross-sectional views illustrating a plurality of Schottky diodes on a SiC substrate in a manufacturing process of the Schottky diode according to the first embodiment.
FIGS. 5A to 5C are cross-sectional views illustrating a mounting process of a semiconductor chip according to a second embodiment of the present invention.
FIG. 6 is a sectional view showing a structure of a pn diode according to a third embodiment of the present invention.
FIG. 7 is a cross-sectional view illustrating a structure of a vertical MOSFET as an example of an embodiment of the present invention.
FIG. 8 is a cross-sectional view showing a structure of a conventional Schottky diode.
FIGS. 9A to 9C are cross-sectional views illustrating a method of manufacturing a conventional resin-encapsulated semiconductor device including a Schottky diode.
10A to 10C are cross-sectional views illustrating a method for manufacturing a conventional resin-encapsulated semiconductor device including a Schottky diode.
[Explanation of symbols]
10mm semiconductor chip
11,11a, 21a @ SiC substrate
12,71% epitaxial growth layer
13 impurity implantation region
14 Schottky electrode
15mm ohmic electrode
16, 65, 75 mm upper electrode
17, 37 lower electrode
18, 66, 79} first electrode layer
19, 29, 39} Second electrode layer
25 ° second ohmic electrode
29 Second electrode layer
35 ° drain electrode
41 groove
51mm lead frame
52 solder
53 wire
54 anode
55 sealing resin
60 pn diode
61 n-type SiC layer
62 p-type SiC layer
63 insulating film
64 first ohmic electrode
70mm vertical MOSFET
72 ° high-concentration n-type impurity implantation region
73 p-type impurity implantation region
74 ° source electrode
76 gate oxide film
77 gate electrode
78 interlayer insulation film

Claims (14)

A SiC substrate whose entire back surface is shaved,
A semiconductor layer provided on the upper surface of the SiC substrate,
In operation, a semiconductor device in which carriers travel in a vertical direction through the SiC substrate and the semiconductor layer. The semiconductor device according to claim 1,
A semiconductor device, wherein the thickness of the SiC substrate is 250 μm or less. The semiconductor device according to claim 1, wherein
A semiconductor device, wherein the thickness of the SiC substrate is 200 μm or less. The semiconductor device according to any one of claims 1 to 3,
An electrode made of metal is provided above the semiconductor layer,
A semiconductor device, wherein a lower electrode made of metal is provided on the back surface of the SiC substrate in ohmic contact with the SiC substrate. The semiconductor device according to claim 4,
A semiconductor device, wherein the lower electrode includes one material selected from aluminum, titanium, nickel, tungsten, chromium, molybdenum, and silver. The semiconductor device according to claim 4, wherein:
The semiconductor layer is provided on the (000-1) carbon surface of the SiC substrate,
A semiconductor device, wherein the lower electrode is provided on a (001) silicon surface of the SiC substrate. A semiconductor device comprising a SiC substrate, a semiconductor layer provided on the SiC substrate, an upper electrode provided above the semiconductor layer, and a lower electrode provided on the back surface of the SiC substrate and serving as an ohmic electrode The method of manufacturing
(A) forming the upper electrode;
A method of manufacturing a semiconductor device, comprising: a step (b) of reducing the thickness of the SiC substrate after the step (a). The method for manufacturing a semiconductor device according to claim 7,
A method for manufacturing a semiconductor device, further comprising a step (c) of forming the lower electrode after the step (b). The method for manufacturing a semiconductor device according to claim 8,
After the step (c), a step (d) of manufacturing a semiconductor chip by separating the SiC substrate and the semiconductor layer;
After the step (d), a step (e) of mounting the semiconductor chip on a lead frame and performing a heat treatment to form an ohmic junction between the SiC substrate and the lower electrode is further included.
The method of manufacturing a semiconductor device, wherein the heat treatment step is omitted in the step (c). The method of manufacturing a semiconductor device according to claim 7,
The semiconductor layer is provided on the (000-1) carbon surface of the SiC substrate,
In the step (c), the lower electrode is provided on a (001) silicon surface of the SiC substrate. The method of manufacturing a semiconductor device according to claim 7,
A method for manufacturing a semiconductor device, further comprising a step (f) of forming a groove for separating each element in the semiconductor layer. The method of manufacturing a semiconductor device according to claim 7,
A method for manufacturing a semiconductor device, wherein the depth of the groove is 1 μm or more. The method of manufacturing a semiconductor device according to claim 7,
A method for manufacturing a semiconductor device, wherein the thickness of the SiC substrate is less than 250 μm. The method for manufacturing a semiconductor device according to claim 7, wherein
A method for manufacturing a semiconductor device, wherein the thickness of the SiC substrate is 200 μm or less.

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