JP2011035322A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is suppressed with a decline in mechanical strength and a decline in the yield by chip cracks and has a low on-resistance and a low thermal resistance in a packaged state, and also to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device includes a semiconductor substrate 1, a semiconductor layer 3 formed on the principal plane of the semiconductor substrate 1, an ohmic electrode 12 formed on the backside of the semiconductor substrate 1, and a back electrode 13 that is formed on the backside of the semiconductor substrate 1 with the ohmic electrode 12 between and is formed of a metal material having a thermal conductivity higher than that of the semiconductor substrate 1. A recess 1a is formed in part of the backside of the semiconductor substrate 1. The back electrode 13 fills in the inside of the recess 1a in the backside of the semiconductor substrate 1 and covers at least part of other region than the recess 1a in the backside of the semiconductor substrate 1, via the ohmic electrode 12. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a power semiconductor device made of silicon carbide used for high breakdown voltage and large current.

  A power semiconductor device is a semiconductor element that is used for a purpose of flowing a large current with a high breakdown voltage, and is desired to have a low loss. Conventionally, power semiconductor devices using silicon (Si) substrates have been mainstream, but in recent years, power semiconductor devices using silicon carbide (SiC) substrates have attracted attention and are being developed (for example, patent documents). 1-4).

  Since silicon carbide (SiC) has a dielectric breakdown voltage that is an order of magnitude higher than that of silicon (Si), the reverse breakdown voltage can be maintained even if the depletion layer at the pn junction or the Schottky junction is thinned. It has the characteristics. Therefore, when SiC is used, the thickness of the device can be reduced and the doping concentration can be increased. Therefore, SiC is expected as a material for realizing a power semiconductor device with low on-resistance, high breakdown voltage, and low loss.

JP-A-10-308510 Japanese Patent No. 3773489 Japanese Patent No. 3784393 Japanese Patent No. 352796 Japanese Patent Laid-Open No. 2004-22878 JP 2003-303966 A JP 2006-156658 A

K. Yamashita, et. al. "Normally-off 4H-SiC Power MOSFET with Submicron Gate", ICSCRM 2007, Oct. 19th, 2007, p. 1115-1118

  FIG. 8 is a cross-sectional view schematically showing a semiconductor device having a conventional vertical DMOSFET (Double Diffused MOSFET) structure formed on a silicon carbide substrate. In the DMOSFET of FIG. 8, a power MOSFET element region Re having a vertical DMOSFET structure and a semiconductor guard ring region Rt having an FLR structure are defined. When viewed from the direction perpendicular to the substrate, the semiconductor guard ring region Rt is formed in a region surrounding the power MOSFET element region Re.

  A conventional semiconductor element includes a first conductivity type silicon carbide substrate 101 made of hexagonal silicon carbide, and a first conductivity type formed on the main surface of the silicon carbide substrate 101 and having a dopant concentration lower than that of the silicon carbide substrate 101. Type silicon carbide buffer layer 102 and a first conductivity type silicon carbide drift epi layer 103 formed on the main surface of silicon carbide buffer layer 102 and having a dopant concentration lower than that of silicon carbide buffer layer 102. On the surface layer of the silicon carbide drift epi layer 103, a second conductivity type well region 104 provided by performing an ion implantation method or a diffusion method, and a first conductivity type source region provided inside the well region 104. 105 and a body contact region 106 of the second conductivity type are provided.

  A channel epi layer 107 is provided on silicon carbide drift epi layer 103 sandwiched between two well regions 104. A gate insulating film 108 and a gate electrode 109 are provided on the channel epi layer 107.

  The gate electrode 109 and the gate insulating film 108 are covered with an interlayer insulating film 110. A source / ohmic electrode 115 is formed on the source region 105 and the body contact region 106, and a gate / ohmic electrode 116 a is formed on a part of the gate electrode 109. A drain / ohmic electrode 112 and a back electrode 113 are formed on the back surface of the silicon carbide substrate 101. A pad electrode 116 is formed on the source / ohmic electrode 115, the gate / ohmic electrode 116 a and the interlayer insulating film 110, and a protective insulating film 117 is formed on a part of the pad electrode 116.

In the case of a conventional semiconductor device having a vertical DMOSFET structure, the resistance component of the substrate portion is not negligible among the on-resistances when current flows in the thickness direction of the semiconductor substrate. The thickness of the silicon carbide substrate 101 is, for example, 250 to 350 μm, and the resistivity when the silicon carbide substrate 101 includes the first conductivity type impurity at a high concentration (for example, 8E18 cm ⁻³ ) is about 0.02 Ωcm. The resistance component of silicon carbide substrate 101 is about 0.5 to 0.7 mΩcm ² . Here, 8E18cm ^-3 is the meaning of 8 × 10 ¹⁸ cm ^-3, or less, in the present specification, there is a case where the same notation for the concentration.

Assuming that the on-resistance of the vertical DMOSFET designed for 600 V withstand voltage is 3 mΩcm ² , the resistance component of silicon carbide substrate 101 occupies a large proportion of about 17 to 23% with respect to the entire on-resistance. In order to further reduce the loss of the device, it is important to reduce the resistance component of the silicon carbide substrate 101.

  Hereafter, the content which this inventor examined about patent documents 5-7 is demonstrated.

  In Patent Document 5, a Schottky barrier diode (SBD) having a Schottky electrode on the C surface (front surface) of silicon carbide and an ohmic electrode on the Si surface (back surface) is formed to reduce the on-resistance of the device. A method is disclosed. Since it is easy to form an ohmic electrode without performing high temperature treatment on the Si surface, according to this method, after the silicon carbide substrate is thinned to 200 μm or less, the ohmic junction of the Si surface is kept at a low temperature (300 ° C., 5 minutes). Can be realized. However, when this method is applied to a MOSFET type device, it is not easy to form a thermal oxide film having a high channel mobility on the C plane.

  For silicon substrates, a technology for processing the thickness to the order of several tens of micrometers by polishing and flattening the back surface has been put into practical use. On the other hand, it is not easy to polish and planarize the silicon carbide substrate in a state where the silicon carbide substrate is uniformly and at a high yield and the mechanical strength is maintained. Furthermore, in order to form a low-resistance ohmic electrode on the back surface after planarizing the silicon carbide substrate, a high-temperature heat treatment at around 1000 ° C. is necessary. Have difficulty.

  Patent Document 6 discloses a method in which a part of a silicon carbide substrate is partially thinned by a sandblast method or the like in order to reduce the on-resistance of the device. However, when such a semiconductor element is mounted on a flat metal lead frame, a space is disposed between the thinned portion and the lead frame, and the thermal resistance (θj-c) in the package mounted state is greatly increased. Is expected to increase. SiC has the characteristics that it has high heat resistance and can operate even at high temperatures. In order to take advantage of such material advantages of SiC, the smaller the thermal resistance in the package mounted state, the more advantageous. Thus, in SiC devices, it is very important to reduce not only on-resistance but also thermal resistance at the same time.

  FIG. 58 of Patent Document 7 shows a configuration in which a concave portion and a convex portion are formed on the back surface of the substrate, and the concave portion is embedded with a conductor such as Al or Cu. However, in the semiconductor device disclosed in Patent Document 7, since the conductor is embedded only in the recess and the ohmic electrode is exposed on the top surface of the protrusion, the thermal resistance is sufficiently reduced. It is considered impossible.

  The present invention has been made to solve the above-mentioned problems, and its main purpose is to suppress a decrease in yield due to mechanical strength and chip cracks, and a semiconductor with low on-resistance and thermal resistance in a packaged state. It is to provide an apparatus and a method for manufacturing the same.

  The semiconductor device of the present invention includes a semiconductor substrate, a semiconductor layer formed on the main surface of the semiconductor substrate, an ohmic electrode formed on the back surface of the semiconductor substrate, and the semiconductor substrate via the ohmic electrode. A back electrode made of a metal material having a higher thermal conductivity than the semiconductor substrate, a recess is formed in a part of the back surface of the semiconductor substrate, and the back electrode is the ohmic electrode And filling the inside of the concave portion on the back surface of the semiconductor substrate and covering at least a part of the region other than the concave portion on the back surface of the semiconductor substrate.

  In one embodiment, the metal material has a thermal conductivity of 350 W / (m · K) or more.

  In one embodiment, the corner of the recess has a rounded shape.

  In one embodiment, the back electrode is made of a material selected from the group consisting of silver or copper.

  In one embodiment, the ohmic electrode comprises an alloy layer of nickel, silicon, and carbon or an alloy layer of titanium, silicon, and carbon.

  In one embodiment, the recess is not formed in a region within 100 μm from the outer periphery of the semiconductor substrate.

  In one embodiment, the area occupied by the region where the recess is formed in the region where the back electrode is formed on the back surface of the semiconductor substrate is 50% or more.

  In one embodiment, the thickness of the region other than the recess in the semiconductor substrate is 300 μm or more, and the depth of the recess is 200 μm or more.

  In one embodiment, the semiconductor layer includes a semiconductor element region in which a semiconductor element is disposed and a guard ring region surrounding the semiconductor element region.

In one embodiment, at least a part of a pn junction diode is formed in the semiconductor element region of the semiconductor layer.

In one embodiment, at least a part of a Schottky junction diode is formed in the semiconductor element region of the semiconductor layer.

  In one embodiment, at least a part of a MISFET is formed in the semiconductor element region in the semiconductor layer.

  In one embodiment, at least a part of a JFET is formed in the semiconductor element region in the semiconductor layer.

  In one embodiment, an electrode is provided on the main surface side of the semiconductor layer, and a current flows between the electrode and the back electrode.

  The method for manufacturing a semiconductor device of the present invention includes a semiconductor substrate, a semiconductor layer formed on a main surface of the semiconductor substrate, a first ohmic electrode formed on the back surface of the semiconductor substrate, and the first A method of manufacturing a semiconductor device having a back electrode formed on the back surface of the semiconductor substrate via an ohmic electrode, the step (a) of forming a recess in a part of the back surface of the semiconductor substrate; (B) forming a first metal layer covering the inside of the recess on the back surface of the semiconductor substrate and at least a part of a region other than the recess on the back surface of the semiconductor substrate; Through the metal layer, the back electrode that fills the inside of the recess on the back surface of the semiconductor substrate and covers at least a part of the region other than the recess on the back surface of the semiconductor substrate, A step (c) of forming using a metal material having a higher thermal conductivity than the semiconductor substrate, and an ohmic between the first metal layer and the semiconductor substrate by a first heat treatment after the step (c). And (d) forming the first ohmic electrode by forming a junction.

  In one embodiment, the step (c) includes a second metal layer filling the inside of the recess on the back surface of the semiconductor substrate and covering at least a part of the region other than the recess on the back surface of the semiconductor substrate. After the formation, the back electrode is formed by polishing the second metal layer.

  In a certain embodiment, the said process (a) forms the said recessed part by a sandblasting method or dry etching.

  In one embodiment, the step (b) forms the first metal layer by vapor deposition or sputtering, and the step (c) forms the second metal layer by plating.

  In one embodiment, after the step (c), a second ohmic electrode is formed by performing a second heat treatment after forming a third metal layer on the main surface of the semiconductor layer (e And a step (f) of forming a pad electrode for electrical connection between the second ohmic electrode and the outside.

  In a certain embodiment, the said process (a) forms the said recessed part which has a rounded corner | angular part.

  In one embodiment, the step (c) and the step (e) are performed in an atmosphere containing nitrogen gas or argon gas.

In one embodiment, the first heat treatment in the step (d) and the second heat treatment in the step (e) are performed at a temperature of 800 ° C. or higher and 950 ° C. or lower.

In one embodiment, the polishing in the step (c) is chemical mechanical polishing or mechanical polishing.

  According to the present invention, the resistance component of the substrate portion of the vertical semiconductor element can be reduced by providing the recess on the back surface of the semiconductor substrate and filling the recess with the back electrode having a lower resistance than the semiconductor substrate. Can be reduced. Furthermore, since the thermal conductivity of the back electrode is higher than that of the semiconductor substrate, the thermal resistance in the package mounted state can be reduced. Thereby, low-loss and stable device characteristics can be realized even when used at high temperatures.

  Moreover, the mechanical strength of the semiconductor substrate can be kept high because the back electrode covers the region other than the concave portion on the back surface of the semiconductor substrate. Thereby, the fall of the yield by a chip crack can be avoided. Moreover, the heat dissipation of the back electrode can be further improved by covering the region other than the recesses on the back surface of the semiconductor substrate.

It is sectional drawing which shows typically embodiment of the semiconductor device by this invention. (A) is a graph which shows the result of having calculated the change of ON resistance (Ron) in room temperature by changing the depth of the recessed part 1a in the semiconductor device of embodiment, (b) and (c) are room temperature, It is a graph which shows the result of having calculated the characteristic fluctuation | variation (temperature characteristic) of ON resistance Ron in 150 degreeC and 250 degreeC. (A) is a figure which shows typically the thermal-analysis model for verifying the thermal resistance improvement of the semiconductor device of embodiment, (b)-(d) is the layout of the back surface electrode 13 in a semiconductor chip. It is a top view which shows an example typically. (A) is the ratio of the embedding ratio of the back surface electrode 13 obtained by carrying out the thermal fluid analysis simulation and the junction-case thermal resistance θj-c (° C./W) (when the conventional value is 100%). (B) is a graph showing the relationship between the depth of the recess 1a and the value of the junction-case thermal resistance θj-c (° C./W) ratio. (C) is a graph which shows the relationship between the embedded area ratio of the back surface electrode 13 which has the layout shown to FIG.3 (b) to (d), and (theta) j-c ratio. (A), (b) is a graph which shows the result of the thermal fluid analysis simulation at the time of using a Si chip. (A)-(d) is sectional drawing which shows the manufacturing process of the semiconductor device by this invention. (A)-(d) is sectional drawing which shows the manufacturing process of the semiconductor device by this invention. It is sectional drawing which shows the structure of the conventional semiconductor device typically.

  Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings. In the following drawings, components having substantially the same function are denoted by the same reference numerals for the sake of brevity. In addition, this invention is not limited to the following embodiment.

  FIG. 1 is a cross-sectional view schematically showing the semiconductor device of the first embodiment. In the semiconductor device shown in FIG. 1, a DMOSFET region Re having a vertical DMOSFET structure and a semiconductor guard ring region Rt having an FLR structure are defined. When viewed from the direction perpendicular to the substrate, the semiconductor guard ring region Rt is formed in a region surrounding the DMOSFET region Re.

  The semiconductor device of the present embodiment includes a first conductivity type silicon carbide substrate 1 made of hexagonal silicon carbide, and a first dopant formed on the main surface of the silicon carbide substrate 1 and having a dopant concentration lower than that of the silicon carbide substrate 1. 1 conductivity type silicon carbide buffer layer 2 and a first conductivity type silicon carbide drift epi layer 3 formed on the main surface of silicon carbide buffer layer 2 and having a dopant concentration lower than that of silicon carbide buffer layer 2. .

  In the surface layer of the silicon carbide drift epi layer 3 in the DMOSFET region Re, a second conductivity type well region 4, a first conductivity type source region 5, and a second conductivity type body contact region 6 are provided. . The source region 5 and the body contact region 6 are provided in the well region 4, and the source region 5 surrounds the body contact region 6 when viewed from the direction perpendicular to the substrate.

  A source / ohmic electrode 15 is provided on the body contact region 6 and the source region 5 located around the body contact region 6. The source ohmic electrode 15 is composed of, for example, an alloy layer of nickel, silicon, and carbon or an alloy layer of titanium, silicon, and carbon.

  A plurality of second-conductivity-type semiconductor rings 4a are provided on the surface layer of the silicon carbide drift epi layer 3 in the semiconductor guard ring region Rt.

  In DMOSFET region Re, channel epi layer 7 made of silicon carbide is formed on silicon carbide drift epi layer 3 sandwiched between two well regions 4 and well region 4 and source region 5 on both sides thereof. . A portion of the channel epi layer 7 located on the well region 4 functions as a MOSFET channel.

On the channel epi layer 7, a gate insulating film 8 made of, for example, a silicon oxide film is formed. A gate electrode 9 made of, for example, polysilicon is formed on the gate insulating film 8. A gate-ohmic electrode 16 a is provided on a part of the gate electrode 9.
The gate ohmic electrode 16a is made of, for example, an alloy layer of nickel and silicon or an alloy layer of titanium and silicon. The gate electrode 9 and the gate insulating film 8 are covered with an interlayer insulating film 10.

  The interlayer insulating film 10 is provided with an opening 10a for exposing the source / ohmic electrode 15 and an opening 10b for exposing the gate / ohmic electrode 16a. The interlayer insulating film 10 is covered with a pad electrode 16, and the pad electrode 16 is in contact with the source ohmic electrode 15 and the gate ohmic electrode 16a in the openings 10a and 10b. The pad electrode 16 is made of, for example, aluminum or copper and an alloy layer thereof.

  A recess 1a is provided on the back surface of silicon carbide substrate 1 in DMOSFET region Re. A region other than the recess 1 a on the back surface of the silicon carbide substrate 1 and the recess 1 a on the back surface of the silicon carbide substrate 1 is covered with the drain / ohmic electrode 12. The drain ohmic electrode 12 is, for example, an alloy layer of nickel, silicon, and carbon or an alloy layer of titanium, silicon, and carbon.

  The inside of the recess 1 a on the back surface of the silicon carbide substrate 1 and the region other than the recess 1 a on the back surface of the silicon carbide substrate 1 are covered with a back surface (drain) electrode 13 through the drain / ohmic electrode 12. The back electrode 13 is made of a metal material having a higher thermal conductivity than silicon carbide and a thermal conductivity of 350 W / (m · K) or more. Specifically, the back electrode 13 is preferably a material selected from the group consisting of silver or copper, for example. When back electrode 13 is made of these materials, thermal resistance in the substrate portion is reduced, and soldering when mounting the SiC chip on the package can be facilitated.

  The thickness of the portion of the back electrode 13 that covers the recess 1a is larger than the depth of the recess 1a (more precisely, the value obtained by subtracting the thickness of the drain / ohmic electrode 12 from the depth of the recess 1a). preferable. Since the back electrode 13 is provided in this way, the lower surface of the portion of the back electrode 13 that covers the recess 1a is disposed below the lower (back side) end of the recess 1a. Therefore, the part which covers the recessed part 1a among the back surface electrodes 13 and the part which covers the area | regions other than the recessed part 1a among the back surface electrodes 13 can be made flat. For example, when the depth of the recess 1a is 200 μm, the thickness of the drain / ohmic electrode 12 covering the recess 1a may be 0.2 μm, and the thickness of the back electrode 13 may be 250 μm. On the other hand, the thickness of the portion of back electrode 13 that covers silicon carbide substrate 1 in the region other than recess 1a may be 49.8 μm. By forming the back electrode 13 not only inside the recess 1a but also in a region other than the recess 1a, the entire back surface of the chip can be covered with the single back electrode 13 and heat dissipation is improved. However, the back electrode 13 may be interrupted on the back surface of the chip.

  In order to prevent chipping (chip cracks) in the dicing process during package mounting, it is preferable not to place the recess 1a in a region within 100 μm from the outer peripheral portion of the semiconductor device (chip after dicing). By not forming the recess 1a in this region, it is possible to suppress a decrease in the mechanical strength of the chip.

  Moreover, it is preferable that the back surface electrode 13 is provided in an area of at least 50% or more of the entire back surface area of the semiconductor device. And it is preferable that the part which covers the recessed part 1a among the back surface electrodes 13 has thickness of 200 micrometers or more. When this condition is satisfied, the on-resistance and the thermal resistance in the package mounting state are sufficiently reduced.

  Furthermore, it is preferable that the corner | angular part of the recessed part 1a has a rounded shape (round shape or taper shape). Since the corner portion of the recess 1a has a round shape, the concentration of stress on the corner portion can be suppressed.

In one example of the present embodiment, the first conductivity type is n-type. In the example shown in FIG. 1, the silicon carbide substrate 1 is an n-type SiC semiconductor substrate (n ⁺ SiC substrate), and the silicon carbide buffer layer 2 Are n ⁻ layers, and the silicon carbide drift epilayer 3 is an n ⁻ layer. The well region 4 is a p ⁻ layer, the source region 5 is an n ⁺ layer, and the body contact region 6 is a p ⁺ layer. Note that “+”, “−”, and the like are symbols representing the relative dopant concentration of n-type or p-type.

The channel epi layer 7 of this embodiment is an insulating layer (or substantially an insulating layer) and may be referred to as an “i layer” or a “channel epi i layer”. However, the channel epi layer 7 may be a low-concentration first conductivity type (n ⁻ ) layer, and the channel epi layer 7 may have a concentration change in the depth direction. Good.

The thickness of the silicon carbide substrate 1 is, for example, 250 to 350 μm, and the concentration of the n ⁺ SiC substrate 10 is, for example, 8E18 cm ⁻³ . As silicon carbide substrate 1, a substrate made of cubic silicon carbide can also be used. From the viewpoint of increasing the mechanical strength, the thickness of silicon carbide substrate 1 is preferably 300 μm or more.

SiC buffer layer 2 and SiC drift epi layer 3 are SiC layers epitaxially formed on the main surface of silicon carbide substrate 1. The concentration of the SiC buffer layer 2 is, for example, 6E16 cm ⁻³ . The thickness of the SiC drift epi layer 3 is, for example, 4 to 15 μm, and the concentration thereof is, for example, 5E15 cm ^{−3 to} 2E16 cm ⁻³ .

The thickness of the well region 4 (that is, the depth from the upper surface of the SiC drift epitaxial layer 3) is, for example, 0.5 to 1.0 μm, and the concentration of the well region 4 is, for example, 1.5E18 cm ⁻³ . Further, the thickness of the source region 5 (that is, the depth from the upper surface of the SiC drift epitaxial layer 3) is, for example, 0.25 μm, and the concentration of the source region 5 is, for example, 5E19 cm ⁻³ . The thickness of the body contact layer (p ⁺ layer) 6 is, for example, 0.3 μm, and the concentration thereof is, for example, 2E20 cm ⁻³ . Note that a JFET region is defined in the SiC drift epi layer 3 between the well regions 4 in the DMOSFET region Re, and the length (width) of the JFET region is, for example, 3 μm.

The channel epi layer 7 is an SiC layer formed epitaxially on the SiC drift epi layer 3, and the thickness of the channel epi layer 3 is, for example, 30 nm to 150 nm. The length (width) of the channel region is, for example, 0.5 μm. The gate insulating film 8 is made of SiO ₂ (silicon oxide film) and has a thickness of 70 nm, for example. The gate electrode 9 is made of polysilicon and has a thickness of, for example, 500 nm.

  In the present embodiment, the recess 1a is provided on the back surface of the silicon carbide substrate 1, and the recess 1a is filled with the back electrode 13 having a resistance lower than that of the silicon carbide substrate 1, thereby reducing the resistance component of the silicon carbide substrate 1 as compared with the prior art. be able to. In the DMOSFET of this embodiment, since the current flows in the vertical direction in the silicon carbide substrate 1, the on-resistance of the entire device can be reduced by reducing the resistance component of the silicon carbide substrate 1. Furthermore, since the thermal conductivity of back electrode 13 is higher than that of silicon carbide substrate 1, the thermal resistance in the package mounted state can be reduced. Thereby, low-loss and stable device characteristics can be realized even when used at high temperatures.

  Moreover, since the back surface electrode 13 covers the region other than the recess 1 a on the back surface of the silicon carbide substrate 1, the mechanical strength of the silicon carbide substrate 1 can be kept high. Thereby, the fall of the yield by a chip crack can be avoided. In addition, since the back electrode 13 covers the region other than the recess 1 a on the back surface of the silicon carbide substrate 1, the heat dissipation of the back electrode 13 can be further improved.

FIG. 2A is a graph showing the result of calculating the change in on-resistance (Ron) at room temperature by changing the depth of the recess 1a in the semiconductor device of this embodiment. In FIG. 2A, the horizontal axis indicates the depth of the recess 1a, and the vertical axis indicates the ratio of the ON resistance when the ON resistance Ron (3 mΩcm ² ) of the conventional structure is set to 100%. The breakdown voltage (Vbd) of the conventional structure is designed to be 600 V, and the resistance component of the substrate portion is assumed to be 0.7 mΩcm ² .

  In the structure of the present embodiment, silver is assumed as the material of the back electrode 13, the ratio of the area of the back electrode 13 to the entire area of the chip back surface (chip area ratio) is 89%, and the depth of the recess 1a is 100 to 100. The thickness was 300 μm. As shown in FIG. 2A, in the calculation result of the present embodiment, the value of the ratio of the on-resistance Ron decreases as the depth of the recess 1a increases. The ratio of the on-resistance Ron when the depth of the recess 1a is 300 μm is about 83%. Thus, in the result shown in FIG. 2A, the on-resistance Ron of the present embodiment is reduced to about 17% with respect to the conventional on-resistance.

FIGS. 2B and 2C are graphs showing the result of trial calculation of the characteristic variation (temperature characteristic) of the on-resistance Ron at 150 ° C. and 250 ° C. in addition to the room temperature state. FIG. 2B shows a case where the withstand voltage (Vbd) is designed to be 600 V and the on-resistance Ron is set to 3 mΩcm ² (the element area is about 0.11 cm ² , which is about 27 mΩ) as in FIG. 2A. The trial calculation results are shown. FIG. 2C shows a calculation result when the withstand voltage (Vbd) is designed to be 1400 V and the on-resistance Ron is set to 5 mΩcm ² (element area: 0.11 cm ² , which is about 45 mΩ). In any case, as in FIG. 2A, silver was assumed as the material of the back electrode 13, the chip area ratio was 89%, and the depth of the recess 1a was 300 μm. The resistance component constituting the on-resistance Ron of the device is roughly classified into three components: a component mainly composed of a drift resistor (indicated as “other than channel” in the drawing), a channel resistance component, and a substrate resistance component. Since the resistance component other than the channel and the substrate resistance component generally have a “positive” temperature coefficient, the resistance component of this portion increases as the temperature increases. However, in the case of a SiC-MOSFET, an oxide film formed by thermal oxidation has many interface state densities (Dit), which is one of the factors that reduce channel mobility. At room temperature, this Dit captures many electron and hole carriers. However, when the temperature rises, the trapped carriers are released, channel mobility is improved, and channel resistance component is decreased. In addition, it is known that the temperature coefficient is “negative” (Non-patent Document 1). Based on various examination results, it is assumed that Dit = 6E11-4E13 cm ^−2, and this trial calculation is carried out.

  From the above, it can be seen that Ron of the SiC-MOSFET having the conventional structure has a trade-off relationship between the resistance component other than the channel having the “positive” temperature coefficient and the substrate resistance and the channel resistance having the “negative” temperature coefficient. . In the conventional structure, the substrate resistance increases as the temperature rises, and the influence of the substrate resistance on the entire on-resistance Ron increases as the temperature increases. In the present embodiment, by increasing the substrate resistance by filling the recess 1a with the back electrode 13, the increase in the on-resistance Ron can be suppressed particularly during high temperature operation.

  Next, the result of studying the influence on the thermal resistance (θj−c) in the package mounting state will be described. Here, using thermal fluid analysis simulation, the influence on the thermal resistance was examined using the metal material, layout, thickness (depth), area ratio, and the like of the back electrode 13 as parameters.

  FIG. 3A schematically shows a thermal fluid analysis model assuming a thermal resistance evaluation environment based on the JEDEC standard (JESD51-6). In the thermal fluid analysis model, the semiconductor chip 21 is mounted on the mounting substrate 25 in a state of being mounted on a TO-220 type semiconductor package 22. The semiconductor package is connected to the copper heat sink 24 via the mica 23.

  3B is a plan view showing a layout in which the back electrode 13 is formed in a line shape on the back surface of the semiconductor chip 21, and FIG. 3C is a diagram in which the back electrode 13 is formed in a square shape on the back surface of the semiconductor chip 21. FIG. 3D is a plan view showing a layout in which the back electrode 13 is formed at the center of the back surface of the semiconductor chip 21.

  FIG. 4A shows the ratio of the back electrode 13 embedding ratio and the junction-case thermal resistance θj-c (° C./W) obtained by carrying out the thermal fluid analysis simulation (the conventional value is 100%). It is a graph which shows the relationship with the value of ratio in the case of doing. The value of θj−c ratio was obtained by dividing the temperature on the back side of the semiconductor chip 21 by the amount of heat generated.

  FIG. 4A shows a simulation result of a conventional structure and a structure using silver, copper, and lead as the back electrode 13. The depths of the concave portions of the back electrode 13 were all set to a constant value of 300 μm. As shown in FIG. 4A, it can be seen that when silver or copper is used for the back electrode 13, the θj-c ratio can be reduced as the embedded area ratio increases. When silver or copper is used, the value of the θj-c ratio when the buried area ratio is about 90% is about 5% lower than that of the conventional structure. This is because the thermal conductivity of silver and copper around 100 ° C. (Ag: about 420 W / (m · K), Cu: about 390 W / (m · K)) is the thermal conductivity of SiC (about 290 W / (m Since it is larger than K)), it is considered that the larger the buried area ratio of these metals is, the more the thermal conductivity at the back-embedded electrode 13 portion is improved and the θj-c ratio can be reduced.

  The θj-c ratio in the case of embedding lead (Pb: about 35 W / (m · K)) whose thermal conductivity is lower than that of SiC is also calculated for comparison, but it is 19% or more θj-c than the conventional structure. It has been found that the ratio increases.

  FIG. 4B is a graph showing the relationship between the depth of the recesses obtained by performing the thermal fluid analysis simulation and the value of the ratio of the junction-case thermal resistance θj-c (° C./W). FIG. 4B shows simulation results of a conventional structure, a structure having a recess (hollow) in which metal is not embedded in the back surface of the semiconductor chip, and a structure having a recess in which silver is embedded in the back surface of the semiconductor chip. Show. The embedded area ratio was a constant value of 89%.

  As shown in FIG. 4 (b), in the structure having the concave portion embedded with silver, the θj-c ratio is reduced as the depth of the concave portion is increased, and in the structure having a thickness of 300 μm, it is about 5% of the conventional structure. Has also been reduced.

  On the other hand, the structure having a recess (hollow) in which no metal is embedded on the back surface of the semiconductor chip has a configuration as disclosed in Patent Document 6, and this semiconductor chip is mounted on a flat lead frame. Has been. The θj-c ratio of the structure having a hollow becomes 700% (7 times) or more when θj-c of the conventional structure having no recess on the back surface of the semiconductor chip is 100%. Thus, in this structure, the on-resistance Ron can be reduced, but the θj-c ratio is greatly increased. When considering package mounting, the configuration of Patent Document 6 is disadvantageous particularly in a high temperature use state.

  FIG. 4C is a graph showing the relationship between the embedded area ratio of the back electrode 13 having the layout shown in FIGS. 3B to 3D and the θj-c ratio. In this result, a large difference was not recognized in the value of the ratio θj−c due to the difference in the layout of the back electrode 13.

  For reference, FIGS. 5A and 5B show the results of thermal fluid analysis simulations when Si chips are used. 5A shows the relationship between the embedded area ratio of the back electrode 13 and the θj-c ratio, and FIG. 5B shows the relationship between the depth of the recess and the θj-c ratio. The simulations shown in FIGS. 5A and 5B were performed using the thermal fluid analysis model shown in FIG. 5A and 5B, both a Si chip having a structure (conventional structure) that does not have a recess on the back surface of the semiconductor chip, and a structure in which the recess is formed on the back surface of the semiconductor chip and Ag is embedded in the recess. The simulation result of Si chip | tip which has is shown.

  As shown in FIG. 5A, in the Si chip having a structure in which Ag is embedded in the recess, the embedded area ratio is in the range of 40% to 90%, and the θj-c ratio is about 85% to 76%. It has dropped to near. When the SiC chip is used, the θj-c ratio when the embedded area ratio is in the range of 40% to 90% is about 98% to 95% (FIG. 4A). When the back electrode is embedded, it can be seen that the effect of improving the thermal resistance is greater than that of the SiC chip.

  On the other hand, as shown in FIG. 5B, in the Si chip having a structure in which Ag is embedded in the recess, the θj-c ratio is about 92% to 76% when the depth of the recess is in the range of 100 μm to 300 μm. It has dropped to near. When a SiC chip is used, the θj-c ratio is about 98% to 95% when the depth of the recess 1a is in the range of 100 μm to 300 μm (FIG. 4B). It can be seen that when the back electrode is embedded in the Si chip, the effect of improving the thermal resistance is greater than in the case of the SiC chip. This is because the thermal conductivity of Si (eg, about 120 W / (m · K) around 100 ° C.) is even lower than the thermal conductivity of SiC (eg, around 280 W / (m · K) around 100 ° C.). This is probably because the degree of improvement in thermal conductivity by embedding metal is even greater. Thus, it is also effective to apply the present invention to the Si chip. However, in Si chips, a processing technique for polishing the back surface to the order of several tens of μm has been put into practical use, whereas in SiC, such a technique has not been put into practical use. Furthermore, in order to form a low-resistance ohmic electrode on the back surface after planarizing the SiC substrate, high-temperature heat treatment at around 1000 ° C. is necessary, and it is difficult to carry out such a manufacturing method after the surface electrode is formed. is there. Therefore, it is considered that the significance of applying the present invention to SiC is greater.

  Next, with reference to FIGS. 6A to 6D and FIGS. 7A to 7D, a method for manufacturing the silicon carbide semiconductor device of this embodiment will be described. FIGS. 6A to 6D and FIGS. 7A to 7D are process cross-sectional views for explaining a part of the manufacturing method of this embodiment.

First, a manufacturing method for obtaining the configuration as shown in FIG. As the n ⁺ SiC substrate 1, an n-type 4H—SiC (0001) substrate is prepared. As the n ⁺ SiC substrate 1, for example, a substrate that is 8 ° or 4 ° offcut in the <11-20> direction and has an n-type doping concentration of 1 × 10 ¹⁸ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ is used. .

Next, on the main surface of the n ⁺ SiC substrate 1, by epitaxial growth, for example, an n ⁻ buffer layer 2 having an impurity concentration of 6E16 cm ⁻³ and a thickness of about 4 to 15 μm, and an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ to 1 ×, for example. forming continuously a drift epi layer 3 ^- 10 ¹⁶ cm ^-3, thickness of about a range of 4-15 .mu.m n. During epitaxial growth, thermal CVD may be performed using, for example, silane (SiH ₄ ) and propane (C ₃ H ₈ ) as source gases, hydrogen (H ₂ ) as a carrier gas, and nitrogen (N ₂ ) gas as a dopant gas. .

Then, n ^- on the drift epi layer 3, a predetermined mask defining a well region 4 (e.g., a mask made of an oxide film) provided, for example, by the Al ⁺ ion implantation, n ^- drift A well region (p ⁻ ) 4 having a predetermined depth is formed on the surface layer of the epi layer 3. The ion implantation at this time is performed, for example, by keeping the substrate temperature at 500 ° C. and dividing it into a plurality of energy with energy between 30 keV and 350 keV. The depth of the well region 4 is, for example, 0.5 to 1.0 μm. The surface portion of the n ⁻ drift epi layer 3 located between the adjacent well regions 4 becomes a JFET region. The width of the JFET region of this embodiment is 3 μm, for example.

Next, a predetermined mask for defining the source region 5 is provided, and N ⁺ (nitrogen ions) or P ⁺ (phosphorus ions) are ion-implanted into the surface of the well region (p ⁻ ) 4 to thereby form the source region (n ⁺⁺ ) 5 is formed. The ion implantation is performed, for example, while maintaining the temperature of the substrate at 500 ° C. and dividing into a plurality of energy with energy between 30 keV and 90 keV. The depth of the source region 5 is, for example, 0.25 μm.

Next, a predetermined mask for defining the body contact region 6 is provided, and Al ⁺ (aluminum ions) or B ⁺ (boron ions) are ion-implanted into the surface of the well region (p ⁻ ) 4 to thereby provide body contact. Region (p ⁺ layer) 6 is formed. The ion implantation is performed, for example, by dividing the substrate at a temperature of 500 ° C. and with energy between 30 keV and 150 keV. The depth of the body contact region (p ⁺ layer) 6 is deeper than the depth of the source region (n ⁺⁺ ) 5, for example, 0.3 μm.

Next, the silicon carbide substrate 1 (more precisely, the silicon carbide substrate 1 on which layers such as the n ⁻ buffer layer 2 and the n ⁻ drift epi layer 3 are formed) is at a temperature of 1000 ° C. or higher, for example, around 1700 ° C. The ion-implanted species is activated by heating.

Next, the channel epi layer 7 is formed by epitaxial growth. The channel epitaxial layer 7 in the present embodiment is made of SiC, has an impurity concentration of, for example, about 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁵ cm ⁻³ , and has a thickness of 30 to 150 nm. In this epitaxial growth, for example, thermal CVD is performed using silane (SiH ₄ ) and propane (C ₃ H ₈ ) as source gases, hydrogen (H ₂ ) as a carrier gas, and nitrogen (N ₂ ) gas as a dopant gas. .

Note that nitrogen (N ₂ ) gas may be introduced during the epitaxial growth to increase the impurity concentration of a part of the channel epitaxial layer 7. Further, the surface of the epitaxially grown channel epi layer 7 may be removed by CMP (Chemical Mechanical Polishing). However, the execution of CMP is optional, and it is not necessary to perform CMP.

Next, the channel epi layer 7 is patterned by performing dry etching through a predetermined mask. Thereafter, a gate insulating film (SiO ₂ ) 8 having a thickness of 70 nm, for example, is formed on the patterned channel epi layer 7.

  Next, a gate electrode (poly-Si) 9 is formed on the gate oxide film 8 by using low pressure CVD. Thereafter, the gate electrode 9 is patterned by etching using a predetermined mask.

  Next, for example, a silicon oxide film or a nitride film or a laminated film thereof is deposited to a thickness of about 500 to 1500 nm by CVD, for example, on the silicon carbide substrate 1 (precisely on the drift epi layer 3). ), An interlayer insulating film 10 is formed. The silicon oxide film constituting the interlayer insulating film 10 may contain impurities such as phosphorus and boron. The interlayer insulating film 10 plays a role of electrical insulation between the pad electrode 13 and the gate electrode 9 and prevention of moisture and impurity intrusion into the semiconductor element. In the present embodiment, the interlayer insulating film 10 is formed not only on the entire silicon carbide substrate 1, that is, not only in the DMOSFET region Re but also in the guard ring (FLR) region Rt.

  Further, by performing dry etching by sandblasting or RIE, a part of the back surface of silicon carbide substrate 1 is removed, thereby forming recess 1a. For example, when using silicon carbide substrate 1 having a thickness of 250 to 350 μm, it is preferable to set the depth of recess 1 a to 200 to 300 μm.

  The corner of the recess 1a is preferably round. By making the corner of the recess 1a round, stress concentration on the corner can be alleviated. For example, when the sand blast method is used when forming the recess 1a, the corner of the recess 1a can be tapered. When dry etching is performed when forming the recess 1a, the corner of the recess 1a can be rounded by performing etching while the etching mask is processed into a tapered shape.

  In order to prevent chipping (chip cracks) in the dicing process during package mounting, it is preferable not to place the recess 1a in a region within 100 μm from the outer peripheral portion of the semiconductor device (chip after dicing). By not forming the recess 1a in this region, it is possible to suppress a decrease in the mechanical strength of the chip.

  Through the above steps, the structure shown in FIG. That is, the structure shown in FIG. 6A is completed through the formation of the injection layer, the formation of the gate, the formation of the interlayer insulating film, and the back surface recess formation process.

  Next, as shown in FIG. 6B, the drain ohmic covering the inside of the recess 1a on the back surface of the silicon carbide substrate 1 and the region other than the recess 1a on the back surface of the silicon carbide substrate 1 by EB vapor deposition or sputtering. Contact metal 11 is deposited. The drain-ohmic contact metal 11 is made of nickel or titanium having a thickness of about 100 nm, for example.

  Next, as shown in FIG. 6C, a back electrode 13 made of, for example, silver or copper is formed on the back surface of the drain / ohmic contact metal 11 by electrolytic plating or the like. By depositing back electrode 13 thicker than the depth of recess 1a, back electrode 13 is formed not only inside recess 1a but also in regions other than recess 1a in silicon carbide substrate 1.

Next, as shown in FIG. 6 (d), the drain / ohmic contact metal 11 is reacted with silicon carbide by performing a high temperature heat treatment in a state where the drain / ohmic contact metal 11 is covered with the back electrode 13. A drain-ohmic electrode 12 is formed. The drain / ohmic electrode 12 is made of, for example, an alloy layer of nickel or titanium, silicon, and carbon. The heat treatment for forming the drain-ohmic electrode 12 is performed at 800 ° C. to 950 ° C. in an Ar or N ₂ atmosphere.

  Further, the back surface of the back electrode 13 is flattened by performing CMP (chemical mechanical polishing) or normal mechanical polishing. Considering the back surface joining by solder at the time of package mounting, it is preferable that the back surface of the back electrode 13 be as flat as possible.

  Next, as illustrated in FIG. 7A, an opening 10 a for forming the source / ohmic electrode 15 and an opening 10 b for forming the gate / ohmic electrode 16 a are formed in the interlayer insulating film 10. The openings 10a and 10b may be formed by forming a mask on the interlayer insulating film 10 by lithography and then removing the interlayer insulating film 10 by RIE or the like. Opening 10a exposes body contact region 6 and source region 5, and opening 10b exposes a portion of gate electrode 9 above.

  Next, as shown in FIG. 7B, the body contact region 6 and the source region 5 exposed to the opening 10a, the gate electrode 9 exposed to the opening 10b, and the interlayer are exposed by EB vapor deposition, sputtering, or the like. A metal layer 14 is deposited on the insulating film 10. The metal layer 14 is made of, for example, nickel or titanium having a thickness of 100 nm.

Next, as shown in FIG. 7C, heat treatment is performed to cause the metal layer 14 in the opening 10a to react with silicon carbide, and the metal layer 14 in the opening 10b to react with polysilicon of the gate electrode 9. As a result, the source / ohmic electrode 15 is formed on the source region 5 and the body contact region 6, and the gate / ohmic electrode 16 a is formed on the gate electrode 9. The source ohmic electrode 15 is made of, for example, an alloy layer of nickel or titanium, silicon, and carbon, and the gate ohmic electrode 16a is made of, for example, an alloy layer of nickel, titanium, or silicon. Heat treatment for forming the alloy layer, for example an Ar or N ₂ atmosphere, may be performed at a temperature of 800 ° C. to 950 ° C.. Thereafter, wet etching is performed using a phosphoric acid chemical solution or the like to remove the metal layer 14 that has not reacted with silicon or carbon.

  In the step shown in FIG. 7C, the salicide process may be performed as described above, or other methods may be employed. Specifically, after the metal layer 14 is deposited, a mask is formed on the metal layer 14 by lithography, and then dry etching such as RIE or wet etching using a phosphoric acid chemical solution or the like is performed. May be patterned. In this case, an alloy layer of the metal layer 14 and silicon and carbon may be formed by performing heat treatment after patterning the metal layer 14.

  Thereafter, as shown in FIG. 7D, by depositing and patterning aluminum or an alloy layer thereof, the source ohmic electrode 15 in the opening 10a, the gate ohmic electrode 16a in the opening 10b, and the interlayer A pad electrode 16 is formed on the insulating film 10.

  The aluminum or the alloy layer thereof constituting the pad electrode 16 may be deposited by EB vapor deposition or sputtering. The thickness of the pad electrode 16 is, for example, about 4 μm. As the patterning of the deposited aluminum or its alloy layer, after forming a mask thereon by lithography, dry etching such as RIE or wet etching using a phosphoric acid chemical solution may be performed through the mask. As the pad electrode 16, copper or an alloy layer thereof may be formed by electrolytic plating or the like. A protective insulating film (passivation film) 17 is formed on the pad electrode 16 by plasma CVD. For example, as the protective insulating film 17, a silicon nitride film (p-SiN) having a thickness of 1.5 μm may be formed.

  Further, a mask for forming a gate and a source pad portion is formed on the protective insulating film 17 by lithography, and the protective insulating film 17 is removed by performing dry etching such as RIE using the mask. .

  The vertical power MOSFET having the FLR structure termination guard ring has been described above. However, the present invention can be applied to other termination structures such as a RESURF structure and other power devices such as diodes, IGBTs, and bipolar transistors. It can be suitably used. The present invention can be suitably used not only for power semiconductor devices made of silicon carbide but also for other semiconductor materials such as silicon (Si), gallium nitride (GaN), and diamond.

  The present invention is suitably used for various semiconductor devices that require high breakdown voltage characteristics and reliability. In particular, it is suitably used for a diode or a transistor using a vertical SiC substrate.

DESCRIPTION OF SYMBOLS 1,101 Silicon carbide substrate 1a Concave part 2,102 Silicon carbide buffer layer 3,103 Silicon carbide drift epi layer 4,104 Well region 5,105 Source region 6,106 Body contact region 7,107 Channel epi layer 8,108 Gate insulation Film 9, 109 Gate electrode 10, 110 Interlayer insulating film 10a, 10b Opening 11, 111 Drain / ohmic contact metal 12, 112 Drain / ohmic electrode 13, 113 Back (drain) electrode 14, 114 Source / ohmic contact metal 15, 115 Source / ohmic electrode 16, 116 Pad electrode 16a Gate / ohmic electrode 17, 117 Protective insulating film 21 Semiconductor chip 22 Package (TO-220 type)
23 Mica 24 Copper heat sink 25 Mounting board

Claims (23)

A semiconductor substrate;
A semiconductor layer formed on the main surface of the semiconductor substrate;
An ohmic electrode formed on the back surface of the semiconductor substrate;
Formed on the back surface of the semiconductor substrate through the ohmic electrode, and comprising a back electrode made of a metal material having a higher thermal conductivity than the semiconductor substrate,
A recess is formed in a part of the back surface of the semiconductor substrate,
The back surface electrode is a semiconductor device that fills the inside of the recess on the back surface of the semiconductor substrate via the ohmic electrode and covers at least a part of the region other than the recess on the back surface of the semiconductor substrate.   The semiconductor device according to claim 1, wherein the metal material has a thermal conductivity of 350 W / (m · K) or more.   The semiconductor device according to claim 1, wherein a corner portion of the concave portion has a rounded shape.   The semiconductor device according to claim 1, wherein the back electrode is made of a material selected from the group consisting of silver or copper.   5. The semiconductor device according to claim 1, wherein the ohmic electrode includes an alloy layer of nickel, silicon, and carbon or an alloy layer of titanium, silicon, and carbon.   The semiconductor device according to claim 1, wherein the recess is not formed in a region within 100 μm from the outer periphery of the semiconductor substrate.   7. The semiconductor device according to claim 1, wherein an area occupied by a region where the concave portion is formed in a region where the back electrode is formed on the back surface of the semiconductor substrate is 50% or more.   8. The semiconductor device according to claim 1, wherein a thickness of a region other than the recess in the semiconductor substrate is 300 μm or more, and a depth of the recess is 200 μm or more.   The semiconductor device according to claim 1, wherein the semiconductor layer includes a semiconductor element region in which a semiconductor element is disposed, and a guard ring region surrounding the semiconductor element region.   The semiconductor device according to claim 9, wherein at least a part of a pn junction diode is formed in the semiconductor element region in the semiconductor layer.   The semiconductor device according to claim 9, wherein at least a part of a Schottky junction diode is formed in the semiconductor element region of the semiconductor layer.   The semiconductor device according to claim 9, wherein at least a part of a MISFET is formed in the semiconductor element region in the semiconductor layer.   The semiconductor device according to claim 9, wherein at least a part of a JFET is formed in the semiconductor element region in the semiconductor layer.   The semiconductor device according to claim 1, wherein an electrode is provided on a main surface side of the semiconductor layer, and a current flows between the electrode and the back electrode. A semiconductor substrate; a semiconductor layer formed on a main surface of the semiconductor substrate; a first ohmic electrode formed on a back surface of the semiconductor substrate; and the semiconductor substrate through the first ohmic electrode. A method of manufacturing a semiconductor device having a back electrode formed on a back surface,
Forming a recess in a part of the back surface of the semiconductor substrate (a);
Forming a first metal layer covering the inside of the recess on the back surface of the semiconductor substrate and at least a part of the region other than the recess on the back surface of the semiconductor substrate;
Via the first metal layer, fill the inside of the recess on the back surface of the semiconductor substrate, and cover the back electrode covering at least a part of the region other than the recess on the back surface of the semiconductor substrate. A step (c) of forming using a metal material having a higher thermal conductivity than
After the step (c), the method includes a step (d) of forming the first ohmic electrode by forming an ohmic junction between the first metal layer and the semiconductor substrate by a first heat treatment. A method for manufacturing a semiconductor device.   In the step (c), after forming the second metal layer that fills the inside of the recess on the back surface of the semiconductor substrate and covers at least a part of the region other than the recess on the back surface of the semiconductor substrate, The method for manufacturing a semiconductor device according to claim 15, wherein the back electrode is formed by polishing a second metal layer.   The method of manufacturing a semiconductor device according to claim 15, wherein in the step (a), the concave portion is formed by a sandblast method or dry etching. In the step (b), the first metal layer is formed by vapor deposition or sputtering,
The method of manufacturing a semiconductor device according to claim 16, wherein in the step (c), the second metal layer is formed by plating. After step (c)
Forming a second ohmic electrode by performing a second heat treatment after forming a third metal layer on the main surface of the semiconductor layer; and
The method of manufacturing a semiconductor device according to claim 15, further comprising a step (f) of forming a pad electrode for electrical connection between the second ohmic electrode and the outside.   20. The method of manufacturing a semiconductor device according to claim 15, wherein the step (a) forms the concave portion having a rounded corner portion.   The method of manufacturing a semiconductor device according to claim 19, wherein the step (c) and the step (e) are performed in an atmosphere containing nitrogen gas or argon gas.   The method for manufacturing a semiconductor device according to claim 19, wherein the first heat treatment in the step (d) and the second heat treatment in the step (e) are performed at a temperature of 800 ° C. or higher and 950 ° C. or lower.   The method of manufacturing a semiconductor device according to claim 16, wherein the polishing in the step (c) is chemical mechanical polishing or mechanical polishing.

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