JP7367341B2 - Semiconductor device and semiconductor device manufacturing method - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

In recent years, silicon carbide (SiC) has attracted attention as one of the semiconductor materials that can replace silicon (Si). Silicon carbide has a band gap that is about three times larger than that of silicon, so it has high withstand voltage characteristics. By using a semiconductor device that operates with majority carriers, on-resistance can be reduced and excellent operating characteristics at high temperatures can be obtained. Furthermore, since the thermal conductivity of silicon carbide is higher than that of silicon, a cooling device for cooling a semiconductor device can be made smaller. Silicon carbide having such characteristics is expected to be applied to power semiconductor devices, for example.

Single-crystal silicon carbide substrates are manufactured using, for example, a sublimation method, but silicon carbide substrates manufactured using this sublimation method have defects called basal plane dislocations (BPD). It has been known.

The following will explain, with reference to FIGS. 1(A) to 1(C), that when a silicon carbide substrate of a semiconductor device has basal plane dislocations, deterioration of electrical characteristics over time may be observed. .

As shown in FIG. 1A, semiconductor device 100 includes silicon carbide substrate 110, n-type drift layer 111, and p ⁺ type layer 112. If basal plane dislocations exist on the surface of silicon carbide substrate 110, basal plane dislocations BPD may propagate into n-type drift layer 111 while epitaxially growing n-type drift layer 111 on silicon carbide substrate 110. The basal plane dislocation BPD formed during epitaxial growth remains in the n-type drift layer 111.

As shown in FIG. 1B, when the semiconductor device 100 performs bipolar operation that generates minority carriers, recombination of holes h and electrons e occurs near the basal plane dislocation BPD, resulting in high energy. Occur.

As shown in FIG. 1C, when high energy is applied to the basal plane dislocation BPD, a phenomenon is observed in which stacking faults SF are generated starting from the BPD. These stacking faults inhibit the movement of carriers over a wide range, increasing the on-resistance, and the forward voltage of the semiconductor device 100 is observed to increase over time.

Therefore, as shown in FIG. 2, a dislocation conversion layer 113 that converts basal plane dislocations of the silicon carbide substrate into edge dislocations is formed on a silicon carbide substrate 110, and an n-type drift layer 111 and an n-type drift layer 111 are formed on the dislocation conversion layer 113. It has been proposed to epitaxially grow and p ⁺ type layer 112 in order (for example, Patent Document 1).

Dislocation conversion layer 113 converts basal plane dislocations that invade from the surface of silicon carbide substrate 110 into edge dislocations when this layer is epitaxially grown on silicon carbide substrate 110 . It has been confirmed that edge dislocations have less influence on the electrical characteristics of semiconductor devices than basal plane dislocations. Therefore, even if the edge dislocation propagates from the dislocation conversion layer 113 to the n-type drift layer 111, it is considered that the influence on the electrical characteristics of the semiconductor device 200 is small.

International Publication No. 2017/199792

However, even in the semiconductor device 200 shown in FIG. 2, when minority carriers reach the basal plane dislocations of the silicon carbide substrate 110 during the operation of the semiconductor device 200, a stacking fault occurs starting from the basal plane dislocation, and the stacking fault There is a possibility that this may propagate into the n-type drift layer 111.

An object of this specification is to provide a semiconductor device and a method for manufacturing a semiconductor device that reduce basal plane dislocations in a silicon carbide layer.

According to the semiconductor device disclosed in this specification, an electrode layer, a first silicon carbide layer of a first conductivity type, which is disposed directly on the electrode layer and has a basal plane dislocation density of 1 piece/cm ² or less; a second silicon carbide layer of the first conductivity type that has an impurity concentration lower than that of the first silicon carbide layer and is disposed on the first silicon carbide layer; a silicon carbide region of a second conductivity type disposed. The electrode layer includes silicide of metal and silicon, metal, or both.

According to another semiconductor device disclosed in this specification, the electrode layer and the source gas containing silicon and carbon have a ratio of the number of carbon atoms to the number of silicon atoms of 0.7 or more and 1.1 or less. A first silicon carbide layer of a first conductivity type, which is formed by growing on a silicon carbide substrate using a raw material gas within the range of , and then removing the silicon carbide substrate, and is disposed directly on the electrode layer. , a second silicon carbide layer of the first conductivity type that has an impurity concentration lower than that of the first silicon carbide layer and is disposed on the first silicon carbide layer, and a second silicon carbide layer on the first silicon carbide layer or in the second silicon carbide layer. a third silicon carbide region of the second conductivity type disposed in the third silicon carbide region of the second conductivity type.

In these semiconductor devices, the impurity concentration of the first silicon carbide layer is preferably in a range of 1×10 ¹⁷ cm ⁻³ or more and 2×10 ¹⁹ cm ^{−3 or} less.

In these semiconductor devices, it is preferable that a region of the first silicon carbide layer on the electrode layer side contains impurities of the first conductivity type and impurities of the second conductivity type.

In these semiconductor devices, the interface of the first silicon carbide layer on the electrode layer side is preferably amorphous.

In these semiconductor devices, the combined thickness of the first silicon carbide layer and the second silicon carbide layer is 50 μm or more, and the impurity concentration of the second silicon carbide layer is 3×10 ¹⁵ cm ⁻³ or less. It is preferable.

In these semiconductor devices, the basal plane dislocation density of the second silicon carbide layer is preferably lower than that of the first silicon carbide layer.

These semiconductor devices are preferably MOSFETs or IGBTs.

Further, according to the method for manufacturing a semiconductor device disclosed in this specification, the raw material gas containing silicon and carbon has a ratio of the number of carbon atoms to the number of silicon atoms of 0.7 or more and 1.1 or less. a first step of forming a first silicon carbide layer of a first conductivity type on a silicon carbide substrate using a raw material gas within a range; A second step of forming a second silicon carbide layer on the first silicon carbide layer, and forming a second conductivity type silicon carbide region on the first silicon carbide layer or within the first silicon carbide layer. a fourth step of removing the silicon carbide substrate to expose the first silicon carbide layer; and a fifth step of forming an electrode layer on the exposed surface of the first silicon carbide layer. include.

In this semiconductor device manufacturing method, in the first step, the ratio R1 of the number of carbon atoms to the number of silicon atoms in the raw material gas used to form the first silicon carbide layer is determined, and in the second step, the ratio R1 of the number of carbon atoms to the number of silicon atoms is determined. The second silicon carbide layer is formed using a raw material gas containing a ratio R2 of the number of carbon atoms to the number of silicon atoms, and the ratio R1/R2 of the ratio R1 to the ratio R2 is: It is preferably within the range of 0.46 to 0.99.

In this semiconductor device manufacturing method, in the first step, a gas containing an impurity that provides conductivity of the first conductivity type and a gas containing an impurity that provides conductivity of the second conductivity type may be added as source gases. preferable.

In this semiconductor device manufacturing method, it is preferable to use dry etching or chemical mechanical polishing in the fourth step.

According to the semiconductor device disclosed in this specification described above, basal plane dislocations in a silicon carbide layer can be reduced.

Further, according to the method for manufacturing a semiconductor device disclosed in this specification described above, a semiconductor device in which basal plane dislocations in a silicon carbide layer are reduced can be obtained.

(A) to (C) are diagrams illustrating a conventional semiconductor device. FIG. 3 is a diagram illustrating another conventional semiconductor device. 1 is a cross-sectional view showing a first embodiment of a semiconductor device disclosed in this specification. FIG. 3 is a cross-sectional view showing a first modification of the semiconductor device of the first embodiment. FIG. 7 is a cross-sectional view showing a second modification of the semiconductor device of the first embodiment. FIG. 7 is a cross-sectional view showing a third modification of the semiconductor device of the first embodiment. FIG. 7 is a cross-sectional view showing a fourth modification of the semiconductor device of the first embodiment. FIG. 2 is a cross-sectional view showing a second embodiment of the semiconductor device disclosed in this specification. FIG. 2 is a diagram (part 1) illustrating steps of an embodiment of the method for manufacturing a semiconductor device disclosed in this specification. FIG. 2 is a diagram (part 2) illustrating steps of an embodiment of the method for manufacturing a semiconductor device disclosed in this specification. FIG. 3 is a diagram (Part 3) illustrating steps of an embodiment of the method for manufacturing a semiconductor device disclosed in this specification. FIG. 4 is a diagram (part 4) illustrating the steps of an embodiment of the method for manufacturing a semiconductor device disclosed in this specification. FIG. 5 is a diagram (part 5) illustrating the steps of an embodiment of the method for manufacturing a semiconductor device disclosed in this specification. FIG. 6 is a diagram (part 6) illustrating the steps of an embodiment of the method for manufacturing a semiconductor device disclosed in this specification.

Hereinafter, a preferred embodiment of the semiconductor device disclosed in this specification will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the invention described in the claims and equivalents thereof.

In this specification and the accompanying drawings, a layer or region marked with n means that electrons are the majority carrier, and a layer or region marked with p means that holes are the majority carrier. . Also, + added to n or p means that the impurity concentration is higher than that of a layer or region without it, and - added to n or p means that the impurity concentration is higher than that of a layer or region without it. It means that the concentration is low. In the following embodiments, the first conductivity type is an n type, and the second conductivity type is a p type.

Furthermore, in the notation of the Miller index, "-" means a bar attached to the index immediately after it, and adding "-" in front of the Miller index indicates a negative index.

FIG. 3 is a cross-sectional view showing the first embodiment of the semiconductor device disclosed in this specification. Semiconductor device 10 of this embodiment is a semiconductor device having a first conductivity type silicon carbide layer and a second conductivity type silicon carbide layer. Specifically, the semiconductor device 10 is a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a trench-type gate electrode.

Semiconductor device 10 includes an n ⁺ -type dislocation conversion layer 11 that is a silicon carbide epitaxial layer of a first conductivity type, a silicon carbide epitaxial layer 12 , a p-type silicon carbide epitaxial layer 13 of a second conductivity type, and a silicon carbide epitaxial layer 13 of a first conductivity type. source region 14 and a second conductivity type contact region 15. The semiconductor device 10 also includes a gate insulating film 16, a gate electrode 17, an interlayer insulating film 18, a source electrode 19, and a drain electrode 20.

First, the n ⁺ type dislocation conversion layer 11 will be explained below. The n ⁺ -type dislocation conversion layer 11 is a silicon carbide epitaxial layer doped with an impurity, for example, nitrogen, which provides a first conductivity type polarity. The n ⁺ type dislocation conversion layer 11 is formed on a single-crystal silicon carbide substrate in the manufacturing process of the semiconductor device 10 (see FIG. 9). n ⁺ -type dislocation conversion layer 11 converts basal plane dislocations that have entered into n ⁺ -type dislocation conversion layer 11 from the silicon carbide substrate into edge dislocations in the manufacturing process of semiconductor device 10 , and converts them into edge dislocations onto silicon carbide epitaxial layer 12 . Propagation of basal plane dislocations into other layers or regions disposed in the substrate is suppressed. In the manufacturing process of semiconductor device 10, after other components such as silicon carbide epitaxial layer 12 are formed on n ⁺ type dislocation conversion layer 11, the silicon carbide substrate is removed from the lower surface of n ⁺ type dislocation conversion layer 11. Then, the drain electrode 20 is formed.

In the semiconductor device 10, since the silicon carbide substrate is removed, even if minority carriers pass through the n ⁺ type dislocation conversion layer 11 and reach the drain electrode 20 during operation, the basal plane existing in the silicon carbide substrate Stacking faults caused by dislocations do not occur.

The n ⁺ -type dislocation conversion layer 11 is a raw material gas containing silicon and carbon, in which the C/Si ratio of the number of carbon atoms to the number of silicon atoms is in the range of 0.7 or more and 1.1 or less. Formed using gas. It is considered that the larger the C/Si ratio in the source gas, the more the formed n ⁺ -type dislocation conversion layer 11 has the effect of converting basal plane dislocations of the silicon carbide substrate into edge dislocations. The n ⁺ -type dislocation conversion layer 11 has a C/Si ratio of 0.7 or more in the raw material gas, so that when growing on the silicon carbide substrate, it converts basal plane dislocations of the silicon carbide substrate into edge dislocations, Propagation of basal plane dislocations through the n ⁺ -type dislocation conversion layer 11 can be sufficiently suppressed. On the other hand, if the C/Si ratio in the raw material gas is greater than 1.1, defects may occur in the n ⁺ -type dislocation conversion layer 11 due to the C/Si ratio. The C/Si ratio in the raw material gas can be determined, for example, by the flow rate ratio of the silicon-containing gas and the carbon-containing gas when manufacturing the n ⁺ -type dislocation conversion layer 11.

In particular, the C/Si ratio in the raw material gas should be 0.8 or more and 1.0 or less to eliminate basal plane dislocations of the silicon carbide substrate at the interface between the silicon carbide substrate and the n ⁺ type dislocation conversion layer 11. This is preferable from the viewpoint of preventing basal plane dislocations from entering the n ⁺ -type dislocation conversion layer 11 by converting them into type dislocations.

Note that since the C/Si ratio of the raw material gas used to form the silicon carbide layer of a semiconductor device is usually in the range of 1.1 or more and 1.5 or less, the above-mentioned n ⁺ type dislocation conversion layer The C/Si ratio of the source gas used to form 11 is different from the range typically used to form silicon carbide layers.

As described above, the n ⁺ type dislocation conversion layer 11 of the semiconductor device of this embodiment is a raw material gas containing silicon and carbon, and the C/Si ratio of the number of carbon atoms to the number of silicon atoms is 0.7. The above is formed using a raw material gas within the range of 1.1 or less. In this way, the semiconductor device of this embodiment has a manufacturing process as a part of its components. The reason why the semiconductor device of this embodiment has the manufacturing process as part of its characteristics will be explained below. The difference between the semiconductor device of this embodiment and the conventional technology is that when the ⁿ However, in light of the non-uniformity of the n ⁺ type dislocation conversion layer, the silicon carbide layer that does not have such an effect and the n ⁺ It is very difficult to unambiguously specify the structure or characteristics that are different from the type dislocation conversion layer 11 in words. On the other hand, although it may be possible in principle to configure the n ⁺ -type dislocation conversion layer using observation with an electron microscope and elemental analysis, We must manufacture a statistically significant number, obtain the results of electron microscope observation and elemental analysis, and perform statistical processing to find a meaningful index and its value that distinguishes this embodiment from the prior art. Otherwise, it will take a huge amount of time and cost. Moreover, since there are a huge number of possibilities in the prior art, it is difficult to unambiguously determine a statistically significant number. Therefore, it is almost impractical to find the above-mentioned indices and their values and directly specify the characteristics of the semiconductor device of this embodiment based only on the structure or characteristics of the object. Based on the above ideas, we have developed a technology that, when grown and formed on a silicon carbide substrate, has the effect of converting the basal plane dislocations of the silicon carbide substrate into edge dislocations, and does not contain many unnecessary defects. In order to specify this, a part of the configuration of the semiconductor device of this embodiment includes a manufacturing process.

Since n ⁺ -type dislocation conversion layer 11 converts basal plane dislocations of the silicon carbide substrate into edge dislocations mainly at the interface between silicon carbide substrate and n ⁺ -type dislocation conversion layer 11 , n ⁺ -type dislocation conversion layer 11 The basal plane dislocation density is 1 dislocation/cm ² or less, preferably 0.1 dislocation/cm ² or less. Although it is preferable that the number of basal plane dislocations contained in the n ⁺ type dislocation conversion layer 11 is as small as possible, the n ⁺ type dislocation conversion layer 11 usually has a basal plane dislocation density of at least about 100 pieces/cm ² . The basal plane dislocation density of the n ⁺ -type dislocation conversion layer 11 can be measured using, for example, an X-ray topography method.

In the thickness direction of the n ⁺ -type dislocation conversion layer 11 , the basal plane dislocations included in the n ⁺ -type dislocation conversion layer 11 form the n ⁺ -type dislocation conversion layer in the direction from the drain electrode 20 side to the silicon carbide epitaxial layer 12 side. 11, may be converted into an edge dislocation at an intermediate depth, or may penetrate to an intermediate depth and then stop. In this specification, the basal plane dislocation density of the n ⁺ type dislocation conversion layer 11 means the density at the depth where the number of basal plane dislocations is maximum in the thickness direction of the n ⁺ type dislocation conversion layer 11.

Note that when the basal plane dislocations of the silicon carbide substrate are converted to edge dislocations at the interface between the silicon carbide substrate and n ⁺ type dislocation conversion layer 11, the basal plane dislocations of this silicon carbide substrate are converted to n ⁺ type dislocations. Since it has not penetrated into the dislocation conversion layer 11, it is not included in the basal plane dislocation density of the n ⁺ type dislocation conversion layer 11.

Further, the concentration of the first conductivity type impurity added to the n ⁺ type dislocation conversion layer 11 is preferably in the range of 1×10 ¹⁷ cm ⁻³ or more and 2×10 ¹⁹ cm ^{−3 or} less. When the impurity concentration is 1×10 ¹⁷ cm ⁻³ or more, basal plane dislocations in the silicon carbide substrate can be sufficiently converted to edge dislocations. On the other hand, if the impurity concentration is 2×10 ¹⁹ cm ⁻³ or higher, defects such as double Shockley stacking faults may occur in the n ⁺ type dislocation conversion layer 11 .

It is preferable that the n ⁺ type dislocation conversion layer 11 and the drain electrode 20 are in ohmic contact from the viewpoint of reducing electrical resistance. From this point of view, for example, it is preferable that the interface of the n ⁺ -type dislocation conversion layer 11 on the drain electrode 20 side be in an amorphous state. At the interface on the drain electrode 20 side of the n ⁺ type dislocation conversion layer 11, it is preferable that 10% or more, particularly 50% or more of the region is amorphous from the viewpoint of obtaining ohmic contact.

Further, in the region near the interface on the drain electrode 20 side of the n ⁺ type dislocation conversion layer 11, it is preferable that the impurity concentration of the first conductivity type is 1×10 ¹⁸ cm ^{−3 or} more from the viewpoint of obtaining an ohmic junction. . The region near the interface on the drain electrode 20 side in the n ⁺ -type dislocation conversion layer 11 may be, for example, within a depth of 0.3 μm, particularly within a depth of 0.05 μm from the interface on the drain electrode 20 side. can.

Furthermore, a silicide region of metal and silicon may be formed in a region near the interface on the drain electrode 20 side of the n ⁺ type dislocation conversion layer 11 to form an ohmic contact with the drain electrode 20. For example, nickel can be used as the metal.

Further, an impurity of the second conductivity type, for example, boron, may be added to a region of the n ⁺ type dislocation conversion layer 11 near the interface on the drain electrode 20 side. Since boron forms a deep acceptor level in the n ⁺ -type dislocation conversion layer 11 and traps holes, boron reduces the hole density in the n ⁺ -type dislocation conversion layer 11 . Furthermore, even when holes trapped in boron are thermally excited, the ⁿ Lifespan can be reduced. Here, the region near the interface is a region 1 μm from the interface. In the region near the interface on the drain electrode 20 side of the n ⁺ -type dislocation conversion layer 11, the boron concentration can be set, for example, in a range of 1×10 ¹⁴ cm ⁻³ or more and 1×10 ¹⁷ cm ^{−3 or} less. . The above is the explanation regarding the n ⁺ type dislocation conversion layer 11.

Silicon carbide epitaxial layer 12 is arranged on n ⁺ type dislocation conversion layer 11 . Silicon carbide epitaxial layer 12 includes a first conductivity type n-type region 12a and a first conductivity type n ⁺ type region 12b.
, a first p ⁺ base region 12c of the second conductivity type, and a second p ⁺ base region 12d of the second conductivity type.

The n-type region 12a is arranged on the n ⁺ -type dislocation conversion layer 11. N-type region 12a is an n ^- type drift layer in which an impurity, for example, nitrogen, which provides a first conductivity type polarity is added to the silicon carbide epitaxial layer at a lower impurity concentration than n + -type dislocation conversion layer 11.

In order to ensure the mechanical strength of the semiconductor device 10, it is preferable that the combined thickness of the n-type region 12a and the n ⁺ -type dislocation conversion layer 11 be 50 μm or more. For example, when the thickness of the n ⁺ -type dislocation conversion layer 11 is 20 μm, the thickness of the n-type region 12a is preferably at least 30 μm. Here, from the viewpoint of setting the withstand voltage of the semiconductor device 10 to 3300 volts, the impurity concentration of the n-type region 12a is preferably 3×10 ¹⁵ cm ⁻³ or less. Further, if the impurity concentration of the n-type region 12a is set to 3×10 ¹⁵ cm ⁻³ or less and the thickness of the n-type region 12a is set to 60 μm, the withstand voltage of the semiconductor device 10 can be increased to 6500 volts. The lower limit of the impurity concentration of the n-type region 12a and the upper limit of the combined thickness of the n-type region 12a and the n ⁺ type dislocation conversion layer 11 are determined from the viewpoint of electrical characteristics such as on-resistance and withstand voltage of the semiconductor device 10. To be determined accordingly. The lower limit of the impurity concentration of n-type region 12a is usually about 1×10 ¹³ cm ⁻³ .

The n-type region 12a is formed by using a raw material gas containing silicon and carbon, in which the C/Si ratio of the number of carbon atoms to the number of silicon atoms is in the range of 1.1 or more and 1.5 or less. It is preferable that the When the C/Si ratio in the source gas is 1.1 or more, it is possible to stabilize the amount of nitrogen taken in, which is an impurity that provides n-type conductivity. Further, it is preferable that the basal plane dislocation density of the n-type region 12a is lower than that of the n ⁺ -type dislocation conversion layer 11. On the other hand, if the C/Si ratio in the source gas is 1.5 or more, defects due to the C/Si ratio may occur in the formed n-type region 12a. The C/Si ratio in the source gas can be determined, for example, by the flow rate ratio of the silicon-containing gas and the carbon-containing gas at the time of manufacturing the n-type region 12a.

The ratio of silicon in the raw material gas used to form the n + -type dislocation conversion layer 11 to the ratio R1 (C/Si ratio) of the number of carbon atoms to the number of silicon atoms in the raw material gas used to form the n ^- type region 12a The ratio R2/R1 of the number of carbon atoms to the number of atoms of carbon (C/Si ratio) is preferably in the range of 0.46 to 0.99.

N ⁺ type region 12b is arranged on n type region 12a. N ⁺ -type region 12b is formed by adding an impurity, for example, nitrogen, which provides a first conductivity type polarity to the silicon carbide epitaxial layer at a higher impurity concentration than n-type region 12a.

The first p ⁺ base region 12c and the second p ⁺ base region 12d are selectively arranged within the n ⁺ type region 12b. The first p ⁺ base region 12c and the second p ⁺ base region 12d are formed by adding an impurity, for example, aluminum, which provides a second conductivity type polarity to the silicon carbide epitaxial layer.

P-type silicon carbide epitaxial layer 13 is arranged on silicon carbide epitaxial layer 12 . The p-type silicon carbide epitaxial layer 13 has an impurity concentration lower than that of the first p ⁺ base region 12c and the second p ⁺ base region 12d, and an impurity that gives the polarity of the second conductivity type, such as aluminum, is added to the silicon carbide epitaxial layer. It is formed. P-type silicon carbide epitaxial layer 13, n-type region 12a, and n ⁺ -type region 12b form an internal PN diode. Further, the first p ⁺ base region 12c and the second p ⁺ base region 12d, and the n type region 12a and n ⁺ type region 12b form an internal PN diode. Although a MOSFET with an internal PN diode is a unipolar device, it may exhibit bipolar operation in which minority carriers are generated.

Trench 10a is arranged to penetrate p-type silicon carbide epitaxial layer 13 and reach silicon carbide epitaxial layer 12. A gate insulating film 16 and a gate electrode 17 are arranged inside the trench 10a. The gate insulating film 16 is disposed along the inner surface of the trench 10a and on the bottom and sides of the trench 10a. Gate electrode 17 is arranged inside gate insulating film 16 . Note that a portion of the gate electrode 17 may protrude upward from the trench 10a. In the example shown in FIG. 3, the semiconductor device 10 has two trenches 10a (gate insulating film 16 and gate electrode 17), but the semiconductor device 10 may have more trenches.

A portion of p-type silicon carbide epitaxial layer 13 near gate insulating film 16 forms a channel region. During operation of semiconductor device 10, a current between source electrode 19 and drain electrode 20 passes through the channel region.

Second p ⁺ base region 12d is arranged below trench 10a. The first p ⁺ base region 12c is arranged between two adjacent trenches 10a. A part of the first p ⁺ base region 12c may extend toward the trench 10a and be connected to the second p ⁺ base region 12d.

Source region 14 and contact region 15 are selectively arranged above p-type silicon carbide epitaxial layer 13 .

Source region 14 is arranged so as to surround trench 10a in plan view. Source region 14 is formed by adding an impurity, for example, nitrogen, which provides a first conductivity type polarity to the silicon carbide epitaxial layer at a higher impurity concentration than n-type region 12a.

Contact region 15 is arranged between two adjacent source regions 14. Contact region 15 is formed by adding an impurity, such as aluminum, which provides a second conductivity type polarity to the silicon carbide epitaxial layer at a higher impurity concentration than first p ⁺ base region 12c and second p ⁺ base region 12d.

Interlayer insulating film 18 is arranged on gate electrode 17 so as to cover gate electrode 17 . Interlayer insulating film 18 has an opening between two adjacent gate electrodes 17 through which source electrode 19 is exposed.

Source electrode 19 is electrically connected to source region 14 and contact region 15 . Source electrode 19 is electrically insulated from gate electrode 17 by interlayer insulating film 18 and gate insulating film 16 .

A drain electrode 20 is arranged on the lower surface of the n ⁺ -type dislocation conversion layer 11 (in FIG. 3, the lower side of the n ⁺ -type dislocation conversion layer 11 ). The drain electrode 20 is formed, for example, by sequentially stacking titanium, nickel, and gold layers from the n ⁺ type dislocation conversion layer 11 side.

The semiconductor device 10 is a switching element that can make a channel region between a source electrode 19 and a drain electrode 20 conductive by applying a voltage equal to or higher than a threshold value to a gate electrode 17. . Since the majority carriers flowing between the source electrode 19 and the drain electrode 20 in a conductive state are electrons, the semiconductor device 10 is a first conductivity type (n-type) MOSFET.

According to the semiconductor device of this embodiment described above, basal plane dislocations in the silicon carbide layer can be reduced.

Next, Modifications 1 to 4 of the semiconductor device of the present embodiment described above will be described below with reference to FIGS. 4 to 7.

FIG. 4 is a sectional view showing a first modification of the semiconductor device of the first embodiment. In the semiconductor device 10 of this modification, an n ⁺⁺ type recombination promotion layer 21 is arranged between the n ⁺ type dislocation conversion layer 11 and the n type region 12a.

Since the n ⁺ type dislocation conversion layer 11 may ^have basal plane dislocations, although the number is small, the semiconductor Stacking faults may occur within the device 10.

The n ⁺⁺ type recombination promotion layer 21 has a defect level that recombines with holes, which are minority carriers, moving from the source electrode 19 side to the drain electrode 20 side, and the holes are transferred to the n ⁺ type dislocation conversion layer. 11 is suppressed.

The n ⁺⁺ type recombination promotion layer 21 is formed by adding an impurity, for example, nitrogen, which provides the first conductivity type polarity to the silicon carbide epitaxial layer at a higher impurity concentration than the n ⁺ type dislocation conversion layer 11 .

The impurity concentration of the n ⁺⁺ type recombination promoting layer 21 can be set in a range of 1×10 ¹⁷ cm ⁻³ or more and 2×10 ¹⁹ cm ^{−3 or} less.

FIG. 5 is a sectional view showing a second modification of the semiconductor device of the first embodiment. The semiconductor device 10 of this modification is a vertical IGBT (Insulated Gate Bipolar Transistor) having a trench-type gate electrode.

The n ⁺ type dislocation conversion layer 11 has a first conductivity type n ⁺ type layer 11a disposed on the n type region 12a side and a second conductivity type p type layer 11b disposed on the collector electrode 20a side.

The n ⁺ type dislocation conversion layer 11 is different from the first embodiment described above in that it has a layer having two polarities in the thickness direction, but the C/Si ratio in the source gas and the basal plane dislocation The description of density also applies to each of the n ⁺ type layer 11a and the p type layer 11b as appropriate.

Further, the semiconductor device 10 has an emitter electrode 19a. The other configuration of the semiconductor device 10 is the same as that of the first embodiment described above.

FIG. 6 is a sectional view showing a third modification of the semiconductor device of the first embodiment. The semiconductor device 10 of this modification is a vertical RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) having a trench-type gate electrode.

A plurality of p-type regions 22 of the second conductivity type are selectively arranged in a portion of the n ⁺ -type dislocation conversion layer 11 on the collector electrode 20a side. P-type region 22, together with n-type regions such as n-type region 12a, forms a freewheeling diode between emitter electrode 19a and collector electrode 20a. The other configuration of the semiconductor device 10 is the same as that of the first embodiment described above.

FIG. 7 is a sectional view showing a fourth modification of the semiconductor device of the first embodiment. The semiconductor device 10 of this modification is a vertical IGBT (Insulated Gate Bipolar Transistor) having a trench-type gate electrode.

The p ⁺ -type dislocation conversion layer 11c is a p-type silicon carbide epitaxial layer doped with an impurity, for example, aluminum, which gives the polarity of the second conductivity type, and has a polarity different from that of the n-type region 12a. The other configuration of the semiconductor device 10 is the same as that of the first embodiment described above.

Next, a second embodiment of the above-described semiconductor device will be described below with reference to FIG. Regarding the points not particularly described in other embodiments, the detailed explanation regarding the above-mentioned first embodiment applies as appropriate. Moreover, the same components are given the same reference numerals.

FIG. 8 is a cross-sectional view showing a second embodiment of the semiconductor device disclosed in this specification. Semiconductor device 30 of this embodiment is a semiconductor device having a silicon carbide layer. Specifically, the semiconductor device 30 is a vertical Schottky barrier diode.

The semiconductor device 30 includes an n ⁺ -type dislocation conversion layer 31 of a first conductivity type, a silicon carbide epitaxial layer 32 of a first conductivity type, a p-type region 33 of a second conductivity type, and a p ^- type region of a second conductivity type. It includes a region 34 , a p ⁺ type region 35 of the second conductivity type, an anode electrode 36 , an interlayer insulating film 37 , and a cathode electrode 38 .

The n ⁺ -type dislocation conversion layer 31 is a single-crystal silicon carbide epitaxial layer doped with an impurity that provides first conductivity type polarity, such as nitrogen. For the n ⁺ -type dislocation conversion layer 31, the explanation for the dislocation conversion layer in the first embodiment described above applies as appropriate.

Silicon carbide epitaxial layer 32 is placed on n ⁺ type silicon carbide layer 31 . The silicon carbide epitaxial layer 32 is an n-type drift layer in which the silicon carbide epitaxial layer is doped with an impurity, such as nitrogen, which gives a first conductivity type polarity at a lower impurity concentration than the dislocation conversion layer 31.

P-type region 33 and p ^−-type region 34 are selectively arranged on top of silicon carbide epitaxial layer 32 .

P type region 33 and p ^- type region 34 have a ring shape in plan view. P ⁻ type region 34 is arranged outside p type region 33 and adjacent to p type region 33 .

P-type region 33 is formed by doping the silicon carbide epitaxial layer with an impurity that imparts second conductivity type polarity, such as aluminum.

P ^- type region 34 is formed by doping the silicon carbide epitaxial layer with an impurity that provides a second conductivity type polarity, such as aluminum, at a lower impurity concentration than p type region 33 .

P ⁺ -type region 35 is arranged inside p-type region 33 and spaced apart from p-type region 33 . P ⁺ -type region 35 is formed by doping the silicon carbide epitaxial layer with an impurity that provides a second conductivity type polarity, such as aluminum, at a higher impurity concentration than p-type region 33 . P ⁺ type region 35 and silicon carbide epitaxial layer 32 form an internal PN diode. Although a Schottky barrier diode with an internal PN diode is a unipolar device, it may perform bipolar operation in which minority carriers are generated.

Anode electrode 36 is arranged on silicon carbide epitaxial layer 32 so as to cover part of p ⁺ type region 35 and p type region 33 .

An active region 30a having a Schottky barrier is formed at the junction between anode electrode 36 and silicon carbide epitaxial layer 32.

In the active region 30a, a plurality of p ⁺ -type regions 35 are arranged at predetermined intervals, forming a JBS (Junction Barrier Schottky) structure. The junction between the plurality of p ⁺ type regions 35 and the anode electrode 36 may be an ohmic junction or a Schottky junction.

A termination region 30b is formed around the active region 30a. In the termination region 30b, a ring-shaped p ^- type region 34 is arranged so as to surround the anode electrode 36 in plan view. Furthermore, p-type region 33 is arranged so as to span from the end of active region 30a to termination region 30b.

The p-type region 33 and the p ^- type region 34 form a breakdown voltage structure that relaxes the electric field and prevents breakdown voltage deterioration of the semiconductor device 30 in the termination region 30b. Specifically, p-type region 33 has a function of avoiding concentration of an electric field at the junction end between silicon carbide epitaxial layer 32 and anode electrode 36. Furthermore, the p-type region 34 has a function of further dispersing the electric field in the peripheral portion of the active region 30a.

Interlayer insulating film 37 is arranged on silicon carbide epitaxial layer 32 so as to cover p-type region 33 and p ^- type region 34 in termination region 30b.

Anode electrode 36 covers the surface of silicon carbide epitaxial layer 32 exposed in active region 30a, and contacts p-type region 33 at the periphery of active region 30a. The anode electrode 36 extends halfway from the active region 30a to the termination region 30b, and the end of the termination region 30b of the anode electrode 36 extends to above the p-type region 33. Furthermore, the anode electrode 36 covers the p-type region 33 with an interlayer insulating film 37 interposed therebetween.

The anode electrode 36 is preferably formed using, for example, a group IVa metal, a group Va metal, a group VIa metal, aluminum, or silicon. Further, the anode electrode 36 is preferably formed using a material containing two or three elements among IVa group metal, Va group metal, VIa group metal, aluminum, and silicon.

The Schottky barrier height between anode electrode 36 and silicon carbide epitaxial layer 32 is preferably 1 eV or more, for example, when semiconductor device 30 is used as a high voltage semiconductor device. Further, the Schottky barrier height of the anode electrode 36 is preferably, for example, 0.5 eV or more and less than 1 eV when the semiconductor device 30 is used as a power supply device.

A cathode electrode 38 is arranged below the n ⁺ -type dislocation conversion layer 31 . When a positive forward voltage is applied to the anode electrode 36 and a negative forward voltage is applied to the cathode electrode 38, the semiconductor device 30 enters a forward conduction state in which electrons flow from the cathode electrode 38 side to the anode electrode 36 side. Conversely, when a negative voltage in the opposite direction is applied to the anode electrode 36 and a positive voltage is applied to the cathode electrode 38, the semiconductor device 30 enters a reverse blocking state. Since the majority carriers flowing between the anode electrode 36 and the cathode electrode 38 in the forward conduction state are electrons, the semiconductor device 10 is a first conductivity type (n-type) diode.

According to the semiconductor device of this embodiment described above, the same effects as in the first embodiment can be achieved.

Next, a preferred embodiment of the method for manufacturing a semiconductor device disclosed in this specification will be described below with reference to FIGS. 9 to 14. The method for manufacturing a semiconductor device of this embodiment is for manufacturing the first embodiment of the semiconductor device described above.

First, as shown in FIG. 9, an n ⁺ type silicon carbide substrate 40 is prepared. The n ⁺ -type silicon carbide substrate 40 is a single-crystal 4H-type silicon carbide substrate doped with an impurity, for example, nitrogen, which provides a first conductivity type polarity. N ⁺ type silicon carbide substrate 40 has a first surface 40a and a second surface 40b. First surface 40a and second surface 40b of n ⁺ -type silicon carbide substrate 40 are (0001) planes (Si planes). Note that the first surface 40a and the second surface 40b may be a (000-1) plane (C plane).

It is preferable that the first surface 40a has an off-angle in a range of about 0.05 degrees to 8 degrees from the viewpoint of growing an epitaxial layer having a (0001) plane (Si plane) on the first surface 40a. On the other hand, if the first surface 40a has a basal plane dislocation because the first surface 40a has an off-angle, there is a possibility that the basal plane dislocation will propagate to the epitaxial layer grown on the first surface 40a.

Therefore, as shown in FIG. 9, n ⁺ type dislocation conversion layer 11 is formed on first surface 40a of n ⁺ type silicon carbide substrate 40 by epitaxial growth, and substrate structure 50 is obtained. The n ⁺ type dislocation conversion layer 11 is formed using, for example, a CVD method. The thickness of the n ⁺ type dislocation conversion layer 11 can be, for example, 0.5 μm to 20 μm.

As the source gas for forming the n ⁺ -type dislocation conversion layer 11, for example, a gas containing silicon and a gas containing carbon can be used. For example, silane (SiH ₄ ) can be used as the silicon-containing gas. For example, propane (C ₃ H ₈ ) can be used as the carbon-containing gas. Furthermore, a gas containing nitrogen or a gas containing aluminum can be used as the impurity gas. For example, nitrogen (N ₂ ) can be used as the nitrogen-containing gas. For example, trimethylaluminum (Al(CH ₃ ) ₃ ) can be used as the gas containing aluminum. By adjusting the flow rate ratio of the silicon-containing gas and the carbon-containing gas, the C/Si ratio in the raw material gas can be kept within the range of 0.7 or more and 1.1 or less, particularly 0.8 or more and 1.0 or less. It is preferable to Further, by adjusting the flow rate of the impurity gas, it is preferable to set the impurity concentration of the n ⁺ type dislocation conversion layer 11 to a range of 1×10 ¹⁷ cm ⁻³ or more and 2×10 ¹⁹ cm ^{−3 or} less.

Here, in the initial stage of growth of the n ⁺ type dislocation conversion layer 11, the flow rate of the impurity gas may be adjusted so that the impurity concentration of the n ⁺ type dislocation conversion layer 11 is 1×10 ¹⁸ cm ^{−3 or} more. . Here, the initial stage of growth is the stage until the growth reaches 1 μm. Further, at the initial stage of growth of the n ⁺ type dislocation conversion layer 11, the boron concentration of the n ⁺ type dislocation conversion layer 11 is in the range of 1×10 ¹⁴ cm ⁻³ or more and 1×10 ¹⁷ cm ^{−3 or} less. For example, boron trifluoride (BF ₃ ) gas may be added.

Next, as shown in FIG. 10, silicon carbide epitaxial layer 12 is formed on n ⁺ type dislocation conversion layer 11 of substrate structure 50. Silicon carbide epitaxial layer 12 is formed using, for example, a CVD method. Silicon carbide epitaxial layer 12 is formed to have the same composition as n-type region 12a of the first embodiment of semiconductor device 10 described above.

As the source gas for forming silicon carbide epitaxial layer 12, for example, a gas containing silicon and a gas containing carbon can be used. For example, silane (SiH ₄ ) can be used as the silicon-containing gas. For example, propane (C ₃ H ₈ ) can be used as the carbon-containing gas. Furthermore, a gas containing nitrogen or a gas containing aluminum can be used as the impurity gas. For example, nitrogen (N ₂ ) can be used as the nitrogen-containing gas. For example, trimethylaluminum (Al(CH ₃ ) ₃ ) can be used as the gas containing aluminum. It is preferable that the C/Si ratio in the raw material gas be within the range of 1.1 or more and 1.5 or less by adjusting the flow rate ratio of the silicon-containing gas and the carbon-containing gas. Further, it is preferable that the impurity concentration of silicon carbide epitaxial layer 12 is set to a range of 3×10 ¹⁵ cm ⁻³ or less by adjusting the flow rate of the impurity gas.

Next, as shown in FIG. 11, an n-type region 12a, an n ⁺ -type region 12b, a first p ⁺ base region 12c, and a second p ⁺ base region 12d are formed in the silicon carbide epitaxial layer 12 of the substrate structure 50. It is formed. Further, on the silicon carbide epitaxial layer 12, a p-type silicon carbide epitaxial layer 13, a source region 14, a contact region 15, a gate insulating film 16, a gate electrode 17, an interlayer insulating film 18, and a source electrode 19 are formed. It is formed.

Here, n-type region 12a has the same composition as silicon carbide epitaxial layer 12. The ratio of silicon in the raw material gas used to form the n ⁺ type dislocation conversion layer 11 to the ratio R2 (C/Si ratio) of the number of carbon atoms to the number of silicon atoms in the raw material gas used to form the n type region 12a The ratio R1/R2 of the number of carbon atoms to the number of atoms of carbon (C/Si ratio) is preferably in the range of 0.46 to 0.99.

Next, as shown in FIG. 12, n ⁺ type silicon carbide substrate 40 of substrate structure 50 is removed to expose n ⁺ type dislocation conversion layer 11. For example, the back side of the substrate structure 50 of the n ⁺ type silicon carbide substrate 40 is removed using a grinding technique such as diamond lapping. The surface of n ⁺ -type dislocation conversion layer 11 exposed when n ⁺ -type silicon carbide substrate 40 is removed by grinding is in an amorphous state.

Further, after n ⁺ -type silicon carbide substrate 40 is ground to an intermediate depth, the remaining portion may be removed using a dry etching technique such as plasma etching. In this case, the end point of dry etching may be detected by a change in the color of plasma emission.

Next, as shown in FIG. 13, the region in which the crystal structure of the surface of the n ⁺ type dislocation conversion layer 11 in the substrate structure 50 is damaged may be removed by polishing using a polishing technique such as chemical mechanical polishing. . Further, a region in which the crystal structure of the surface of the n ⁺ -type dislocation conversion layer 11 in the substrate structure 50 is damaged may be removed using wet etching or dry etching technology.

Furthermore, the number of defects on the surface of the n ⁺ -type dislocation conversion layer 11 may be reduced by heating the substrate structure 50 to rearrange the surface of the n ^{+ -type} dislocation conversion layer 11 . Since step bunching is formed on the surface of the n ⁺ type dislocation conversion layer 11 after heating, the arithmetic mean roughness of the surface can be, for example, 10 nm or more. The upper limit of the arithmetic mean roughness of the surface is usually about 100 nm. The temperature at which the substrate structure 50 is heated can be in the range of 1500°C to 1800°C. Note that the process shown in FIG. 13 may be omitted.

Next, as shown in FIG. 14, a drain electrode 20 is formed on the exposed surface of the n ⁺ type dislocation conversion layer 11 of the substrate structure 50, and the semiconductor device 10 is obtained. Note that the drain electrode 20 may be formed directly on the surface of the n ⁺ type dislocation conversion layer 11 which is in an amorphous state.

In the present invention, the semiconductor device and the method for manufacturing the semiconductor device of the embodiments described above can be modified as appropriate without departing from the spirit of the present invention. Moreover, the constituent features of one embodiment can be applied to other embodiments as appropriate.

For example, although the semiconductor device of the first embodiment described above is a vertical MOSFET having a trench-type gate electrode, the semiconductor device may be a vertical MOSFET having a planar-type gate electrode.

Moreover, although the semiconductor device of the second embodiment described above is a Schottky barrier type diode, the semiconductor device may be a PN type or PIN type diode.

Further, in the semiconductor device of the embodiment described above, the majority carriers are electrons, but the semiconductor device may have holes as the majority carriers. In this case, the dislocation conversion layer is a p-type silicon carbide epitaxial layer.

10 Semiconductor device 11 n ⁺ type dislocation conversion layer (first silicon carbide layer)
11a n ⁺ type layer 11b p type layer 12 silicon carbide epitaxial layer 12a n type region (second silicon carbide layer)
12b n ⁺ type region 12c first p ⁺ base region 12d second p ⁺ base region 13 p type silicon carbide epitaxial layer (third silicon carbide region)
14 source region 15 contact region 16 gate insulating film 17 gate electrode 18 interlayer insulating film 19 source electrode 19a emitter electrode 20 drain electrode 20a collector electrode 21 n ⁺⁺ type recombination promotion layer 22 p type region 30 semiconductor device 31 n ⁺ type dislocation conversion Layer (first silicon carbide layer)
32 Silicon carbide epitaxial layer (second silicon carbide layer)
33 p type region 34 p ⁻ type region 35 p ⁺ type region (third silicon carbide region)
36 anode electrode 37 interlayer insulating film 38 cathode electrode 40 n ⁺ type silicon carbide substrate 40a first surface 40b second surface 50 substrate structure

Claims (12)

an electrode layer;
a first silicon carbide layer of a first conductivity type disposed directly on the electrode layer and having a basal plane dislocation density of 0.1 pieces/cm ² or less;
a second silicon carbide layer of the first conductivity type that has a lower impurity concentration than the first silicon carbide layer and is disposed on the first silicon carbide layer;
a second conductivity type silicon carbide region disposed on or within the second silicon carbide layer;
A semiconductor device comprising: an electrode layer;
After growth on a silicon carbide substrate using a raw material gas containing silicon and carbon in which the ratio of the number of carbon atoms to the number of silicon atoms is within the range of 0.7 or more and 1.1 or less. a first silicon carbide layer of a first conductivity type that is formed by removing the silicon carbide substrate and is disposed directly on the electrode layer;
a second silicon carbide layer of the first conductivity type that has a lower impurity concentration than the first silicon carbide layer and is disposed on the first silicon carbide layer;
a third silicon carbide region of a second conductivity type disposed on or within the second silicon carbide layer;
Equipped with
In the semiconductor device, an interface of the first silicon carbide layer on the electrode layer side is amorphous. an electrode layer;
a first silicon carbide layer of a first conductivity type that is disposed directly on the electrode layer and has a basal plane dislocation density of 1 piece/cm ² or less;
a second silicon carbide layer of the first conductivity type that has a lower impurity concentration than the first silicon carbide layer and is disposed on the first silicon carbide layer;
a second conductivity type silicon carbide region disposed on or within the second silicon carbide layer;
Equipped with
In the semiconductor device, an interface of the first silicon carbide layer on the electrode layer side is amorphous . an electrode layer;
a first silicon carbide layer of a first conductivity type that is disposed directly on the electrode layer and has a basal plane dislocation density of 1 piece/cm ² or less;
a second silicon carbide layer of the first conductivity type that has a lower impurity concentration than the first silicon carbide layer and is disposed on the first silicon carbide layer;
a second conductivity type silicon carbide region disposed on or within the second silicon carbide layer;
Equipped with
A semiconductor device, wherein a region of the first silicon carbide layer on the electrode layer side includes the first conductivity type impurity and the second conductivity type impurity. an electrode layer;
After growth on a silicon carbide substrate using a raw material gas containing silicon and carbon in which the ratio of the number of carbon atoms to the number of silicon atoms is within the range of 0.7 or more and 1.1 or less. a first silicon carbide layer of a first conductivity type that is formed by removing the silicon carbide substrate and is disposed directly on the electrode layer;
a second silicon carbide layer of the first conductivity type that has a lower impurity concentration than the first silicon carbide layer and is disposed on the first silicon carbide layer;
a third silicon carbide region of a second conductivity type disposed on or within the second silicon carbide layer;
Equipped with
A semiconductor device, wherein a region of the first silicon carbide layer on the electrode layer side includes the first conductivity type impurity and the second conductivity type impurity. 6. The semiconductor device according to claim 1, wherein the impurity concentration of the first silicon carbide layer is in a range of 1×10 ¹⁷ cm ⁻³ or more and 2×10 ¹⁹ cm ⁻³ or less . The combined thickness of the first silicon carbide layer and the second silicon carbide layer is 50 μm or more and 80 μm or less, and the impurity concentration of the second silicon carbide layer is 3×10 15 cm ⁻³ or ^less . The semiconductor device according to any one of claims 1 to 6 . 8. The semiconductor device according to claim 1, wherein the second silicon carbide layer has a lower basal plane dislocation density than the first silicon carbide layer. 9. The semiconductor device according to claim 1, wherein the semiconductor device is a MOSFET or an IGBT . Using a raw material gas containing silicon and carbon, in which the ratio of the number of carbon atoms to the number of silicon atoms is within the range of 0.7 or more and 1.1 or less, a first layer is formed on a silicon carbide substrate. a first step of forming a first conductive silicon carbide layer;
a second step of forming a second silicon carbide layer of the first conductivity type having a lower impurity concentration than the first silicon carbide layer on the first silicon carbide layer;
a third step of forming a second conductivity type silicon carbide region on the first silicon carbide layer or within the first silicon carbide layer;
a fourth step of removing the silicon carbide substrate to expose the first silicon carbide layer;
a fifth step of forming an electrode layer on the exposed surface of the first silicon carbide layer;
including;
In the first step, the ratio R1 of the number of carbon atoms to the number of silicon atoms in the raw material gas used to form the first silicon carbide layer,
In the second step, the second silicon carbide layer is formed using a raw material gas containing silicon and carbon and having a ratio R2 of the number of carbon atoms to the number of silicon atoms,
A method for manufacturing a semiconductor device, wherein a ratio R1/R2 of the ratio R1 to the ratio R2 is within a range of 0.46 to 0.99. Using a raw material gas containing silicon and carbon, in which the ratio of the number of carbon atoms to the number of silicon atoms is within the range of 0.7 or more and 1.1 or less, a first layer is formed on a silicon carbide substrate. a first step of forming a first conductive silicon carbide layer;
a second step of forming a second silicon carbide layer of the first conductivity type having a lower impurity concentration than the first silicon carbide layer on the first silicon carbide layer;
a third step of forming a second conductivity type silicon carbide region on the first silicon carbide layer or within the first silicon carbide layer;
a fourth step of removing the silicon carbide substrate to expose the first silicon carbide layer;
a fifth step of forming an electrode layer on the exposed surface of the first silicon carbide layer;
including;
In the first step, a method for manufacturing a semiconductor device includes adding, as source gases, a gas containing an impurity that imparts conductivity of the first conductivity type and a gas containing an impurity that imparts conductivity of the second conductivity type. . 12. The method of manufacturing a semiconductor device according to claim 10 , wherein the fourth step uses dry etching or chemical mechanical polishing.

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