JP5017768B2 - Silicon carbide semiconductor element - Google Patents

Description

  The present invention relates to a voltage-driven MOS type power semiconductor device such as a MOSFET or IGBT using silicon carbide as a semiconductor material, particularly a trench type semiconductor device.

Silicon carbide semiconductors have a band gap of 4H-SiC, 3.25 eV and about 3 times larger than 1.12 eV of Si, and the electric field strength is nearly an order of magnitude larger than Si (0.3 MV / cm) (2 to 4 MV / cm). It has the characteristics. In a power semiconductor device, the on-resistance when the device is in an on state decreases in inverse proportion to the third power of the electric field strength and decreases in proportion to the reciprocal of mobility as shown in the following equation.
R _DRIFT = (4BV ² ) / (μεE _CR ³ ) ・ ・ Expression (1)
Here, BV is the dielectric strength, mu is the carrier mobility, epsilon is the dielectric constant of the semiconductor, E _CR is the critical electric field strength of the semiconductor. This _RDRIFT is the minimum on-resistance of the unipolar device, and the relationship between this on-resistance and the withstand voltage is called a unipolar limit.
Therefore, even if it is considered that the mobility is lower than that of Si, the on-resistance can be reduced to several hundredth of that of Si, which is expected as a next-generation power semiconductor device. To date, devices with various structures such as diodes, transistors, and thyristors have been prototyped, and some of them have been put into practical use.

  Among them, FIG. 11 shows a cross-sectional view of one cell of an n-channel DIMOSFET (Double Implanted MOSFET) which is one form of a transistor. As a general production method, first, the same N type drift layer 2 is formed on a low resistance N type silicon carbide substrate 1. A deep P-type base region 3 is selectively formed there by generally using aluminum (Al). Further, a low-resistance N-type source region 4 is selectively formed in the P-type base region 3 by ion implantation of nitrogen (N) or phosphorus (P) so as to be surrounded by the P-type base region 3. What is important at this time is that the width of the channel region 5 in the surface portion sandwiched between the N-type source region 4 and the N-type drift layer 2 in the base region 3 is made constant between the cells, and this width is manufactured with high accuracy. As a method of doing this, it is described in Patent Document 1, for example. Thereafter, after forming the gate oxide film 6, the gate electrode 7 made of polysilicon, the metal source electrode 8 connected to the N-type source region 4 and the P-type base region, and the metal connected to the N-type silicon carbide substrate 1 on the back surface are formed. A drain electrode 9 is formed. Reference numeral 10 denotes an interlayer insulating film for insulating the gate electrode 7 from the source electrode 8.

  In actual operation, when the source electrode 8 is set to the ground potential in advance and a negative bias is applied to the gate electrode 7, holes are induced in the channel region 5 sandwiched between the N-type source region 4 and the N-type drift layer 2. In this n-channel MOSFET, electrons are used as conduction carriers, so that no current flows. When a positive high voltage is applied to the drain electrode 9, the junction between the base region 3 and the drift layer 2 is in a reverse bias state, so that the depletion layer extends into the base region 3 and the drift layer region 2, and the current is kept low. The high voltage is maintained and this is in the off state. When a positive bias is applied to the gate electrode 7 from this state, an inverted state is brought about in which electrons are induced in the channel region 5 on the surface of the base region 3 sandwiched between the source region 4 and the drift layer 2. The region 4, the inverted channel region 5, the drift layer 2, the substrate 1, and the drain electrode 9 are turned on in this order. When a negative bias is applied again to the gate electrode, the inversion of the channel region 5 disappears, the electron flow path is cut off, and the transistor is turned off.

The on-resistance in the on-state is the contact resistance of the source electrode, the resistance of the source region, the channel resistance of the channel region, and the interface of the drift layer 2 with the gate oxide film 6 as shown by the arrow 12 in the above-described current path. Storage resistance when electrons move in the vicinity, n-type drift layer 2 is sandwiched between adjacent p-type base layers 3 when flowing from the vicinity of gate oxide film 6 in drift layer 2 toward the lower drain Is the sum of the JFET resistance, the resistance in the thickness direction of the drift layer 2 excluding the thickness of the p-type base layer 3, the substrate resistance, and the drain contact resistance.
Since this DIMOSFET has no built-in voltage in principle, the on-voltage can be made lower than that of a bipolar device. Since it is a unipolar device, there is no accumulation in the carrier device in the on state, so switching loss is small. Further, since the voltage driving is performed by applying a small positive / negative voltage to the gate electrode to perform the on / off operation, there is an advantage that the driving circuit is simplified.

In contrast, FIG. 12 shows a cross-sectional view of one cell of a UMOSFET having a trench gate structure. An n-type drift layer 2 is epitaxially grown on the n-type low resistance substrate 1, and a p-type base region 3 is further epitaxially grown. Thereafter, the source region 4 is formed by ion implantation of nitrogen (N) or phosphorus (P). Thereafter, a trench 11 is formed by a reactive ion etching method, a gate oxide film 6 is formed so as to cover the trench 11, and a gate electrode 7 is formed on the gate oxide film 6. After the gate electrode 7 is covered with the interlayer insulating film 10, the interlayer insulating film 10 is etched to open a window so that the source electrode can come into contact with the base layer 3 and the source region 4, thereby forming the source electrode 8. Finally, the drain electrode 9 is formed on the back surface of the wafer to complete the n-channel UMOSFET.
The actual operation is the same as that of the n-channel DIMOSFET of FIG.
However, since the channel region 5 is structurally formed on the side surface of the trench 11 in the UMOSFET, the ON resistance in the ON state is the same as that of the gate oxide film 6 of the drift layer 2 added in the DIMOSFET as indicated by the arrow 13 in the figure. Storage resistance when electrons move near the interface, n-type drift layer 2 is sandwiched between adjacent p-type base layers 3 when flowing from the vicinity of gate oxide film 6 in drift layer 2 toward the lower drain Since there is no JFET resistance caused by this, there is an advantage that the storage resistance and the JFET resistance can be reduced as much as possible. Further, since there is no JFET resistance, the distance between the adjacent p-type base layers 3 can be reduced, so that there is an advantage that the cell pitch can be reduced and the on-resistance can be made smaller than that of the DIMOSFET.

For the above reasons, in particular, in a transistor having a withstand voltage of about 1 to 2 kV, the on-resistance cannot be ignored. Therefore, a UMOSFET that can reduce the on-resistance by miniaturization is promising.
However, in the actual device, there are various resistance components as described above, and the ratio of these resistance components to the resistance of the drift layer increases as the withstand voltage decreases. Is a problem.
In addition, in the MOSFET, there is a problem that a channel resistance component represented by the following formula occupies a large proportion.
_{R CH = L / {WC OX} μ n (V G -V T)} ·· formula (2)
Here, L is the channel length, W is the channel width, C _OX is oxide capacitance, the mu _n is the mobility, V _G is the gate voltage, V _T of the carrier is the threshold voltage of the gate. From this equation (2), it is understood that R _CH is greatly affected by the electron mobility μ _n .

In a MOSFET, electrons are trapped at the trap level existing at the interface between silicon carbide and the gate oxide film, and the number of electrons actually contributing to conduction is reduced, or the mobility is increased due to Coulomb scattering by the trapped electrons. There is a problem that it falls below the bulk value. Examples of efforts to improve mobility will be described below sequentially.
First, the crystal structure and crystal plane of SiC from which a UMOSFET is fabricated will be described. FIG. 13 shows a crystal plane of hexagonal silicon carbide mainly used for the unit cell structure and the MOS interface. The main hexagonal silicon carbide includes 4H-SiC, which has a structure in which a pair of Si-C layers are stacked in the c-axis direction at a four-layer cycle, and 6H-SiC, which is stacked at a six-layer cycle. is there. In 4H-SiC, five layers are included in the unit cell of FIG. 13, and in 6H-SiC, seven layers are included.
In FIG. 13, (a) is the (0001) plane of the hexagonal column, (000-1) plane of the bottom, (b) is the (1-100) plane of the hexagonal column, (c) is (1) (11-20) plane that is perpendicular to the (-100) plane, (d) is a 4H (03-38) plane or a plane that shares one side of the hexagon on the top surface and has an angle of 54.7 ° with the bottom surface. This surface is called the 6H (01-14) surface. Here, when describing the symbols on the lattice plane, for negative indices, a superscript bar (-) is used in numbers for crystallography, but (-) in front of the numbers because of electronic application. The sign of A plane having equivalent symmetry is represented by {}, when indicating a direction in the crystal by [], and when indicating all equivalent directions, it is represented by <>.

Currently, a silicon carbide single crystal ingot whose main surface is the (0001) plane or the (000-1) plane is bulk-grown, and the wafer is cut out and polished so that the (0001) plane and the (000-1) plane are the main surfaces. A silicon carbide wafer as a surface is produced. Therefore, in the DIMOSFET, an element is manufactured using these surfaces as MOS interfaces.
According to the description of Non-Patent Document 1, a MOS interface was formed on each crystal surface of 4H-SiC, and the mobility of the MOSFET at that time was investigated. As a result, the effective mobility was (0001). , (11-20), (03-38) plane, ^{respectively, 3.8cm 2 /Vs,5.4cm 2 /Vs,10.6cm 2 /} Vs and the (0001) plane from (11-20) plane and (03-38 It is reported that the mobility of MOSFET on the surface is high. This is because the (0001) plane of 4H or 6H-SiC is the Si (111) plane, the (11-20) plane of 4H or 6H-SiC, and the (1-100) plane of 4H or 6H-SiC is Si (110). ) Surface and 4H-SiC (03-38) surface or 6H-SiC (01-14) surface are described as equivalent to Si (100) surface, and even in Si, (100) surface, (110) surface The mobility is higher in the order of (111) planes. This is explained by the fact that the lower the surface density of the atoms, the lower the interface state density, the less the conduction electrons trapped in the interface states, and the less Coulomb scattering from the trapped electrons. Yes. Patent Document 2 describes a MOSFET using a 4H—SiC (03-38) plane or a 6H—SiC (01-14) plane.

Using these characteristics for SiC-UMOSFET, in Patent Document 3, the main surface is the SiC (000-1) surface, and the groove of the gate trench penetrates from the main surface to the source and base layers and penetrates to the drift layer. In addition, in the proposal of a structure with the (11-20) plane as a trench sidewall and in Patent Document 4, the SiC (000-1) plane is the main surface, and the groove of the gate trench drifts from the main surface through the source and base layers. There has been proposed a structure that penetrates the layer and has the (1-100) plane as a trench sidewall.
Further, in Patent Document 5, various cases in which the main surface is the (1-100) plane, the (0001) plane, and the (11-20) plane while using the (11-20) plane as the MOS channel plane. Proposals have been made.
Japanese Patent No. 3460585 JP 2002-261275 A Japanese Patent Laid-Open No. 9-19724 Japanese Patent Laid-Open No. 10-247732 Japanese Unexamined Patent Publication No. 7-11016 Hiroshi Yano, Taichi Hirao, Tsuneenobu kimoto, and Hiroyuki Matsunami “Sio Itsu / SIC Interface Properties on Various Surface Orientations” ), Materials Research Society Symposium Proceding (Mat. Res. Soc. Symp. Proc., Vol.742, 2003 Materials Research Society pp.219-226)

However, when manufacturing a UMOSFET on a hexagonal silicon carbide wafer, if the main surface is the (000-1) plane as in Patent Documents 3 and 4, screw dislocations or micropipes parallel to the crystal c-axis There was a problem that the hollow defect called reached the outermost surface on which the UMOSFET was fabricated, causing an increase in leakage current and a decrease in breakdown voltage during reverse bias.
In Patent Document 5, a SiC wafer having the (11-20) plane as the main surface is etched to expose the (11-20) plane as the MOS interface, but this (11-20) side wall is the main surface. The angle needs to be 60 ° with respect to the surface, and there is a problem that etching is difficult as compared with the vertical side wall.
Further, as described in Patent Document 5, a method of digging a trench perpendicularly to a wafer having a (1-100) plane as a main surface to form a (11-20) plane and forming a MOS structure on that plane is as follows. The corner at the bottom of the trench has a right angle, and the electric field concentrates at this corner, causing a problem that dielectric breakdown is caused at a reverse voltage lower than the dielectric strength defined by the parallel plate pn junction. Even in the methods in Patent Document 3 and Patent Document 4, the mobility is still insufficient. Another problem is that if the angle at the bottom of the trench is a right angle, electric field concentration occurs, leading to early dielectric breakdown.

In order to solve the above problems while ensuring the mobility and suppressing the resistance of the MOS channel part, the first conductivity type whose main surface is a plane whose angle formed with the (1-100) plane is within 5 ° base layer is a second conductivity type on a wafer having a drift layer which is a first conductivity type Chi also the same structure as the substrate in der Ru carbonization silicon semiconductor substrate, the source layer is a first conductivity type Are sequentially formed , a MOS structure having a trench that penetrates the source layer and the base layer and reaches the drift layer, and an insulating layer and a gate electrode in the trench, and the angle of the trench sidewall parallel to or forming [0001] is 10 It is preferable that the silicon carbide semiconductor element has a trench sidewall such that the angle formed by the {1-100} plane and the sidewall is 60 ° ± 10 °.

Since the (1-100) plane is a plane perpendicular to the c-axis, screw dislocations and micropipes are not exposed on the main surface, so that the dislocation density can be greatly reduced. Furthermore, the trench bottom corners Using the above trench sidewalls becomes obtuse, electric field concentration Ru is relaxed.

According to the present invention, by specifying the plane orientation of the main surface and the plane orientation of the trench sidewall, there is an effect that the on-resistance can be reduced by improving the mobility and the yield can be improved.

FIG. 1 is a sectional view showing a manufacturing process of a MOSFET having a trench according to an embodiment of the present invention. First, on the n-type 4H-SiC or 6H-SiC substrate 1 whose main surface is an angle formed with the (11-20) plane within 5 °, n of 5 μm and 10 ¹⁶ cm ^-3 are sequentially deposited by thermal CVD. A type drift layer 2, a 1 μm, 10 ¹⁷ cm ⁻³ p-type base layer ^{3, and} a 0.5 μm, 10 ¹⁹ cm ⁻³ n-type source layer 4 are formed by epitaxial growth (FIG. 1A).
The substrate 1 is etched to 70 ° or more by a reactive ion etching method to a depth at which the source layer 4 and the base layer 3 can be partially removed completely . In this case , the trench 11 is etched to a depth of 2.1 μm. Form. In this embodiment, the angular MOS interface formed with the 4H-SiC (03-38) plane surface or 6H-SiC corners within 10 ° formed by the (01-14) plane of the trench sidewall is plane within 10 ° Thus, etching was performed so that the long side of the rectangle on the outer periphery of the trench when viewed from the <11-20> direction had an angle of 54.7 ° from the <1-100> direction.
After forming the trench 11 in this way, a gate oxide film 6 of about 30 nm is formed. Further, poly-Si doped with boron is deposited so as to cover the entire gate trench, thereby forming the gate electrode 7. Further, only the surface of the poly-Si gate electrode 7 is oxidized to form an oxide film as an interlayer insulating film 10 (FIG. 1B).
Thereafter, a part of the n-type source layer 4 is selectively removed by reactive ion etching until the p-type base layer 3 is exposed. Thereafter, a metal electrode 8a is formed on the exposed p base layer 3 (FIG. 1 (c)).

Thereafter, a metal for n source contact is formed to form the source electrode 8, and the oxide film on the back surface is removed to form the drain electrode 9. (FIG. 1 (d)).
Hereinafter, an embodiment in which the surface orientation of the main surface of the substrate on which the source electrode and the gate electrode of UMOSFET (trench MOSFET) are formed and the surface orientation of the trench sidewall will be described.

2A and 2B are structural diagrams for illustrating the plane orientation of the semiconductor substrate 14 and the plane orientation of the trench 11, wherein FIG. 2A is a plan view and FIG. 2B is a cross-sectional view taken along line AA of FIG. Semiconductor such angular MOS interface formed with the 4H-SiC (03-38) plane surface or 6H-SiC corners within 10 ° formed by the (01-14) plane of the side wall of the trench 11 becomes a plane within 10 ° Etching is performed so that the long side of the outer periphery of the trench as viewed from the main surface <11-20> direction of the substrate 14 is at an angle of 54.7 ° from the <1-100> direction. The side walls are more than 70 ° with respect to the main surface and in this case are etched vertically.
FIG. 3 is a structural diagram for illustrating the plane orientation of the semiconductor substrate 14 and the plane orientation of the trench 11. The length of the rectangle on the outer periphery of the trench when viewed from the direction of the main surface <11-20> of the semiconductor substrate 14 so that the angle formed by the MOS interface on the side wall of the trench 11 is within 10 ° with the (1-100) plane Etching is performed so that the sides are perpendicular to the <1-100> direction.
4A and 4B are structural views for showing the plane orientation of the semiconductor substrate 14 and the plane orientation of the trench 11, wherein FIG. 4A is a plan view and FIG. 4B is a cross-sectional view taken along line AA in FIG. Semiconductor such angular MOS interface formed with the 4H-SiC (03-38) plane surface or 6H-SiC corners within 10 ° formed by the (01-14) plane of the side wall of the trench 11 becomes a plane within 10 ° The shape of the outer periphery of the trench when viewed from the main surface <11-20> direction of the substrate 14 is a rhombus or a parallelogram, and the pair of surfaces are inclined by 54.7 ° with respect to the <1-100> direction, and the inner surfaces of the pair of surfaces Etching is performed so that the angle formed by becomes 70.6 °.

FIG. 5 is a structural diagram for illustrating the plane orientation of the semiconductor substrate 14 and the plane orientation of the trench 11. The shape of the outer periphery of the trench 11 when viewed from the main surface <11-20> direction of the semiconductor substrate 14 is a rhombus or a parallelogram, and a pair of sides and a side surface extending below the pair are parallel to the <0001> direction (1 -100) plane, and the 4H-SiC (03-38) plane or 6H-SiC (01-14) plane is formed by etching so that the angle formed with the plane is 144.7 °. The main surface is a surface whose angle formed with <11-20> is within 5 °, and the trench 11 is a surface whose angle formed with respect to the surface orientation is within 10 °.
FIG. 6 is a structural diagram for illustrating the plane orientation of the semiconductor substrate 14 and the plane orientation of the trench 11. The shape of the outer periphery of the trench 11 when viewed from the main surface <11-20> direction of the semiconductor substrate 14 is a hexagon. If numbers 1 to 6 are assigned to each side surface of the trench 11, the surfaces 1 and 4 are 4H-SiC (03-38) or 6H-SiC (5H) with an angle of 54.7 ° to the <1-100> direction. 01-14). Surfaces 2 and 5 form an angle of 54.7 °, similar to the <1-100> direction, and 4H-SiC (03-38) surface, which is different from surfaces 1 and 4 that form an angle of 70.6 ° with surfaces 1 and 4 Alternatively, it is a 6H-SiC (01-14) plane. Further, the surfaces 3 and 6 are parallel to the <0001> direction and are (1-100) surfaces. The main surface is a surface whose angle with respect to the plane orientation is within 5 °, and the trench 11 is a surface whose angle with respect to the plane orientation is within 10 °.
In Example 1, the side wall of the gate trench can be formed perpendicular to the main surface, and the range of etching conditions has been expanded.
By using a substrate having the (11-20) plane as the main surface, the conventional substrate having the (000-1) plane as the main surface has a defect density of 100 / cm ² and a device yield of 90%. Although the area was 10 ⁻³ cm ² (300 μm square), the defect density was reduced to 1 piece / cm ^2, and the device area where 90% yield was obtained increased to 0.1 cm ² (3 mm square).
Regarding mobility, when the 4H-SiC (03-38) surface or 6H-SiC (01-14) surface is the MOS interface, it is 200 cm ² / Vs, and when the (1-100) surface is the MOS interface, A value comparable to that of the conventional technology of 100 cm ² / Vs was obtained.

In the process cross-sectional view of the manufacturing process of FIG. 1, the n-type 4H-SiC having the (03-38) plane as the main surface or the n-type 6H-SiC substrate 1 having the (01-14) plane as the main surface in sequence, 5μm by a thermal CVD method, 10 ¹⁶ cm ^-3 of n-type drift layer 2,1μm, 10 ¹⁷ cm ^-3 of p-type base layer 3,0.5Myuemu, a 10 ¹⁹ cm n-type source layer 4 ^-3 is epitaxially grown. The substrate 1 is etched to 70 ° or more by a reactive ion etching method to a depth at which the source layer 4 and the base layer 3 can be partially removed completely . In this case , the trench 11 is etched to a depth of 2.1 μm. Form. In this case, the rectangular length of the outer periphery of the trench when viewed from the 4H-SiC <03-38> or 6H-SiC <01-14> direction so that the MOS interface on the sidewall of the trench 11 is the (11-20) plane. Etch so that the sides are parallel to the <1-100> direction. Thereafter, a gate oxide film 6 having a thickness of about 30 nm is formed. Further, poly-Si doped with boron is deposited so as to cover the entire gate trench, thereby forming the gate electrode 7. Further, only the surface of the poly-Si electrode is oxidized to form an oxide film as the interlayer insulating film 10. Thereafter, a part of the n-type source layer 4 is selectively removed by reactive ion etching until the p-type base layer 3 is exposed. Thereafter, a metal electrode 8 a is formed on the exposed p base layer 3. Thereafter, a metal for n source contact is formed to form the source electrode 8, and the oxide film on the back surface is removed to form the drain electrode 9. 7A and 7B are structural diagrams for illustrating the plane orientation of the semiconductor substrate 14 and the plane orientation of the trench 11, wherein FIG. 7A is a plan view and FIG. 7B is a cross-sectional view taken along line AA of FIG. The outer periphery of the trench when viewed from the main surface 4H-SiC (03-38) surface or 6H-SiC (01-14) surface of the semiconductor substrate 14 so that the MOS interface on the side wall of the trench 11 becomes the (11-20) surface. Etching is performed such that the long side of the rectangle is perpendicular to the <11-20> direction. The main surface is a surface whose angle with respect to the plane orientation is within 5 °, and the trench 11 is a surface whose angle with respect to the plane orientation is within 10 °.
In Example 2, as in Patent Document 5, when the side wall of the trench is at an angle of 60 ° with respect to the main surface with respect to the SiC wafer having the (11-20) plane as the main surface, 60 ° ± The proportion of elements that fall within 10 ° was about 60% in a 2-inch wafer. However, when etched vertically as in the present invention, the proportion of trench sidewalls of 80 ° or more with respect to the main surface was 90%. It improved to more than%.
In addition, a non-defective product that can obtain a withstand voltage of 80% or more of the theoretical withstand voltage by using a substrate whose main surface is the 4H-SiC (03-38) or 6H-SiC (01-14) surface. In the conventional substrate with the (000-1) plane as the main surface, the element area where 90% yield was obtained was 10 ^-3 cm ² (300 μm square), but 1 cm ² (3.3 mm square).
Furthermore, with regard mobility (000-1) as in the case where the surface was MOS interface was mobility of 75 cm ² / Vs is by a MOS interface (the 11-20) plane, 150 cm ² / Vs increased, and the MOS channel resistance was reduced to 1/2.
In the case of a pn diode that does not include a gate trench, when a substrate with a {1-100} surface as the main surface is defined as a non-defective product that can withstand a withstand voltage of 80% or more of the theoretical withstand voltage. In the substrate with the (000-1) plane as the main surface, the element area where 90% yield was obtained was 10 ⁻³ cm ² (300 μm square), but increased to 0.1 cm ² (3.3 mm square). .
Furthermore, when a UMOSFET is fabricated on a substrate having {1-100} as the main surface, the withstand voltage that can be achieved by 80% of the total number of elements is a theoretical value of 60 when the gate trench is etched vertically. However, when a MOS structure is fabricated on a surface as close to the {1-100} plane as possible, it is 70% of the theoretical value, and as much as possible the 4H-SiC {03-38} plane or 6H-SiC {01 When the MOS structure was fabricated on a surface close to the -14} surface, the theoretical value was 80%, and the effect of increasing the dielectric strength with increasing corner angle outside the silicon carbide at the bottom of the trench was obtained.
When a UMOSFET is fabricated on a substrate with {0001} or {000-1} as the main surface, the breakdown voltage that can be achieved by 80% of the total number of elements is the theoretical value when the gate trench is etched vertically. When the MOS structure is fabricated on the surface as close to the 4H-SiC {03-38} surface or 6H-SiC {01-14} surface as much as possible, it becomes 80% of the theoretical value. The effect was obtained that the withstand voltage improved as the corner angle outside the silicon carbide at the bottom of the trench increased.
Also, the mobility was 150cm ² / Vs for both (11-20) plane and (1-100) plane , but on 4H-SiC {03-38} plane or 6H-SiC {01-14} plane By forming a MOS structure, a value of 200 cm ² / Vs was obtained, and the channel resistance could be reduced.

In the process cross-sectional view of the manufacturing process of FIG. 1, an n-type 4H-SiC or 6H-SiC substrate 1 having a (1-100) plane as a main surface is sequentially deposited by thermal CVD to 5 μm and 10 ¹⁶ cm ⁻³ n. -type drift layer 2,1μm, 10 ¹⁷ cm ^-3 of p-type base layer 3,0.5Myuemu, a 10 ¹⁹ cm n-type source layer 4 ^-3 is epitaxially grown. The substrate 1 is etched to 70 ° or more by a reactive ion etching method to a depth at which the source layer 4 and the base layer 3 can be partially removed completely . In this case , the trench 11 is etched to a depth of 2.1 μm. Form. Thereafter, a gate oxide film 6 having a thickness of about 30 nm is formed. Further, poly-Si doped with boron is deposited so as to cover the entire gate trench, thereby forming the gate electrode 7. Further, only the surface of the poly-Si electrode is oxidized to form an oxide film as the interlayer insulating film 10. Thereafter, a part of the n-type source layer 4 is selectively removed by reactive ion etching until the p-type base layer 3 is exposed. Thereafter, a metal electrode 8 a is formed on the exposed p base layer 3. Thereafter, a metal for n source contact is formed to form the source electrode 8, and the oxide film on the back surface is removed to form the drain electrode 9.

8A and 8B are structural views for showing the plane orientation of the semiconductor substrate 14 and the plane orientation of the trench 11, wherein FIG. 8A is a plan view and FIG. 8B is a cross-sectional view taken along line AA of FIG. In this case, the rectangular long side of the outer periphery of the trench when viewed from the [1-100] direction so that the MOS interface on the sidewall of the trench 11 becomes a pair of opposed (01-10) plane and (-1010) plane is Etching is performed to 60 ° ± 10 ° so that an angle formed by a plane parallel to [0001] and including the long side of the outer periphery of the trench with respect to the (1-100) plane is as close to 60 ° as possible. To etch Thus at an oblique angle, the method comprising an etching mask in a tapered shape, it is effective to promote the lateral etching in the gas pressure. The main surface is a surface whose angle with respect to the plane orientation is within 5 °, and the trench 11 is a surface whose angle with respect to the plane orientation is within 10 °.
9A and 9B are structural views for showing the plane orientation of the semiconductor substrate 14 and the plane orientation of the trench 11, wherein FIG. 9A is a plan view, FIG. 9B is a cross-sectional view taken along line AA in FIG. These are explanatory drawings for demonstrating the crystal plane of the side wall of a trench. The MOS interface on the side wall of the trench 11 is a pair of 4H-SiC (03-38) plane and 4H-SiC (0-338) plane or 6H-SiC (01-14) plane and 6H-SiC (0-114) facing each other. When viewed from the [01-10] direction so as to be a plane, the long side of the outer periphery of the trench is parallel to the [-2110] direction and the plane including the long side of the outer periphery of the trench is (01-10 Etching is performed at 35.3 ° ± 10 ° so that the angle formed with respect to the surface is as close to 35.3 ° as possible. The main surface is a surface whose angle with respect to the plane orientation is within 5 °, and the trench 11 is a surface whose angle with respect to the plane orientation is within 10 °.

In the process cross-sectional view of the manufacturing process of FIG. 1, an n-type 4H-SiC or 6H-SiC substrate 1 having a (1-100) plane as a main surface is sequentially deposited by thermal CVD to 5 μm and 10 ¹⁶ cm ⁻³ n. -type drift layer 2,1μm, 10 ¹⁷ cm ^-3 of p-type base layer 3,0.5Myuemu, a 10 ¹⁹ cm n-type source layer 4 ^-3 is epitaxially grown. The substrate 11 is etched to 70 ° or more by reactive ion etching to a depth at which the source layer 4 and the base layer 3 can be completely removed . In this case , the trench 11 is etched to a depth of 2.1 μm. Form. Thereafter, a gate oxide film 6 having a thickness of about 30 nm is formed. Further, poly-Si doped with boron is deposited so as to cover the entire gate trench, thereby forming the gate electrode 7. Further, only the surface of the poly-Si electrode is oxidized to form an oxide film. Thereafter, a part of the n-type source layer 4 is selectively removed by reactive ion etching until the p-type base layer 3 is exposed. Thereafter, a metal electrode 8 a is formed on the exposed p base layer 3. Thereafter, a metal for n source contact is formed to form the source electrode 8, and the oxide film on the back surface is removed to form the drain electrode 9.

10A and 10B are structural views for showing the plane orientation of the semiconductor substrate 14 and the plane orientation of the trench 11, wherein FIG. 10A is a plan view, and FIG. 10B is a cross-sectional view of the main surface taken along line AA in FIG. (C) is sectional drawing of the main back surface of an AA line. In this case, the long side of the outer periphery of the trench 11 when viewed from the <0001> direction is parallel to [-2110], and the surface including the long side of the outer periphery of the trench forms the (0001) plane. Etch to 54.7 ° ± 10 ° so that the angle is as close to 54.7 ° as possible. Then, a surface close to the 4H-SiC {03-38} plane or the 6H-SiC {01-14} plane can be exposed. To etch Thus at an oblique angle, the method comprising an etching mask in a tapered shape, it is effective to promote the lateral etching in the gas pressure. The main surface is a surface whose angle with respect to the plane orientation is within 5 °, and the trench 11 is a surface whose angle with respect to the plane orientation is within 10 °.

  It can be applied not only to power conversion devices such as inverter devices using MOSFETs and IGBTs, but also to switching elements for automotive electrical components with severe usage environments such as temperature.

Cross-sectional process diagram showing UMOSFET fabrication process Structure diagram when 4H (03-38) or 6H (01-14) surface is used as a trench sidewall Structure diagram when (1-100) plane is trench side wall Structural diagram when trench sidewall is composed of two different 4H-SiC (03-38) or 6H-Si (01-14) surfaces Structure diagram when a trench side wall composed of a pair of 4H-SiC (03-38) or 6H-Si (01-14) and a pair of (1-100) is configured Structure diagram of trench side wall composed of two pairs of 4H-SiC (03-38) plane or 6H-Si (01-14) plane and a pair of (1-100) planes Structure diagram with 4H-SiC (03-38) or 6H-Si (01-14) as the main surface and (11-20) as the trench sidewall Structure diagram when {1-100} plane is the main surface and different {1-100} planes with an angle of 60 ° with the main surface are exposed Structural drawing when the 4H-SiC {03-38} or 6H-SiC {01-14} surface with the {1-100} surface as the main surface and the angle with the main surface being 35.3 ° is exposed When exposing the 4H-SiC {03-38} or 6H-SiC {01-14} surface with the {0001} or {000-1} surface as the main surface and an angle of 54.7 ° with the main surface Structure diagram of Partial sectional view showing a conventional SiC vertical DIMOSFET Partial sectional view showing a conventional SiC vertical UMOSFET Explanatory drawing showing the structure and crystal plane of hexagonal silicon carbide unit cell

DESCRIPTION OF SYMBOLS 1 Silicon carbide substrate 2 N-type drift layer 3 Base region 4 Source region 5 Channel region 6 Gate oxide film 7 Gate electrode 8 Source electrode 9 Drain electrode 10 Interlayer insulating film 11 Trench 14 Semiconductor substrate

Claims (1)

On the silicon carbide semiconductor substrate, which is the first conductivity type, whose main surface is an angle formed with the (1-100) plane within 5 °, the first conductivity type drift layer has the same structure as the substrate. A base layer which is the second conductivity type and a source layer which is the first conductivity type are sequentially formed on the wafer, a trench which penetrates the source layer and the base layer and reaches the drift layer, and an insulating layer and a gate in the trench MOS structure with electrodes, where the trench sidewalls are parallel or formed with [0001] or less than 10 °, and the angle between the {1-100} surface and sidewalls is 60 ° ± 10 ° A silicon carbide semiconductor element characterized by being a trench side wall.

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