JP5564781B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device and a manufacturing method thereof, and more particularly, to a silicon carbide semiconductor device exhibiting excellent electrical characteristics and a manufacturing method thereof.

Conventionally, a silicon carbide semiconductor device using silicon carbide (SiC) is known, and an example thereof is described in, for example, International Publication No. 01/018872 pamphlet (hereinafter referred to as “Patent Document 1”). Yes. Patent Document 1 describes a MOS field effect transistor (MOSFET) as a silicon carbide semiconductor device having a plane orientation of approximately {03-38} and formed using a 4H type polytype SiC substrate. In the MOSFET described in Patent Document 1, the gate oxide film is formed by dry oxidation, and high channel mobility (about 100 cm ² / Vs) can be realized.
International Publication No. 01/018872 Pamphlet

  In order to stably exhibit the excellent electrical characteristics of the silicon carbide semiconductor device using SiC, it is required to realize high channel mobility with good reproducibility.

  However, as a result of studies by the present inventors, it has been found that the channel mobility may not be sufficiently high even in the MOSFET described in Patent Document 1.

  In view of the above circumstances, an object of the present invention is to provide a silicon carbide semiconductor device capable of realizing high channel mobility with high reproducibility and a method for manufacturing the same.

The present invention relates to a semiconductor layer made of silicon carbide having a surface inclined within a range of 50 ° to 65 ° with respect to the {0001} plane, and an insulating film formed so as to be in contact with the surface of the semiconductor layer. The maximum value of the nitrogen concentration in the region within 10 nm from the interface between the surface of the semiconductor layer and the insulating film is 1 × 10 ²¹ cm ⁻³ or more, and is orthogonal to the <−2110> direction in the surface of the semiconductor layer This is a silicon carbide semiconductor device having a channel length direction within a range of ± 10 °.

The present invention also includes a substrate made of silicon carbide of the first conductivity type, a first conductivity type impurity formed on the surface of the substrate and having a lower concentration than the substrate, and at least 50 ° with respect to the {0001} plane. A semiconductor layer made of silicon carbide of the first conductivity type having a surface inclined within a range of 65 ° or less, a second conductivity type impurity diffusion layer formed in the surface of the semiconductor layer, and a second conductivity type impurity diffusion A first conductivity type impurity diffusion layer formed in the surface of the layer; an insulating film formed so as to be in contact with the surface of the semiconductor layer; and at least a part of a region other than a portion where the insulating film is formed on the surface of the semiconductor layer A source electrode formed so as to be in contact with the gate electrode, a gate electrode formed on the insulating film, and a drain electrode formed on a surface of the substrate opposite to the side on which the semiconductor layer is formed , In a region within 10 nm from the interface with the insulating film The maximum value of the oxygen concentration is not more than 1 × 10 ²¹ cm ^-3, is silicon carbide semiconductor device having a channel length direction in a range of directions ± 10 ° orthogonal to the <-2110> direction in the surface of the semiconductor layer .

Further, the present invention includes a substrate made of silicon carbide of the first conductivity type, and a first conductivity type impurity formed on the substrate and having a lower concentration than the substrate, and is 50 ° to 65 ° with respect to the {0001} plane. A semiconductor layer made of silicon carbide of the first conductivity type having a surface inclined within the following range, a second conductivity type impurity diffusion layer formed in the surface of the semiconductor layer, and a second conductivity type impurity diffusion layer. The first conductivity type impurity diffusion layer formed in the surface, the insulating film formed so as to be in contact with the surface of the semiconductor layer, and a part of the region other than the insulating film forming portion on the surface of the semiconductor layer A source electrode formed in such a manner, a drain electrode formed so as to be in contact with another part of the region other than the insulating film forming portion on the surface of the semiconductor layer, and a gate electrode formed on the insulating film. includes, within 10nm from the interface between the surface and the insulating film of the semiconductor layer And the maximum value of the nitrogen concentration is less than 1 × 10 ²¹ cm ^-3 in the region, the silicon carbide semiconductor having a channel length direction in a range of directions ± 10 ° orthogonal to the <-2110> direction in the inner surface of the semiconductor layer Device.

  Here, in the silicon carbide semiconductor device of the present invention, the surface of the source electrode is preferably striped.

  In the silicon carbide semiconductor device of the present invention, it is preferable that the surface of the source electrode has a honeycomb shape.

  In the silicon carbide semiconductor device of the present invention, the surface of the semiconductor layer is preferably a crystal plane inclined within a range of ± 5 ° with respect to the {03-38} plane.

Furthermore, the present invention includes a step of forming a semiconductor layer made of silicon carbide having a surface inclined within a range of 50 ° to 65 ° with respect to the {0001} plane, and <−2110 within the surface of the semiconductor layer. The step of investigating the direction orthogonal to the direction, and a part of the surface of the semiconductor layer so that the channel length direction is formed within the range of ± 10 ° in the direction orthogonal to the <−2110> direction in the surface of the semiconductor layer And adjusting the nitrogen concentration so that the maximum value of the nitrogen concentration in a region within 10 nm from the interface between the surface of the semiconductor layer and the insulating film is 1 × 10 ²¹ cm ⁻³ or more. A method of manufacturing a silicon carbide semiconductor device including a process.

  Here, in the method for manufacturing a silicon carbide semiconductor device of the present invention, it is preferable to investigate the direction orthogonal to the <−2110> direction in the surface of the semiconductor layer based on the orientation of the defects contained in the semiconductor layer.

  In the method for manufacturing a silicon carbide semiconductor device of the present invention, the step of adjusting the nitrogen concentration preferably includes a step of heat-treating the semiconductor layer on which the insulating film is formed in an atmosphere of a nitrogen-containing gas.

  In the method for manufacturing a silicon carbide semiconductor device of the present invention, the step of adjusting the nitrogen concentration preferably includes a step of heat-treating the semiconductor layer after the heat treatment in an inert gas atmosphere.

  ADVANTAGE OF THE INVENTION According to this invention, the silicon carbide semiconductor device which can implement | achieve high channel mobility with sufficient reproducibility, and its manufacturing method can be provided.

  Embodiments of the present invention will be described below. In the drawings of the present invention, the same reference numerals represent the same or corresponding parts.

  In addition, when expressing the crystal plane and direction, it should be expressed by adding a bar on the required number. However, because there are restrictions on the expression means, in the present invention, the required number Instead of the expression with a bar above, “−” is added in front of the required number. In the present invention, the individual orientation is represented by [], the collective orientation is represented by <>, the individual plane is represented by (), and the collective plane is represented by {}.

<Embodiment 1>
FIG. 1 shows a schematic cross-sectional view of an example of a vertical DiMOSFET (Double Implanted Metal Oxide Semiconductor Field Effect Transistor) which is an example of the silicon carbide semiconductor device of the present invention.

  A silicon carbide semiconductor device 1 shown in FIG. 1 includes, for example, a substrate 11 made of silicon carbide of n-type and polytype 4H—SiC, and a semiconductor layer 12 made of n-type silicon carbide formed on the surface 11 a of the substrate 11. A second conductivity type impurity diffusion layer 14 which is a p-type region formed in the surface 12a of the semiconductor layer 12, and a surface of the second conductivity type impurity diffusion layer 14 (also in the surface 12a of the semiconductor layer 12). The first conductivity type impurity diffusion layer 15, which is an n-type region, the insulating film 13 formed in contact with the surface 12 a of the semiconductor layer 12, and the insulating film 13 on the surface 12 a of the semiconductor layer 12 are formed. A source electrode 16 formed in a region other than the region, a gate electrode 17 formed on the surface of the insulating film 13, and a drain electrode 18 formed on the back surface of the substrate 11 are provided.

  Here, the surface 11a of the substrate 11 on which the semiconductor layer 12 is formed is a crystal plane inclined within a range of 50 ° to 65 ° with respect to the {0001} plane.

Further, as the semiconductor layer 12, for example, it can be used such as a layer of a low have n-type silicon carbide in the n-type impurity concentration than the substrate 11. Further, the surface 12a of the semiconductor layer 12 is also a crystal plane inclined within a range of 50 ° to 65 ° with respect to the {0001} plane.

  As the insulating film 13, for example, an oxide film formed by dry oxidation (thermal oxidation) or the like can be used. The insulating film 13 is not limited to a one-layer structure, and may have a two-layer structure or more.

  In addition, as the second conductivity type impurity diffusion layer 14, for example, a p type region formed by diffusing a p type impurity as the second conductivity type impurity in the surface 12a of the semiconductor layer 12 can be used. Here, as the p-type impurity as the second conductivity type impurity, for example, aluminum, boron or the like can be used. Further, the second conductivity type having a higher concentration than the second conductivity type impurity diffusion layer 14 is formed in at least a part of the region other than the formation region of the first conductivity type impurity diffusion layer 15 in the surface of the second conductivity type impurity diffusion layer 14. A p + -type region containing a p-type impurity as an impurity may be formed.

  In addition, as the first conductivity type impurity diffusion layer 15, for example, an n type region formed by diffusing an n type impurity as the first conductivity type impurity in the surface 12 a of the semiconductor layer 12 can be used. The n-type impurity concentration as the first conductivity type impurity in the first conductivity type impurity diffusion layer 15 can be higher than the n-type impurity concentration as the first conductivity type impurity in the semiconductor layer 12. Here, as the n-type impurity as the first conductivity type impurity, for example, nitrogen, phosphorus or the like can be used.

  The source electrode 16, the gate electrode 17, and the drain electrode 18 can each be made of a conventionally known metal, for example.

In the silicon carbide semiconductor device 1 shown in FIG. 1, the maximum value of the nitrogen concentration in the region within 10 nm from the interface between the semiconductor layer 12 and the insulating film 13 is 1 × 10 ²¹ cm ⁻³ or more. Here, the region within 10 nm from the interface between the semiconductor layer 12 and the insulating film 13 refers to a region that advances from the interface between the semiconductor layer 12 and the insulating film 13 by 10 nm perpendicular to the interface toward the semiconductor layer 12. And a region which is advanced from the interface between the semiconductor layer 12 and the insulating film 13 by 10 nm perpendicular to the interface toward the insulating film 13.

  FIG. 2 is a schematic plan view of silicon carbide semiconductor device 1 shown in FIG. 1 viewed from the gate electrode 17 side. Here, the surface of the source electrode 16 and the surface of the gate electrode 17 are formed so as to extend in a stripe shape in the <−2110> direction, respectively, and the source electrode 16 and the gate electrode in a direction orthogonal to the <−2110> direction. 17 are alternately arranged. Further, one gate electrode 17 is disposed between the two source electrodes 16, and the surface of the insulating film 13 is exposed from the gap between the source electrode 16 and the gate electrode 17. Thus, when the surface of the source electrode 16 is striped, the channel direction is formed within the range of ± 10 ° in the direction orthogonal to the <−2110> direction in the surface 12a of the semiconductor layer 12 as will be described later. It tends to be easy to do. In the present invention, the channel direction means a direction in which carriers move in the surface 12 a of the semiconductor layer 12.

  Here, the channel direction of silicon carbide semiconductor device 1 having the above-described configuration is formed to be included in the range of ± 10 ° in the direction orthogonal to the <−2110> direction in surface 12a of semiconductor layer 12.

  Hereinafter, an example of the manufacturing method of the silicon carbide semiconductor device 1 having the above-described configuration will be described. First, as shown in the schematic cross-sectional view of FIG. 3, from silicon carbide (4H—SiC) having a surface 11a composed of a crystal plane inclined within a range of 50 ° to 65 ° with respect to the {0001} plane. A substrate 11 is prepared.

  Here, as shown in the schematic perspective view of FIG. 4, for example, the substrate 11 having the surface 11a is n-type in which the {0001} plane is exposed by crystal growth in the [0001] direction (c-axis direction). The silicon carbide crystal ingot 10 is sliced in a direction where the angle α ° with respect to the {0001} plane is 50 ° or more and 65 ° or less, and the crystal is inclined at an angle of 50 ° or more and 65 ° or less with respect to the {0001} plane. It can be formed by exposing the surface (shaded portion in FIG. 4).

  Further, the surface 11a of the substrate 11 inclined within the range of 50 ° to 65 ° with respect to the {0001} plane is, for example, a {03-38} plane as shown in the schematic cross-sectional view of FIG. On the other hand, the crystal plane is preferably tilted within a range of ± 5 °. When the surface 11a of the substrate 11 is a crystal plane inclined within a range of ± 5 ° with respect to the {03-38} plane, electrical characteristics such as channel mobility of the silicon carbide semiconductor device 1 are improved. There is a tendency. Further, from the viewpoint of further improving the electrical characteristics such as channel mobility of the silicon carbide semiconductor device 1, a crystal in which the surface 11a of the substrate 11 is inclined within a range of ± 3 ° with respect to the {03-38} plane. More preferably, the surface 11a of the substrate 11 is the {03-38} plane. A crystal plane inclined within a range of ± 5 ° with respect to the {03-38} plane and a crystal plane inclined within a range of ± 3 ° with respect to the {03-38} plane are each {03 Needless to say, the −38} plane is included.

  Next, as shown in the schematic cross-sectional view of FIG. 6, the semiconductor layer 12 is formed on the surface 11 a of the substrate 11.

Here, the semiconductor layer 12 can be formed by, for example, epitaxially growing the semiconductor layer 12 made of n-type silicon carbide having n-type impurities at a lower concentration than the substrate 11 on the surface 11 a of the substrate 11. it can. When the semiconductor layer 12 is formed by the above-described epitaxial growth, the crystal plane of the surface 11a of the substrate 11 can be inherited by the surface 12a of the semiconductor layer 12, so that the surface 12a of the semiconductor layer 12 is made to the {0001} plane. The crystal plane can be inclined within a range of 50 ° to 65 °.

  For the same reason as described above, the surface 12a of the semiconductor layer 12 is preferably a crystal plane inclined within a range of ± 5 ° with respect to the {03-38} plane, and the {03-38} plane Is more preferably a crystal plane inclined within a range of ± 3 ° with respect to the angle, and most preferably a {03-38} plane. Also here, the crystal plane inclined within the range of ± 5 ° with respect to the {03-38} plane and the crystal plane inclined within the range of ± 3 ° with respect to the {03-38} plane are also included. Needless to say, each includes the {03-38} plane.

  Next, as shown in the schematic plan view of FIG. 7, the direction orthogonal to the <−2110> direction in the surface 12 a of the semiconductor layer 12 is investigated.

  Here, the direction orthogonal to the <−2110> direction in the surface 12 a of the semiconductor layer 12 can be investigated based on, for example, defects included in the semiconductor layer 12. That is, in the manufacturing process of the silicon carbide semiconductor device 1, defects may be formed at certain locations in the semiconductor layer 12, so that the position of the defects formed at certain locations in the semiconductor layer 12 is used as a reference. Thus, the direction orthogonal to the <−2110> direction can be specified in the surface 12 a of the semiconductor layer 12. Further, based on the surface morphology of the semiconductor layer 12, the direction orthogonal to the <−2110> direction can be specified in the surface 12 a of the semiconductor layer 12.

  Next, as shown in the schematic cross-sectional view of FIG. 8, the second conductivity type impurity diffusion layer 14 is formed in the surface 12 a of the semiconductor layer 12. In this example, the second conductivity type impurity diffusion layer 14 is formed in a stripe shape extending in the <-2110> direction, but is not limited to this shape.

  Here, the second conductivity type impurity diffusion layer 14 is formed, for example, after an ion implantation prevention mask is provided in a region other than the formation region of the second conductivity type impurity diffusion layer 14 in the surface 12 a of the semiconductor layer 12. A p-type impurity ion as a type impurity can be formed by ion implantation into the surface 12 a of the semiconductor layer 12. As the ion implantation preventing mask, for example, an oxide film patterned by photolithography and etching can be used.

  Next, as shown in the schematic cross-sectional view of FIG. 9, the first conductivity type impurity diffusion layer 15 is formed in the surface of the second conductivity type impurity diffusion layer 14 formed as described above. In this example, the first conductivity type impurity diffusion layer 15 is also formed in a stripe shape extending in the <−2110> direction, but is not limited to this shape.

  Here, the first conductivity type impurity diffusion layer 15 is formed, for example, after an ion implantation prevention mask is provided in a region other than the formation region of the first conductivity type impurity diffusion layer 15 in the surface 12 a of the semiconductor layer 12. An n-type impurity ion as a type impurity can be formed by ion implantation into the surface 12 a of the semiconductor layer 12. Here, as the ion implantation preventing mask, for example, an oxide film patterned by photolithography and etching can be used.

  Next, activation annealing is performed on the semiconductor layer 12 after the formation of the second conductivity type impurity diffusion layer 14 and the first conductivity type impurity diffusion layer 15 as described above. Thus, the p-type impurity as the second conductivity type impurity in the second conductivity type impurity diffusion layer 14 ion-implanted as described above and the n type impurity as the first conductivity type impurity in the first conductivity type impurity diffusion layer 15 are obtained. Can be activated.

  Here, the activation annealing treatment is performed at a temperature of about 1700 ° C., for example, on the semiconductor layer 12 after the formation of the second conductivity type impurity diffusion layer 14 and the first conductivity type impurity diffusion layer 15 in an argon gas atmosphere. This can be done by heating for about a minute.

  Next, as shown in the schematic cross-sectional view of FIG. 10, the insulating film 13 in contact with the entire surface 12a of the semiconductor layer 12 after the formation of the second conductivity type impurity diffusion layer 14 and the first conductivity type impurity diffusion layer 15 is formed. Form.

  Here, as the insulating film 13, for example, an oxide film formed by dry oxidation (thermal oxidation) or the like can be used. The dry oxidation (thermal oxidation) is performed, for example, in the air on the surface 12a of the semiconductor layer 12 on which the second conductive type impurity diffusion layer 14 and the first conductive type impurity diffusion layer 15 formed as described above are formed. For example, it can be performed by heating at a temperature of about 1200 ° C. for about 30 minutes.

Next, a nitrogen annealing process is performed on the semiconductor layer 12 after the formation of the insulating film 13. Thereby, the nitrogen concentration is adjusted so that the maximum value of the nitrogen concentration in a region within 10 nm from the interface between the semiconductor layer 12 and the insulating film 13 is 1 × 10 ²¹ cm ⁻³ or more.

Here, the above-mentioned nitrogen annealing treatment is performed, for example, by subjecting the semiconductor layer 12 after the formation of the insulating film 13 to 120 ° C. at a temperature of about 1100 ° C. in a gas atmosphere containing nitrogen such as nitrogen monoxide (NO) gas. By performing heating for about a minute, the maximum value of the nitrogen concentration in a region within 10 nm from the interface between the semiconductor layer 12 and the insulating film 13 can be set to 1 × 10 ²¹ cm ⁻³ or more.

  Further, it is preferable that the semiconductor layer 12 after the nitrogen annealing treatment is further subjected to an inert gas annealing treatment in an atmosphere of an inert gas such as argon gas. When the inert gas annealing process is performed on the semiconductor layer 12 after the nitrogen annealing process, the tendency for the silicon carbide semiconductor device 1 to achieve high channel mobility with high reproducibility increases.

  Here, the above-described inert gas annealing treatment can be performed by heating the semiconductor layer 12 after the above-described nitrogen annealing treatment at a temperature of about 1100 ° C. for about 60 minutes, for example, in an atmosphere of argon gas. .

  Next, as shown in the schematic cross-sectional view of FIG. 11, a part of the insulating film 13 formed as described above is removed, and the insulating film 13 is patterned.

  Here, the patterning of the insulating film 13 is performed in the channel direction within a range of ± 10 ° in the direction orthogonal to the <−2110> direction in the surface 12a of the semiconductor layer 12 as shown in the schematic plan view of FIG. To be included. That is, in the patterning of the insulating film 13, the channel direction is in the range of −10 ° from the direction −20 ° perpendicular to the <−2110> direction in the surface 12 a of the semiconductor layer 12 to + 10 ° from the direction perpendicular to the <−2110> direction. It is performed so as to be parallel to either direction.

  The insulating film 13 is partially removed by, for example, forming an etching mask patterned on the surface of the insulating film 13 so that the removed portion of the insulating film 13 is exposed by photolithography and etching. 13 can be formed by removing the exposed portion by etching.

  Next, as shown in FIG. 1, the source electrode 16 is formed so as to be in contact with the surface of the first conductivity type impurity diffusion layer 15 in the surface 12 a of the semiconductor layer 12 exposed from the removed portion of the insulating film 13.

  Here, the source electrode 16 is formed by, for example, sputtering a conductive film made of a metal such as nickel on the surface 12a of the semiconductor layer 12 exposed after the etching of the insulating film 13 and the surface of the etching mask. After the formation, it can be formed by removing the etching mask. That is, the conductive film formed on the surface of the etching mask is removed (lifted off) together with the etching mask, and only the conductive film formed on the surface 12 a of the semiconductor layer 12 remains as the source electrode 16.

  In addition, it is preferable that the semiconductor layer 12 after the formation of the source electrode 16 is subjected to heat treatment for alloying.

  Here, as the heat treatment for alloying, the semiconductor layer 12 after the formation of the source electrode 16 is heated at a temperature of about 950 ° C. for about 2 minutes in an atmosphere of an inert gas such as argon gas, for example. Can be done.

  Next, as shown in FIG. 1, a gate electrode 17 is formed on the surface of the insulating film 13. Here, the gate electrode 17 is, for example, a resist mask having an opening in a portion where the gate electrode 17 is formed by photolithography and etching so as to cover the entire surface of the insulating film 13 and the surface of the source electrode 16. After forming a conductive film made of a metal such as aluminum on the surface of the resist mask and the surface of the insulating film 13 exposed from the opening of the resist mask by, for example, sputtering, the resist mask is removed. Can be formed. That is, the conductive film formed on the surface of the resist mask is removed (lifted off) together with the resist mask, and only the conductive film formed on the surface of the insulating film 13 remains as the gate electrode 17.

  Next, as shown in FIG. 1, the drain electrode 18 is formed on the back surface of the substrate 11. Here, the drain electrode 18 can be formed by, for example, forming a conductive film made of a metal such as nickel on the back surface of the substrate 11 by, for example, sputtering.

Thus, silicon carbide semiconductor device 1 having the configuration shown in FIG. 1 can be manufactured.
In silicon carbide semiconductor device 1 of the present invention, for example, as shown in the schematic plan view of FIG. 13, the surface of source electrode 16 is formed in a honeycomb shape, and a partial region surrounding the outer periphery of source electrode 16 is formed. The excluded region can also be formed as the gate electrode 17.

  As described above, when the surface of the source electrode 16 is formed in a honeycomb shape, the surface of each source electrode 16 is formed in a hexagonal shape, and in particular, it may be formed in a regular hexagonal shape. preferable. When the surface of each source electrode 16 is formed in a regular hexagonal shape, it becomes easy to form the channel direction within a range of ± 10 ° perpendicular to the <−2110> direction, and the substrate 11 having the same size is formed. Since the number of silicon carbide semiconductor devices 1 that can be formed can be increased even when using the silicon carbide semiconductor device 1, the silicon carbide semiconductor device 1 having high channel mobility can be manufactured with higher reproducibility and higher manufacturing efficiency. There is a tendency.

  The other configuration of silicon carbide semiconductor device 1 having source electrode 16 and gate electrode 17 having the configuration shown in FIG. 13 can be the same as described above.

  In silicon carbide semiconductor device 1 having the configuration described above, for example, when a negative voltage is applied to source electrode 16 and a positive voltage is applied to gate electrode 17 and drain electrode 18, carriers injected from source electrode 16 are injected. (Electrons in the above example) move to the drain electrode 18 through the surface of the first conductivity type impurity diffusion layer 15, the surface of the second conductivity type impurity diffusion layer 14, the inside of the semiconductor layer 12, and the inside of the substrate 11. It will be.

  Even when a negative voltage is applied to the source electrode 16 and a positive voltage is applied to the drain electrode 18, when a positive voltage is not applied to the gate electrode 17, carriers injected from the source electrode 16 (in the above example) The movement of electrons) in the surface of the second conductivity type impurity diffusion layer 14 can be restricted.

In silicon carbide semiconductor device 1 having the above configuration, for example, on surface 11a of substrate 11 inclined within a range of 50 ° to 65 ° with respect to the {0001} plane of n-type silicon carbide (4H—SiC). In addition, the semiconductor layer 12 made of n-type silicon carbide containing the n-type impurity as the first conductivity type impurity having a lower concentration than the substrate 11 can be formed by epitaxial growth. In such a configuration, the surface 12a of the semiconductor layer 12 (a crystal plane inclined within a range of 50 ° to 65 ° with respect to the {0001} plane) is used for a channel in which carriers move. Therefore, it is possible to obtain higher carrier mobility (channel mobility) compared to the case where the {0001} plane is used for the channel.

In silicon carbide semiconductor device 1 having the above-described configuration, for example, as shown in FIG. 14, the maximum value of the nitrogen concentration in a region within 10 nm from the interface between semiconductor layer 12 and insulating film 13 is 1 × 10 ^21. cm ⁻³ or more. Therefore, in the silicon carbide semiconductor device 1 of the present invention, the interface state generated when the insulating film 13 is formed by dry oxidation (thermal oxidation) or the like at the interface between the semiconductor layer 12 and the insulating film 13 can be reduced. Therefore, the second conductivity type impurity diffusion between the first conductivity type impurity diffusion layer 15 and the semiconductor layer 12 in the channel immediately below the insulation film 13 (part of the surface 12a of the semiconductor layer 12 in contact with the insulation film 13). The carrier mobility (channel mobility) in the surface portion of the layer 14 can be stably improved.

FIG. 14 shows an example of the distribution of nitrogen concentration in the vicinity of the interface between insulating film 13 and semiconductor layer 12 in silicon carbide semiconductor device 1 having the configuration described above. Here, in FIG. 14, the vertical axis represents the nitrogen concentration (cm ⁻³ ), and the horizontal axis represents the distance (nm) from the interface between the insulating film 13 and the semiconductor layer 12. Further, in FIG. 14, the position where the horizontal axis distance (nm) is 0 (nm) means the interface between the insulating film 13 and the semiconductor layer 12, and the horizontal axis distance (nm) is 0 (nm). It means that it progresses to the insulating film 13 side as it advances from the position to the left side, and it means that it progresses to the semiconductor layer 12 side as the distance (nm) on the horizontal axis goes from the position of 0 (nm) to the right side. ing.

  Furthermore, since silicon carbide semiconductor device 1 having the above-described configuration has a channel direction within a range of ± 10 ° in a direction orthogonal to the <−2110> direction in surface 12a of semiconductor layer 12, the channel Since carrier movement in the direction becomes smooth and carrier mobility and current characteristics in the channel direction can be improved, the on-resistance of silicon carbide semiconductor device 1 can be reduced.

  FIG. 15 shows the <− in the surface 12a of the semiconductor layer 12 in the silicon carbide semiconductor device 1 having the above-described configuration (a crystal plane inclined within a range of 50 ° to 65 ° with respect to the {0001} plane). An example of the relationship between the angle (°) relative to the 2110> direction and the channel mobility (relative value) is shown. In FIG. 15, the vertical axis represents channel mobility (relative value), and the horizontal axis represents the angle (°) with respect to the <−2110> direction in the surface 12 a of the semiconductor layer 12. Note that the angle (°) of the horizontal axis in FIG. 15 is not limited to the direction of inclination with respect to the <−2110> direction. And a direction inclined by −80 ° is meant.

  Note that the channel mobility (relative value) on the vertical axis in FIG. 15 is expressed as a relative value when the channel mobility in the direction orthogonal to the <−2110> direction in the surface 12a of the semiconductor layer 12 is 1. ing. Further, a 90 ° portion of the angle (°) of the horizontal axis in FIG. 15 indicates a direction orthogonal to the <−2110> direction in the surface 12 a of the semiconductor layer 12.

  As shown in FIG. 15, in the surface 12a of the semiconductor layer 12, when the channel direction is in the direction where the angle with respect to the <-2110> direction is 90 ° (the direction orthogonal to the <-2110> direction), the channel mobility is the highest. It can be seen that the channel mobility tends to decrease as the deviation from the direction orthogonal to the <−2110> direction in the surface 12a of the semiconductor layer 12 increases. Note that the tendency shown in FIG. 15 is established for any crystal plane in which the surface 12a of the semiconductor layer 12 is tilted within a range of 50 ° to 65 ° with respect to the {0001} plane.

  Therefore, from the viewpoint of realizing high channel mobility, the channel direction is a direction orthogonal to the <−2110> direction in the surface 12a of the semiconductor layer 12 (that is, a direction ± perpendicular to the <−2110> direction ± 0 °) is considered most preferable.

  However, as shown in FIG. 15, the angle with respect to the <−2110> direction in the surface 12 a of the semiconductor layer 12 is in the direction of 80 ° or more and 90 ° or less (that is, the range of ± 10 ° in the direction orthogonal to the <−2110> direction) Channel mobility (relative value) is higher than 0.99 when the channel direction is present in the inner direction), so even if the channel mobility of silicon carbide semiconductor device 1 varies somewhat, Is unlikely to decline significantly.

  Therefore, in the silicon carbide semiconductor device 1 of the present invention having a channel direction within a range of ± 10 ° in a direction perpendicular to the <−2110> direction in the surface 12a of the semiconductor layer 12, high channel mobility is realized with good reproducibility. can do. Further, in the silicon carbide semiconductor device 1 of the present invention, in order to realize high channel mobility with good reproducibility, the channel direction is formed in the direction perpendicular to the <−2110> direction in the surface 12a of the semiconductor layer 12. Is most preferable as described above.

  In the above description, the case where the first conductivity type is n-type and the second conductivity type is p-type has been described. However, in the present invention, in the configuration of the silicon carbide semiconductor device 1 described above, the first conductivity-type is used. May be p-type and the second conductivity type may be n-type.

<Embodiment 2>
FIG. 16 is a schematic cross-sectional view of an example of a lateral MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that is an example of the silicon carbide semiconductor device of the present invention.

  A silicon carbide semiconductor device 100 shown in FIG. 16 includes, for example, a substrate 11 made of silicon carbide of n-type and polytype 4H—SiC, and a semiconductor layer 12 made of n-type silicon carbide formed on the surface 11 a of the substrate 11. A second conductivity type impurity diffusion layer 14 which is a p-type region formed in the surface 12a of the semiconductor layer 12, and a surface of the second conductivity type impurity diffusion layer 14 (also in the surface 12a of the semiconductor layer 12). The first conductivity type impurity diffusion layer 15, which is an n-type region, the insulating film 13 formed in contact with the surface 12 a of the semiconductor layer 12, and the insulating film 13 on the surface 12 a of the semiconductor layer 12 are formed. A source electrode 16 and a drain electrode 18 formed in a region other than the region, and a gate electrode 17 formed on the surface of the insulating film 13 on the surface 12a of the semiconductor layer 12 are provided.

  Also here, the surface 11a of the substrate 11 on which the semiconductor layer 12 is formed is a crystal plane inclined within a range of 50 ° to 65 ° with respect to the {0001} plane. Further, the surface 12a of the semiconductor layer 12 is also a crystal plane inclined within a range of 50 ° to 65 ° with respect to the {0001} plane.

  As the insulating film 13, for example, an oxide film formed by dry oxidation (thermal oxidation) or the like can be used. The insulating film 13 is not limited to a one-layer structure, and may have a two-layer structure or more.

  In addition, as the second conductivity type impurity diffusion layer 14, for example, a p type region formed by diffusing a p type impurity as the second conductivity type impurity in the surface 12a of the semiconductor layer 12 can be used. Further, the second conductivity type having a higher concentration than the second conductivity type impurity diffusion layer 14 is formed in at least a part of the region other than the formation region of the first conductivity type impurity diffusion layer 15 in the surface of the second conductivity type impurity diffusion layer 14. A p + -type region containing a p-type impurity as an impurity may be formed.

  In addition, as the first conductivity type impurity diffusion layer 15, for example, an n type region formed by diffusing an n type impurity as the first conductivity type impurity in the surface 12 a of the semiconductor layer 12 can be used. The n-type impurity concentration as the first conductivity type impurity in the first conductivity type impurity diffusion layer 15 can be higher than the n-type impurity concentration as the first conductivity type impurity in the semiconductor layer 12. Here, as the n-type impurity as the first conductivity type impurity, for example, nitrogen, phosphorus or the like can be used.

Also in the silicon carbide semiconductor device 100 shown in FIG. 16, the maximum value of the nitrogen concentration in a region within 10 nm from the interface between the semiconductor layer 12 and the insulating film 13 is 1 × 10 ²¹ cm ⁻³ or more. Also in this case, the region within 10 nm from the interface between the semiconductor layer 12 and the insulating film 13 is a region which is advanced from the interface between the semiconductor layer 12 and the insulating film 13 to the semiconductor layer 12 side by 10 nm perpendicularly to the interface. And a region which is advanced from the interface between the semiconductor layer 12 and the insulating film 13 by 10 nm perpendicular to the interface toward the insulating film 13.

  FIG. 17 is a schematic plan view of silicon carbide semiconductor device 100 shown in FIG. 16 viewed from the gate electrode 17 side. Here, the surface of the source electrode 16, the surface of the gate electrode 17, and the surface of the drain electrode 18 are formed so as to extend in stripes in the <−2110> direction, respectively, and in a direction orthogonal to the <−2110> direction. The source electrode 16, the gate electrode 17, and the drain electrode 18 are arranged in this order.

  One gate electrode 17 is disposed between the source electrode 16 and the drain electrode 18, and a gap between the source electrode 16 and the gate electrode 17 and a gap between the gate electrode 17 and the drain electrode 18 are arranged. The surface of the insulating film 13 is exposed from each.

  Thus, when the surface of the source electrode 16, the surface of the gate electrode 17, and the surface of the drain electrode 18 are striped, as will be described later, it is orthogonal to the <−2110> direction in the surface 12 a of the semiconductor layer 12. The channel direction tends to be easily formed within the range of the direction ± 10 °. In the present invention, the channel direction means a direction in which carriers move in the surface 12 a of the semiconductor layer 12.

  Also in this case, the channel direction of silicon carbide semiconductor device 100 having the above configuration is formed to be included in the range of ± 10 ° in the direction orthogonal to the <−2110> direction in surface 12a of semiconductor layer 12.

  Hereinafter, an example of a method for manufacturing silicon carbide semiconductor device 100 having the above-described configuration will be described. First, as shown in the schematic cross-sectional view of FIG. 3, from silicon carbide (4H—SiC) having a surface 11a composed of a crystal plane inclined within a range of 50 ° to 65 ° with respect to the {0001} plane. A substrate 11 is prepared.

  Here, as shown in the schematic perspective view of FIG. 4, for example, the substrate 11 having the surface 11a is n-type in which the {0001} plane is exposed by crystal growth in the [0001] direction (c-axis direction). The silicon carbide crystal ingot 10 is sliced in a direction where the angle α ° with respect to the {0001} plane is 50 ° or more and 65 ° or less, and the crystal is inclined at an angle of 50 ° or more and 65 ° or less with respect to the {0001} plane. It can be formed by exposing the surface (shaded portion in FIG. 4).

  Further, the surface 11a of the substrate 11 inclined within the range of 50 ° to 65 ° with respect to the {0001} plane is, for example, a {03-38} plane as shown in the schematic cross-sectional view of FIG. On the other hand, the crystal plane is preferably tilted within a range of ± 5 °. When the surface 11a of the substrate 11 is a crystal plane inclined within a range of ± 5 ° with respect to the {03-38} plane, electrical characteristics such as channel mobility of the silicon carbide semiconductor device 100 are improved. There is a tendency. Further, from the viewpoint of further improving electrical characteristics such as channel mobility of silicon carbide semiconductor device 100, a crystal in which surface 11a of substrate 11 is inclined within a range of ± 3 ° with respect to the {03-38} plane. More preferably, the surface 11a of the substrate 11 is the {03-38} plane. A crystal plane inclined within a range of ± 5 ° with respect to the {03-38} plane and a crystal plane inclined within a range of ± 3 ° with respect to the {03-38} plane are each {03 Needless to say, the −38} plane is included.

  Next, as shown in the schematic cross-sectional view of FIG. 6, the semiconductor layer 12 is formed on the surface 11 a of the substrate 11.

Here, the semiconductor layer 12 can be formed by, for example, epitaxially growing the semiconductor layer 12 made of n-type silicon carbide having n-type impurities at a lower concentration than the substrate 11 on the surface 11 a of the substrate 11. it can. When the semiconductor layer 12 is formed by the above-described epitaxial growth, the crystal plane of the surface 11a of the substrate 11 can be inherited by the surface 12a of the semiconductor layer 12, so that the surface 12a of the semiconductor layer 12 is made to the {0001} plane. The crystal plane can be inclined within a range of 50 ° to 65 °.

  For the same reason as described above, the surface 12a of the semiconductor layer 12 is preferably a crystal plane inclined within a range of ± 5 ° with respect to the {03-38} plane, and the {03-38} plane Is more preferably a crystal plane inclined within a range of ± 3 ° with respect to the angle, and most preferably a {03-38} plane. Also here, the crystal plane inclined within the range of ± 5 ° with respect to the {03-38} plane and the crystal plane inclined within the range of ± 3 ° with respect to the {03-38} plane are also included. Needless to say, each includes the {03-38} plane.

  Next, as shown in the schematic plan view of FIG. 7, the direction orthogonal to the <−2110> direction in the surface 12 a of the semiconductor layer 12 is investigated.

  Here, the direction orthogonal to the <−2110> direction in the surface 12 a of the semiconductor layer 12 can be investigated based on, for example, defects included in the semiconductor layer 12. That is, in the manufacturing process of the silicon carbide semiconductor device 100, since defects may be formed at certain locations in the semiconductor layer 12, the position of the defects formed at certain locations in the semiconductor layer 12 is used as a reference. Thus, the direction orthogonal to the <−2110> direction can be specified in the surface 12 a of the semiconductor layer 12. Further, based on the surface morphology of the semiconductor layer 12, the direction orthogonal to the <−2110> direction can be specified in the surface 12 a of the semiconductor layer 12.

  Next, as shown in the schematic cross-sectional view of FIG. 18, the second conductivity type impurity diffusion layer 14 is formed on the entire surface 12 a of the semiconductor layer 12.

  Next, as shown in the schematic cross-sectional view of FIG. 19, the first conductivity type impurity diffusion layer 15 is formed in a part of the surface of the second conductivity type impurity diffusion layer 14 formed as described above. In this example, the first conductivity type impurity diffusion layer 15 is formed in a stripe shape extending in the <−2110> direction, but is not limited to this shape.

  Here, the first conductivity type impurity diffusion layer 15 is formed, for example, after an ion implantation prevention mask is provided in a region other than the formation region of the first conductivity type impurity diffusion layer 15 in the surface 12 a of the semiconductor layer 12. An n-type impurity ion as a type impurity can be formed by ion implantation into the surface 12 a of the semiconductor layer 12. Here, as the ion implantation preventing mask, for example, an oxide film patterned by photolithography and etching can be used.

  Next, activation annealing is performed on the semiconductor layer 12 after the formation of the second conductivity type impurity diffusion layer 14 and the first conductivity type impurity diffusion layer 15 as described above. Thus, the p-type impurity as the second conductivity type impurity in the second conductivity type impurity diffusion layer 14 ion-implanted as described above and the n type impurity as the first conductivity type impurity in the first conductivity type impurity diffusion layer 15 are obtained. Can be activated.

  Here, the activation annealing treatment is performed at a temperature of about 1700 ° C., for example, on the semiconductor layer 12 after the formation of the second conductivity type impurity diffusion layer 14 and the first conductivity type impurity diffusion layer 15 in an argon gas atmosphere. This can be done by heating for about a minute.

  Next, as shown in the schematic cross-sectional view of FIG. 20, the insulating film 13 in contact with the entire surface 12a of the semiconductor layer 12 after the formation of the second conductivity type impurity diffusion layer 14 and the first conductivity type impurity diffusion layer 15 is formed. Form.

  Here, as the insulating film 13, for example, an oxide film formed by dry oxidation (thermal oxidation) or the like can be used. The dry oxidation (thermal oxidation) is performed, for example, in the air on the surface 12a of the semiconductor layer 12 on which the second conductive type impurity diffusion layer 14 and the first conductive type impurity diffusion layer 15 formed as described above are formed. For example, it can be performed by heating at a temperature of about 1200 ° C. for about 30 minutes.

Next, a nitrogen annealing process is performed on the semiconductor layer 12 after the formation of the insulating film 13. Thereby, the nitrogen concentration is adjusted so that the maximum value of the nitrogen concentration in a region within 10 nm from the interface between the semiconductor layer 12 and the insulating film 13 is 1 × 10 ²¹ cm ⁻³ or more.

Here, the above-mentioned nitrogen annealing treatment is performed, for example, by subjecting the semiconductor layer 12 after the formation of the insulating film 13 to 120 ° C. at a temperature of about 1100 ° C. in a gas atmosphere containing nitrogen such as nitrogen monoxide (NO) gas. By performing heating for about a minute, the maximum value of the nitrogen concentration in a region within 10 nm from the interface between the semiconductor layer 12 and the insulating film 13 can be set to 1 × 10 ²¹ cm ⁻³ or more.

  Further, it is preferable that the semiconductor layer 12 after the nitrogen annealing treatment is further subjected to an inert gas annealing treatment in an atmosphere of an inert gas such as argon gas. When the inert gas annealing process is performed on the semiconductor layer 12 after the nitrogen annealing process, the silicon carbide semiconductor device 100 has a tendency to achieve high channel mobility with high reproducibility.

  Here, the above-described inert gas annealing treatment can be performed by heating the semiconductor layer 12 after the above-described nitrogen annealing treatment at a temperature of about 1100 ° C. for about 60 minutes, for example, in an atmosphere of argon gas. .

  Next, as shown in the schematic cross-sectional view of FIG. 21, a part of the insulating film 13 formed as described above is removed, and the insulating film 13 is patterned.

  Here, the patterning of the insulating film 13 is performed in the channel direction within a range of ± 10 ° in the direction orthogonal to the <−2110> direction in the surface 12a of the semiconductor layer 12 as shown in the schematic plan view of FIG. To be included. That is, in the patterning of the insulating film 13, the channel direction is within the range of −10 ° from the direction −20 ° perpendicular to the <−2110> direction in the surface 12 a of the semiconductor layer 12 to + 10 ° from the direction perpendicular to the −2110> direction It is performed so as to be parallel to either direction.

  The insulating film 13 is partially removed by, for example, forming an etching mask patterned on the surface of the insulating film 13 so that the removed portion of the insulating film 13 is exposed by photolithography and etching. 13 can be formed by removing the exposed portion by etching.

  Next, as shown in FIG. 16, the source electrode 16 and the drain electrode 18 are formed so as to contact the surface of the first conductivity type impurity diffusion layer 15 in the surface 12 a of the semiconductor layer 12 exposed from the removed portion of the insulating film 13. To do.

  Here, the source electrode 16 and the drain electrode 18 are made of, for example, a conductive film made of a metal such as nickel on the surface 12a of the semiconductor layer 12 exposed after the etching of the insulating film 13 and the surface of the etching mask. It can be formed by removing the etching mask after forming by sputtering. That is, the conductive film formed on the surface of the etching mask is removed (lifted off) together with the etching mask, and only the conductive film formed on the surface 12 a of the semiconductor layer 12 remains as the source electrode 16 and the drain electrode 18. .

  The semiconductor layer 12 after the formation of the source electrode 16 and the drain electrode 18 is preferably subjected to heat treatment for alloying.

  Here, as the heat treatment for alloying, the semiconductor layer 12 after the formation of the source electrode 16 and the drain electrode 18 is formed at a temperature of, for example, about 950 ° C. in an atmosphere of an inert gas such as argon gas. This can be done by heating for about a minute.

  Next, as shown in FIG. 16, a gate electrode 17 is formed on the surface of the insulating film 13. Here, for example, the gate electrode 17 covers the entire surface of the insulating film 13, the surface of the source electrode 16, and the surface of the drain electrode 18, and is opened in a portion where the gate electrode 17 is formed by photolithography and etching. After forming a resist mask having a portion and forming a conductive film made of a metal such as aluminum on the surface of the resist mask and the surface of the insulating film 13 exposed from the opening of the resist mask by, for example, sputtering. It can be formed by removing the resist mask. That is, the conductive film formed on the surface of the resist mask is removed (lifted off) together with the resist mask, and only the conductive film formed on the surface of the insulating film 13 remains as the gate electrode 17.

  Thus, silicon carbide semiconductor device 100 having the configuration shown in FIG. 16 can be manufactured.

  In silicon carbide semiconductor device 100 having the configuration described above, for example, when a negative voltage is applied to source electrode 16 and a positive voltage is applied to gate electrode 17 and drain electrode 18, carriers injected from source electrode 16 are injected. (Electrons in the above example) are emitted from the surface of the first conductivity type impurity diffusion layer 15 on the source electrode 16 side, the surface of the second conductivity type impurity diffusion layer 14, and the first conductivity type impurity diffusion layer 15 on the drain electrode 18 side. It moves to the drain electrode 18 through the surface.

  Even when a negative voltage is applied to the source electrode 16 and a positive voltage is applied to the drain electrode 18, when a positive voltage is not applied to the gate electrode 17, carriers injected from the source electrode 16 (in the above example) The movement of electrons) in the surface of the second conductivity type impurity diffusion layer 14 can be restricted.

In silicon carbide semiconductor device 100 having the above configuration, for example, on surface 11a of substrate 11 tilted within a range of 50 ° to 65 ° with respect to the {0001} plane of n-type silicon carbide (4H—SiC). In addition, the semiconductor layer 12 made of n-type silicon carbide containing the n-type impurity as the first conductivity type impurity having a lower concentration than the substrate 11 can be formed by epitaxial growth. In such a configuration, the surface 12a of the semiconductor layer 12 (a crystal plane inclined within a range of 50 ° to 65 ° with respect to the {0001} plane) is used for a channel in which carriers move. Therefore, it is possible to obtain higher carrier mobility (channel mobility) compared to the case where the {0001} plane is used for the channel.

Also in silicon carbide semiconductor device 100 having the configuration described above, for example, as shown in FIG. 14, the maximum value of the nitrogen concentration in a region within 10 nm from the interface between semiconductor layer 12 and insulating film 13 is 1 × 10 ^21. cm ⁻³ or more. Therefore, in silicon carbide semiconductor device 100 of the present invention, the interface state generated when insulating film 13 is formed by dry oxidation (thermal oxidation) or the like at the interface between semiconductor layer 12 and insulating film 13 can be reduced. This makes it possible to stabilize carrier mobility (channel mobility) particularly in the channel immediately below the insulating film 13 (the surface 12a portion of the semiconductor layer 12 in contact with the insulating film 13 (the surface portion of the second conductivity type impurity diffusion layer 14)). Can be improved.

  Furthermore, since silicon carbide semiconductor device 100 having the above-described configuration has a channel direction within a range of ± 10 ° in a direction orthogonal to the <−2110> direction in surface 12a of semiconductor layer 12, the channel Since carrier movement in the direction becomes smooth and carrier mobility and current characteristics in the channel direction can be improved, the on-resistance of silicon carbide semiconductor device 100 can be reduced.

  Also in silicon carbide semiconductor device 100 having the configuration described above, for example, as shown in FIG. 15, the angle with respect to the <−2110> direction is 90 ° (<−2110> direction) within surface 12 a of semiconductor layer 12. The channel mobility is highest when the channel direction is in the direction orthogonal to the channel), and the channel mobility decreases as the deviation from the direction orthogonal to the <−2110> direction in the surface 12a of the semiconductor layer 12 increases. There is a tendency to go.

  Therefore, also in silicon carbide semiconductor device 100 having the above-described configuration, the channel direction is a direction orthogonal to the <−2110> direction in surface 12a of semiconductor layer 12 from the viewpoint of realizing high channel mobility. The case (that is, the case of ± 0 ° in the direction orthogonal to the <−2110> direction) is considered most preferable.

  However, also in the silicon carbide semiconductor device 100 having the configuration described above, as shown in FIG. 15, the angle with respect to the <−2110> direction in the surface 12 a of the semiconductor layer 12 is in a direction of 80 ° or more and 90 ° or less (ie, Since the channel mobility (relative value) is higher than 0.99 when the channel direction is present in the direction within the range of ± 10 ° orthogonal to the <−2110> direction, silicon carbide semiconductor device 100 Even if the channel mobility slightly varies, it is unlikely that the channel mobility will greatly decrease.

  Therefore, in the silicon carbide semiconductor device 100 of the present invention having the channel direction within the range of ± 10 ° in the direction orthogonal to the <−2110> direction in the surface 12a of the semiconductor layer 12, high channel mobility is realized with good reproducibility. can do. Further, in the silicon carbide semiconductor device 100 of the present invention, in order to achieve high channel mobility with good reproducibility, the channel direction is formed in the direction perpendicular to the <−2110> direction in the surface 12a of the semiconductor layer 12. Is most preferable as described above.

  In the present embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type has been described. However, in the present invention, in the configuration of silicon carbide semiconductor device 100 described above, The first conductivity type may be p-type and the second conductivity type may be n-type.

  In addition, since the description other than the above in the present embodiment is the same as that in the first embodiment, the description thereof is omitted.

<Example 1>
(Production of vertical DiMOSFET)
A silicon carbide semiconductor device as a vertical DiMOSFET of an example was manufactured as follows.

  First, as shown in FIG. 3, a substrate 11 made of an n-type silicon carbide crystal (4H—SiC) having a thickness of 400 μm was prepared. Here, the substrate 11 has a {03-38} plane, which is a crystal plane inclined at an angle of about 55 ° with respect to the {0001} plane, as the surface 11a.

Next, as shown in FIG. 6, on the surface 11a of the substrate 11, a semiconductor layer 12 made of n-type silicon carbide crystal doped with nitrogen as an n-type impurity (n-type impurity concentration: 5 × 10 ¹⁵ cm ^{−). 3} ) was epitaxially grown to a thickness of 10 μm by a CVD (Chemical Vapor Deposition) method.

  Next, as shown in FIG. 7, the direction orthogonal to the <−2110> direction in the surface 12 a of the semiconductor layer 12 was examined. Here, the direction orthogonal to the <−2110> direction in the surface 12 a of the semiconductor layer 12 was specified based on the defects formed in the semiconductor layer 12.

Next, as shown in FIG. 8, a second conductivity type impurity diffusion layer 14 (p-type impurity concentration: 1 × 10 ¹⁷ cm ⁻³ ) was formed in the surface 12 a of the semiconductor layer 12. Here, the second conductivity type impurity diffusion layer 14 is an oxide film patterned using photolithography and etching in a region other than the formation region of the second conductivity type impurity diffusion layer 14 in the surface 12a of the semiconductor layer 12. Then, using the oxide film as an ion implantation prevention mask, boron, which is a p-type impurity, is implanted by ion implantation. The second conductivity type impurity diffusion layer 14 was formed so that the surface of the second conductivity type impurity diffusion layer 14 had a regular hexagonal shape.

Next, as shown in FIG. 9, the first conductivity type impurity diffusion layer 15 (n-type impurity concentration: 5 × 10 ¹⁹ cm ⁻ is formed in the surface of the second conductivity type impurity diffusion layer 14 formed as described above. ³ ) and a p + type region (not shown) (p type impurity concentration: 3 × 10 ¹⁹ cm ⁻³ ). Here, the first conductivity type impurity diffusion layer 15 is formed so that the surface of the first conductivity type impurity diffusion layer 15 has a regular hexagonal shape, and the p + type region is a channel of the first conductivity type impurity diffusion layer 15. It was formed so as to be in contact with the opposite side to the formation side. The first conductivity type impurity diffusion layer 15 forms an oxide film patterned using photolithography and etching in a region other than the formation region of the first conductivity type impurity diffusion layer 15 in the surface 12a of the semiconductor layer 12. Then, the oxide film was used as an ion implantation preventing mask, and phosphorus, which is an n-type impurity, was ion implanted. The p + -type region also forms an oxide film patterned by photolithography and etching in a region other than the formation region of the p + -type region in the surface 12a of the semiconductor layer 12, and the oxide film is ion-implanted. A p-type impurity boron was ion-implanted as a prevention mask.

  Next, the second conductivity type impurity diffusion layer 14, the first conductivity type impurity diffusion layer 15 and the semiconductor layer 12 formed with the p + type region as described above are heated in an argon gas atmosphere at 1700 ° C. for 30 minutes. Thus, activation annealing treatment was performed.

  Next, as shown in FIG. 10, the surface 12 a of the semiconductor layer 12 is heated in air at 1200 ° C. for 30 minutes and dry-oxidized (thermal oxidation), whereby an insulating film in contact with the entire surface 12 a of the semiconductor layer 12 is formed. 13 was formed.

  Next, nitrogen annealing treatment was performed by heating the semiconductor layer 12 after the formation of the insulating film 13 at 1100 ° C. for 120 minutes in a nitrogen monoxide (NO) gas atmosphere.

  Next, an inert gas annealing process was performed by heating the semiconductor layer 12 after the above-described nitrogen annealing process in an argon gas atmosphere at 1100 ° C. for 60 minutes.

  Next, a part of the insulating film 13 formed as described above is removed so that the channel direction becomes a direction orthogonal to the <−2110> direction in the surface 12 a of the semiconductor layer 12. Ning. Here, the patterning of the insulating film 13 is performed by forming an etching mask patterned on the surface of the insulating film 13 so as to expose the removed portion of the insulating film 13 by photolithography and etching, and then exposing the insulating film 13. This was done by removing the portion by etching.

  Next, nickel having a regular hexagonal surface as shown in FIG. 13 is formed on the surface of the first conductivity type impurity diffusion layer 15 and the p + type region (not shown) exposed from the removed portion of the insulating film 13. A source electrode 16 having a thickness of 0.1 μm was formed.

  Next, heat treatment for alloying was performed by heating the semiconductor layer 12 after the formation of the source electrode 16 at 950 ° C. for 2 minutes in an argon gas atmosphere.

  Next, a 1 μm-thick gate electrode 17 made of aluminum having a surface shape as shown in FIG. 13 was formed on the surface of the insulating film 13.

  Next, a drain electrode 18 made of nickel and having a thickness of 0.1 μm was formed on the entire back surface of the substrate 11.

  Thus, silicon carbide semiconductor device 1 as a vertical DiMOSFET of the example was manufactured.

  The channel length of the silicon carbide semiconductor device 1 as the vertical DiMOSFET of the embodiment manufactured as described above (the first conductivity type impurity diffusion layer 15 between the adjacent source electrodes 16 in the surface 12a of the semiconductor layer 12 and the semiconductor). The distance between the layers 12) was 2 μm.

  For comparison, a silicon carbide semiconductor device as a vertical DiMOSFET of a comparative example was fabricated in the same manner as described above except that the channel direction was the <−2110> direction in the surface 12a of the semiconductor layer 12.

(Vertical DiMOSFET evaluation)
With respect to the vertical DiMOSFETs of Examples and Comparative Examples manufactured as described above, the distribution in the depth direction of the nitrogen concentration in the vicinity of the interface between the semiconductor layer 12 and the insulating film 13 is measured by SIMS (secondary ion mass spectrometry). did.

As a result, in each of the vertical DiMOSFETs of the example and the comparative example, the maximum nitrogen concentration in the vicinity of the interface between the semiconductor layer 12 and the insulating film 13 was 1 × 10 ²¹ cm ⁻³ or more, respectively. Therefore, it is confirmed that the maximum value of the nitrogen concentration in the region within 10 nm from the interface between the semiconductor layer 12 and the insulating film 13 is 1 × 10 ²¹ cm ⁻³ or more for each of the vertical DiMOSFETs of the example and the comparative example. It was done.

  Further, the channel mobility was evaluated for the vertical DiMOSFETs of the example and the comparative example. The following method was used as the channel mobility evaluation method. First, with the source-drain voltage VDS = 0.1 V, the gate voltage VG was applied to measure the source-drain current IDS (the gate voltage dependency was measured). Then, as gm = (δIDS) / (δVG), the maximum value of the channel mobility with respect to the gate voltage was obtained by the following equation (1), and the maximum value was calculated as the channel mobility.

Channel mobility μ = gm × (L × d) / (W × ε × VDS) (1)
In the above equation (1), L represents the channel length, d represents the thickness of the insulating film 13, W represents the channel width, and ε represents the dielectric constant of the insulating film 13.

As a result, the channel mobility of the vertical DiMOSFET of the example was 80 cm ² / Vs, and the channel mobility of the vertical DiMOSFET of the comparative example was 70 cm ² / Vs.

  Therefore, the channel mobility of the vertical DiMOSFET of the example is about 1.14 times the channel mobility of the vertical DiMOSFET of the comparative example, and accordingly, the source-drain current value is 1.14 times. It was confirmed that the on-resistance was greatly reduced.

  Therefore, according to the configuration of the vertical DiMOSFET of the embodiment, even if the channel mobility varies somewhat due to a manufacturing problem, it is not considered that the channel mobility is greatly reduced. It can be realized.

<Example 2>
(Production of lateral MOSFET)
A silicon carbide semiconductor device as a lateral MOSFET of the example was manufactured as follows.

  First, as shown in FIG. 3, a substrate 11 made of an n-type silicon carbide crystal (4H—SiC) having a thickness of 400 μm was prepared. Here, the substrate 11 has a {03-38} plane, which is a crystal plane inclined at an angle of about 55 ° with respect to the {0001} plane, as the surface 11a.

Next, as shown in FIG. 6, on the surface 11a of the substrate 11, a semiconductor layer 12 made of n-type silicon carbide crystal doped with nitrogen as an n-type impurity (n-type impurity concentration: 5 × 10 ¹⁵ cm ^{−). 3} ) was epitaxially grown to a thickness of 10 μm by a CVD (Chemical Vapor Deposition) method.

  Next, as shown in FIG. 7, the direction orthogonal to the <−2110> direction in the surface 12 a of the semiconductor layer 12 was examined. Here, the direction orthogonal to the <−2110> direction in the surface 12 a of the semiconductor layer 12 was specified based on the surface morphology of the semiconductor layer 12.

Next, as shown in FIG. 18, the second conductivity type impurity diffusion layer 14 (p-type impurity concentration: 1 × 10 ¹⁷ cm ⁻³ ) was formed on the entire surface 12 a of the semiconductor layer 12.

Next, as shown in FIG. 19, a first conductivity type impurity diffusion layer 15 (n-type impurity concentration: 5 × 10 5 is formed on a part of the surface of the second conductivity type impurity diffusion layer 14 formed as described above. ¹⁹ cm ⁻³ ) and p + -type region (not shown) (p-type impurity concentration: 3 × 10 ¹⁹ cm ⁻³ ) were formed. Here, the first conductivity type impurity diffusion layer 15 is formed so that the surface of the first conductivity type impurity diffusion layer 15 has a stripe shape, and the p + type region is the channel of the first conductivity type impurity diffusion layer 15. A stripe was formed in contact with the side opposite to the formation side. The first conductivity type impurity diffusion layer 15 forms an oxide film patterned using photolithography and etching in a region other than the formation region of the first conductivity type impurity diffusion layer 15 in the surface 12a of the semiconductor layer 12. Then, the oxide film was used as an ion implantation preventing mask, and phosphorus, which is an n-type impurity, was ion implanted. The p + -type region also forms an oxide film patterned by photolithography and etching in a region other than the formation region of the p + -type region in the surface 12a of the semiconductor layer 12, and the oxide film is ion-implanted. A p-type impurity boron was ion-implanted as a prevention mask.

  Next, the second conductivity type impurity diffusion layer 14, the first conductivity type impurity diffusion layer 15 and the semiconductor layer 12 formed with the p + type region as described above are heated in an argon gas atmosphere at 1700 ° C. for 30 minutes. Thus, activation annealing treatment was performed.

  Next, as shown in FIG. 20, the surface 12a of the semiconductor layer 12 is heated in air at 1200 ° C. for 30 minutes for dry oxidation (thermal oxidation), whereby an insulating film in contact with the entire surface 12a of the semiconductor layer 12 is formed. 13 was formed.

  Next, nitrogen annealing treatment was performed by heating the semiconductor layer 12 after the formation of the insulating film 13 at 1100 ° C. for 120 minutes in a nitrogen monoxide (NO) gas atmosphere.

  Next, an inert gas annealing process was performed by heating the semiconductor layer 12 after the above-described nitrogen annealing process in an argon gas atmosphere at 1100 ° C. for 60 minutes.

  Next, a part of the insulating film 13 formed as described above is removed so that the channel direction becomes a direction orthogonal to the <−2110> direction in the surface 12 a of the semiconductor layer 12. Ning. Here, the patterning of the insulating film 13 is performed by forming an etching mask patterned on the surface of the insulating film 13 so as to expose the removed portion of the insulating film 13 by photolithography and etching, and then exposing the insulating film 13. This was done by removing the portion by etching.

  Next, the first conductive impurity diffusion layer 15 exposed from the removed portion of the insulating film 13 and the surface of the p + type region (not shown) are made of nickel having a striped surface as shown in FIG. A source electrode 16 and a drain electrode 18 each having a thickness of 0.1 μm were formed.

  Next, heat treatment for alloying was performed by heating the semiconductor layer 12 after the formation of the source electrode 16 at 950 ° C. for 2 minutes in an argon gas atmosphere.

  Next, a 1 μm-thick gate electrode 17 made of aluminum having a striped surface as shown in FIG. 17 was formed on the surface of the insulating film 13.

  Thus, silicon carbide semiconductor device 100 as a lateral MOSFET of the example having the configuration shown in FIG. 16 was produced.

  The channel length (distance between the source electrode 16 and the drain electrode 18 adjacent in the surface 12a of the semiconductor layer 12) of the silicon carbide semiconductor device 100 as the lateral MOSFET of the embodiment manufactured as described above is 2 μm. It was.

  For comparison, a silicon carbide semiconductor device as a lateral MOSFET of a comparative example was fabricated in the same manner as described above except that the channel direction was the <−2110> direction in the surface 12a of the semiconductor layer 12.

(Evaluation of lateral MOSFET)
For the lateral MOSFETs of Examples and Comparative Examples manufactured as described above, the nitrogen concentration distribution in the vicinity of the interface between the semiconductor layer 12 and the insulating film 13 was measured by SIMS (secondary ion mass spectrometry). .

As a result, in each of the lateral MOSFETs of the example and the comparative example, the maximum nitrogen concentration in the vicinity of the interface between the semiconductor layer 12 and the insulating film 13 was 1 × 10 ²¹ cm ⁻³ or more, respectively. Therefore, it is confirmed that the maximum value of the nitrogen concentration in the region within 10 nm from the interface between the semiconductor layer 12 and the insulating film 13 is 1 × 10 ²¹ cm ⁻³ or more for the lateral MOSFETs of the example and the comparative example. It was.

  Further, channel mobility was evaluated for the lateral MOSFETs of the example and the comparative example. The following method was used as the channel mobility evaluation method. First, with the source-drain voltage VDS = 0.1 V, the gate voltage VG was applied to measure the source-drain current IDS (the gate voltage dependency was measured). Then, as gm = (δIDS) / (δVG), the maximum value of the channel mobility with respect to the gate voltage was obtained by the following equation (1), and the maximum value was calculated as the channel mobility.

Channel mobility μ = gm × (L × d) / (W × ε × VDS) (1)
In the above equation (1), L represents the channel length, d represents the thickness of the insulating film 13, W represents the channel width, and ε represents the dielectric constant of the insulating film 13.

As a result, the channel mobility of the lateral MOSFET of the example was 80 cm ² / Vs, and the channel mobility of the lateral MOSFET of the comparative example was 70 cm ² / Vs.

  Therefore, the channel mobility of the lateral MOSFET of the example is about 1.14 times the channel mobility of the lateral MOSFET of the comparative example, and accordingly, the current value between the source and the drain is 1.14 times. Was confirmed to be significantly reduced.

  Therefore, according to the configuration of the lateral MOSFET of the embodiment, even if the channel mobility varies somewhat due to a manufacturing problem, it is not considered that the channel mobility is greatly reduced, so high channel mobility is realized with high reproducibility. I think it can be done.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  According to the present invention, a silicon carbide semiconductor device capable of realizing high channel mobility with high reproducibility and a method for manufacturing the same can be provided. Therefore, the present invention provides, for example, a vertical DiMOSFET and a lateral MOSFET using SiC. There is a possibility that it can be suitably used for, for example.

It is typical sectional drawing of an example of vertical DiMOSFET which is an example of the silicon carbide semiconductor device of this invention. It is the typical top view which looked at the silicon carbide semiconductor device shown in FIG. 1 from the gate electrode side. It is typical sectional drawing illustrating a part of manufacturing process of an example of the manufacturing method of the silicon carbide semiconductor device of this invention. It is a typical perspective view illustrating a part of manufacturing process of an example of the manufacturing method of the silicon carbide semiconductor device of this invention. It is typical sectional drawing of an example of the board | substrate used for this invention. It is typical sectional drawing illustrating a part of manufacturing process of an example of the manufacturing method of the silicon carbide semiconductor device of this invention. It is a typical top view of an example of the surface of the semiconductor layer used for this invention. It is typical sectional drawing illustrating a part of manufacturing process of an example of the manufacturing method of the silicon carbide semiconductor device of this invention. It is typical sectional drawing illustrating a part of manufacturing process of an example of the manufacturing method of the silicon carbide semiconductor device of this invention. It is typical sectional drawing illustrating a part of manufacturing process of an example of the manufacturing method of the silicon carbide semiconductor device of this invention. It is typical sectional drawing illustrating a part of manufacturing process of an example of the manufacturing method of the silicon carbide semiconductor device of this invention. It is a typical top view illustrating a part of manufacturing process of an example of the manufacturing method of the silicon carbide semiconductor device of this invention. It is the typical top view which looked at another example of the silicon carbide semiconductor device of this invention from the gate electrode side. It is a figure which shows an example of distribution of the nitrogen concentration in the interface vicinity of the insulating film and semiconductor layer in an example of the silicon carbide semiconductor device of this invention. It is a figure which shows an example of the relationship between the angle (degree) with respect to the <-2110> direction in the surface of the semiconductor layer in an example of the silicon carbide semiconductor device of this invention, and channel mobility (relative value). It is typical sectional drawing of an example of lateral MOSFET which is an example of the silicon carbide semiconductor device of this invention. FIG. 17 is a schematic plan view of the silicon carbide semiconductor device shown in FIG. 16 viewed from the gate electrode side. It is typical sectional drawing illustrating a part of manufacturing process of an example of the manufacturing method of the silicon carbide semiconductor device of this invention. It is typical sectional drawing illustrating a part of manufacturing process of an example of the manufacturing method of the silicon carbide semiconductor device of this invention. It is typical sectional drawing illustrating a part of manufacturing process of an example of the manufacturing method of the silicon carbide semiconductor device of this invention. It is typical sectional drawing illustrating a part of manufacturing process of an example of the manufacturing method of the silicon carbide semiconductor device of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,100 Silicon carbide semiconductor device, 10 Silicon carbide crystal ingot, 11 Substrate, 11a surface, 12 Semiconductor layer, 12a surface, 13 Insulating film, 14 2nd conductivity type impurity diffusion layer, 15 1st conductivity type impurity diffusion layer, 16 Source electrode, 17 gate electrode, 18 drain electrode.

Claims (10)

A semiconductor layer made of silicon carbide having a surface inclined within a range of 50 ° to 65 ° with respect to the {0001} plane;
An insulating film formed in contact with the surface of the semiconductor layer,
A maximum value of nitrogen concentration in a region within 10 nm from the interface between the surface of the semiconductor layer and the insulating film is 1 × 10 ²¹ cm ⁻³ or more;
A silicon carbide semiconductor device having a channel length direction within a range of ± 10 ° in a direction perpendicular to the <−2110> direction in the surface of the semiconductor layer. A substrate made of silicon carbide of the first conductivity type;
A first conductivity type formed on the substrate, including a first conductivity type impurity having a lower concentration than the substrate, and having a surface inclined within a range of 50 ° to 65 ° with respect to the {0001} plane. A semiconductor layer made of silicon carbide;
A second conductivity type impurity diffusion layer formed in the surface of the semiconductor layer;
A first conductivity type impurity diffusion layer formed in a surface of the second conductivity type impurity diffusion layer;
An insulating film formed in contact with the surface of the semiconductor layer;
A source electrode formed so as to be in contact with at least a part of a region other than a portion where the insulating film is formed on the surface of the semiconductor layer;
A gate electrode formed on the insulating film;
A drain electrode formed on the surface of the substrate opposite to the side on which the semiconductor layer is formed,
The maximum value of the nitrogen concentration in a region within 10 nm from the interface between the surface of the semiconductor layer and the insulating film is 1 × 10 ²¹ cm ⁻³ or more;
A silicon carbide semiconductor device having a channel length direction within a range of ± 10 ° in a direction perpendicular to the <−2110> direction in the surface of the semiconductor layer. A substrate made of silicon carbide of the first conductivity type;
A first conductivity type formed on the substrate, including a first conductivity type impurity having a lower concentration than the substrate, and having a surface inclined within a range of 50 ° to 65 ° with respect to the {0001} plane. A semiconductor layer made of silicon carbide;
A second conductivity type impurity diffusion layer formed in the surface of the semiconductor layer;
A first conductivity type impurity diffusion layer formed in a surface of the second conductivity type impurity diffusion layer;
An insulating film formed in contact with the surface of the semiconductor layer;
A source electrode formed so as to be in contact with a part of a region other than a portion where the insulating film is formed on the surface of the semiconductor layer;
A drain electrode formed so as to be in contact with another part of the region other than a portion where the insulating film is formed on the surface of the semiconductor layer;
A gate electrode formed on the insulating film,
The maximum value of the nitrogen concentration in a region within 10 nm from the interface between the surface of the semiconductor layer and the insulating film is 1 × 10 ²¹ cm ⁻³ or more;
A silicon carbide semiconductor device having a channel length direction within a range of ± 10 ° in a direction perpendicular to the <−2110> direction in the surface of the semiconductor layer.   The silicon carbide semiconductor device according to claim 2, wherein a surface of the source electrode is striped.   The silicon carbide semiconductor device according to claim 2, wherein a surface of the source electrode has a honeycomb shape.   6. The silicon carbide according to claim 1, wherein the surface of the semiconductor layer is a crystal plane inclined within a range of ± 5 ° with respect to a {03-38} plane. Semiconductor device. Forming a semiconductor layer having a surface inclined within a range of 50 ° to 65 ° with respect to the {0001} plane;
Investigating a direction orthogonal to the <-2110> direction in the surface of the semiconductor layer;
An insulating film in contact with a part of the surface of the semiconductor layer is formed so that a channel length direction is formed within a range of ± 10 ° in a direction perpendicular to the <−2110> direction in the surface of the semiconductor layer. Process,
Adjusting the nitrogen concentration so that the maximum value of the nitrogen concentration in a region within 10 nm from the interface between the surface of the semiconductor layer and the insulating film is 1 × 10 ²¹ cm ⁻³ or more. Device manufacturing method.   The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein a direction orthogonal to a <−2110> direction in the surface of the semiconductor layer is investigated based on an orientation of a defect included in the semiconductor layer. Method.   The carbonization according to claim 7 or 8, wherein the step of adjusting the nitrogen concentration includes a step of heat-treating the semiconductor layer on which the insulating film is formed in an atmosphere of a gas containing nitrogen. A method for manufacturing a silicon semiconductor device.   10. The method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein the step of adjusting the nitrogen concentration includes a step of heat-treating the semiconductor layer after the heat treatment in an atmosphere of an inert gas.

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