JP2016004955A - Silicon carbide semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device and a manufacturing method of the same, which support reduction in channel resistance and reduction in JFET resistance at the same time.SOLUTION: A silicon carbide semiconductor device of the present invention comprises: a first conductivity type silicon carbide substrate; a first conductivity type drift layer on a principal surface of the silicon carbide substrate; and second conductivity type well regions which are provided at a distance from each other in a surface layer of the drift layer. The well region has a retrograde profile where a second conductivity type impurity concentration decreases in a range of up to 400 nm in a depth direction, from 1×10cmto a concentration equivalent with a first conductivity type impurity concentration in the drift layer.

Description

  The present invention relates to an ion implantation method for improving channeling and reducing channel resistance.

  Conventionally, in order to suppress channeling in ion implantation in the formation of a semiconductor device, a method of performing ion implantation from a predetermined angle with respect to the normal direction of the sidewall of the implantation mask (for example, Patent Document 1), with respect to the normal direction of the substrate An inclined rotation implantation method (for example, Patent Document 2) in which ions are implanted while rotating around a normal line while maintaining a predetermined inclination angle (implantation angle), and a parallel scanning method with a predetermined implantation angle ( For example, Patent Document 3) is adopted.

JP-A-10-256173 JP-A-5-41387 JP-A-5-166745

  However, since all of the ion implantation methods of Patent Documents 1-3 perform oblique ion implantation in the normal direction of the sidewall of the implantation mask, some ions pass through the end of the implantation mask in the oblique direction. The incident range shortens the range. Therefore, there is a problem that a region having a high impurity concentration is locally formed in the surface portion of the SiC substrate under the end portion of the implantation mask, and the channel resistance of the MOSFET is increased.

  In view of the above-described problems, an object of the present invention is to provide a silicon carbide semiconductor device that achieves both a reduction in channel resistance and a reduction in JFET resistance, and a method for manufacturing the same.

A silicon carbide semiconductor device according to the present invention is provided on a first conductivity type silicon carbide substrate, a first conductivity type drift layer on a main surface of the silicon carbide substrate, and a surface layer of the drift layer so as to be separated from each other. A well region of a second conductivity type, and the well region has a first conductivity type impurity in the drift layer from 1 × 10 ¹⁸ cm ^{−3 in} a range where the second conductivity type impurity concentration is 400 nm or less in the depth direction. It has a retrograde profile that decreases to a concentration equal to the concentration.

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention, the first conductivity type drift layer is formed on the main surface of the first conductivity type silicon carbide substrate, and provided on the surface layer of the drift layer so as to be separated from each other. A second conductivity type well region is formed. The well region is formed by forming a rectangular implantation mask on the drift layer and performing ion implantation in a direction parallel to the longitudinal side wall of the implantation mask and from an oblique direction with respect to the implantation surface of the drift layer. The

A silicon carbide semiconductor device according to the present invention is provided on a first conductivity type silicon carbide substrate, a first conductivity type drift layer on a main surface of the silicon carbide substrate, and a surface layer of the drift layer so as to be separated from each other. A well region of a second conductivity type, and the well region has a first conductivity type impurity in the drift layer from 1 × 10 ¹⁸ cm ^{−3 in} a range where the second conductivity type impurity concentration is 400 nm or less in the depth direction. It has a retrograde profile that decreases to a concentration equal to the concentration. By setting the impurity concentration profile of the well region to the above-mentioned retrograde, it is possible to achieve both a reduction in channel resistance and a reduction in JFET resistance.

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention, the first conductivity type drift layer is formed on the main surface of the first conductivity type silicon carbide substrate, and provided on the surface layer of the drift layer so as to be separated from each other. A second conductivity type well region is formed. The well region is formed by forming a rectangular implantation mask on the drift layer and performing ion implantation in a direction parallel to the longitudinal side wall of the implantation mask and from an oblique direction with respect to the implantation surface of the drift layer. The Thereby, a silicon carbide semiconductor device having low channel resistance and low JFET resistance can be manufactured.

FIG. 3 is a cross-sectional view of the MOSFET according to the first embodiment. 3 is a plan view of a silicon carbide substrate showing an arrangement of an implantation mask and well regions according to the first embodiment. FIG. It is aa 'sectional drawing of FIG. It is bb 'sectional drawing of FIG. It is a figure which shows the relationship between the injection | pouring angle in a 4 degree | times off board | substrate, and the pulling condition of the bottom of a concentration profile. It is a figure which shows the relationship between the implantation angle in an 8 degree | times off board | substrate, and the pulling condition of the bottom of a concentration profile. It is a figure which shows the density | concentration profile of a well area | region. It is a figure which shows the current-voltage characteristic of the ON state of MOSFET. It is a figure which shows the on-resistance of MOSFET. FIG. 6 is a plan view of a silicon carbide substrate showing an arrangement of an implantation mask and well regions according to a modification of the first embodiment.

<A. Embodiment 1>
<A-1. Channeling>
In the fabrication of a MOSFET using a silicon carbide (SiC) substrate, impurities are doped by ion implantation. Since SiC has a much smaller thermal diffusion coefficient of impurities than Si, an impurity concentration profile cannot be determined by thermal diffusion of impurities as in the case of a Si substrate. Therefore, in the SiC substrate, the peak value of the impurity concentration and the implantation depth in the impurity region are controlled by the ion implantation conditions.

In the well region of the MOSFET formed by ion implantation, it is necessary to reduce the impurity concentration on the surface side in order to reduce the channel resistance. On the other hand, the impurity concentration is set to 1 × 10 in order to suppress punch-through except on the surface side. ^It is necessary to be ¹⁸ cm ⁻³ or more. In addition, the drift layer concentration of the MOSFET having a withstand voltage of several kV is 1 × 10 ¹⁵ cm ⁻³ or more, and in order to reduce the JFET resistance, the implantation depth at which the impurity concentration is equal to the drift layer needs to be shallow. . In summary, the impurity concentration profile in the well region is the smallest on the surface side, has a peak at a certain depth, and requires a retrograde that decreases sharply.

  In ion implantation, there is a phenomenon called channeling in which implanted impurities reach deep into the substrate through the gaps between atoms. In the Si substrate, ion implantation is performed by tilting the substrate by 7 to 8 ° in order to suppress channeling. On the other hand, in the case of a SiC substrate, since the substrate used for device fabrication is provided with an off angle of 4 to 8 °, it is considered that channeling does not occur, and oblique ion implantation from the viewpoint of suppressing channeling is performed. It was not done.

  However, the applicant has found that, in the SiC substrate, secondary channeling occurs due to the random component of the ions that collide with the crystal lattice and are scattered, resulting in the bottom of the concentration profile, resulting in the formation of a deep JFET region and the JFET resistance. We found that an increase occurred. Therefore, when forming a well region in a SiC substrate, in order to avoid a secondary channeling and to form a retrograde steep concentration profile, as in the case of a Si substrate, the substrate is inclined from an oblique direction. It is necessary to perform ion implantation.

  In order to solve the above-described problem, when the implantation is performed obliquely with respect to the implantation surface in the direction perpendicular to the side wall of the mask during ion implantation, the ions are locally introduced by passing through the edge of the mask in the oblique direction. Since a high concentration region is formed, channel resistance increases.

  Therefore, in the silicon carbide semiconductor device according to the present invention, the well region is formed by performing ion implantation from an oblique direction with respect to the implantation surface in a direction parallel to the sidewall of the implantation mask. The concentration profile of the p-well region manufactured by this method has a feature that it decreases sharply compared to the conventional case because the secondary channeling described above is suppressed.

<A-2. Configuration>
FIG. 1 is a schematic cross-sectional view of a vertical MOSFET 100 that is a silicon carbide semiconductor device according to the first embodiment of the present invention. Hereinafter, in this specification, regarding the conductivity type of the semiconductor layer, the first conductivity type is n-type and the second conductivity type is p-type, but the opposite conductivity type may be used.

  The vertical MOSFET 100 includes an SiC substrate 10, a drift layer 20, a well region 30, a source region 40, a gate insulating film 50, an interlayer insulating film 55, a gate electrode 60, a source ohmic electrode 70, a back ohmic electrode 71, a source electrode 80, and a drain. An electrode 85 is provided.

  SiC substrate 10 is made of silicon carbide having a first conductivity type and low resistance, and has a 4H polytype. The plane orientation of the first main surface is inclined 4 ° in the c-axis direction from the (0001) plane. Drift layer 20 made of silicon carbide of the first conductivity type is formed on the first main surface of SiC substrate 10.

  On the surface layer side of the drift layer 20, a plurality of well regions 30, which are semiconductor layers of the second conductivity type, are formed apart from each other in plan view. The well region 30 is a second conductivity type semiconductor layer containing aluminum (Al) as an impurity. Of the surface layer of the drift layer 20, a region between adjacent well regions 30 and a region from the surface of the drift layer 20 to the same depth as the depth of the well region 30 is defined as a separation region 21.

  On the surface layer of the well region 30, a source region 40, which is a first conductivity type semiconductor layer containing nitrogen (N) as an impurity, is formed. Further, a second conductivity type well contact region 35 penetrating from the surface layer to the bottom surface is partially formed in the source region 40. The second conductivity type impurity in the well contact region is aluminum (Al).

  A gate insulating film 50 made of silicon oxide is formed across the surface of the well region 30 and a part of the surface of the source region 40. Further, a gate electrode 60 is formed on the surface of the gate insulating film 50 so as to face the end portions of the well region 30 and the source region 40 with the gate insulating film 50 interposed therebetween. In the well region 30, a region facing the gate electrode 60 through the gate insulating film 50 and in which an inversion layer is formed during the on operation is referred to as a channel region.

  An interlayer insulating film 55 made of silicon oxide is formed on the gate insulating film 50 so as to cover the gate electrode 60. In order to reduce contact resistance with silicon carbide, the surface of the region of the source region 40 that is not covered with the gate insulating film 50 and the partial surface of the well contact region 35 on the side in contact with the source region 40 Source ohmic electrode 70 is formed. The well region 30 can easily exchange electrons with the source ohmic electrode 70 via the low-resistance well contact region 35.

  A source electrode 80 is formed on the source ohmic electrode 70 and the interlayer insulating film 55. On the second main surface opposite to the first main surface of SiC substrate 10, that is, on the back surface side, drain electrode 85 is formed via back surface ohmic electrode 71. Although not shown, the gate electrode 60 is electrically short-circuited with the gate pad and the gate wiring through the gate contact hole opened in the interlayer insulating film 55 in a part of the region where the unit cell does not exist in the semiconductor device. ing.

<A-3. Manufacturing process>
A method for manufacturing MOSFET 100 will be described. First, an SiC substrate 10 having a 4H polytype is prepared, and chemical vapor deposition (Chemical Vapor deposition) is performed on the first main surface inclined by an off angle in the [11-20] direction from the (0001) plane of the SiC substrate 10. A drift layer 20 made of silicon carbide having a thickness of 5 to 50 μm is epitaxially grown by a deposition (CVD) method. The first conductivity type impurity concentration of the drift layer 20 is 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ .

  Next, an implantation mask 31 is formed on the surface of the drift layer 20 with a photoresist or the like, and Al is ion-implanted as a second conductivity type impurity. This ion implantation region becomes the well region 30. Here, as shown in FIG. 2, when the SiC substrate 10 is viewed from above, the implantation mask 31 and the well region 30 are formed in a stripe shape that repeats in parallel and alternately. The stripe direction is set to be parallel to the off-angle direction of the SiC substrate 10.

  FIG. 3 is a cross-sectional view taken along the line aa ′ of FIG. 2 and is a cross-sectional view seen from a direction perpendicular to the sidewall of the implantation mask 31. FIG. 4 is a cross-sectional view taken along the line bb ′ of FIG. 2 and shows a cross-sectional view seen from a direction parallel to the sidewall of the implantation mask. The Al ion implantation direction is perpendicular to the implantation surface when viewed from a direction perpendicular to the sidewall of the implantation mask 31 as shown in FIG. 3, and on the sidewall of the implantation mask 31 as shown in FIG. When viewed from a direction parallel to the surface, the direction is oblique to the injection surface.

Also, the Al ion implantation depth is about 0.5 to 3 μm which does not exceed the thickness of the drift layer 20. As described above, the impurity concentration of the well region 30, from 1 × ¹⁰ 18 ^{cm -3} required for punch-through suppression, 1 × ¹⁰ 16 equal to the first conductivity type impurity concentration of the drift layer 20 cm ^- It is necessary to decrease sharply in the depth direction up to ³ . In this respect, by performing ion implantation from an oblique direction with respect to the implantation surface of the SiC substrate 10 as described above, the impurity concentration is in the range of 400 nm or less from 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁶ cm ^−3. An impurity concentration profile that decreases sharply is obtained. Therefore, the JFET length is shortened, and the JFET length can be reduced. Also, when viewed from a direction perpendicular to the side wall of the implantation mask 31, ion implantation is performed perpendicular to the implantation surface, so that implanted ions do not pass through the end portion of the implantation mask 31 in an oblique direction and enter. Therefore, it is possible to avoid locally increasing the impurity concentration on the surface of the well region 30 below the end of the implantation mask 31, and to avoid an increase in the channel resistance of the MOSFET. Thereafter, the implantation mask 31 is removed. The region into which Al is ion-implanted by this step becomes the well region 30.

Next, an implantation mask is formed on the surface of the drift layer 20 with a photoresist or the like, and Al, which is a p-type impurity, is ion implanted adjacent to the outer periphery of the well region 30. At this time, the depth of Al ion implantation is about 0.5 to 3 μm which does not exceed the thickness of the drift layer 20. The impurity concentration of the ion-implanted Al is higher than the first conductivity type impurity concentration of the drift layer 20 in the range of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ and the Al concentration of the well region 30. Make it lower. Thereafter, the implantation mask is removed. A region into which Al is ion-implanted by this step becomes a JTE region (not shown).

Next, an implantation mask is formed on the surface of the drift layer 20 using a photoresist or the like, and N which is an n-type impurity is ion-implanted. The N ion implantation depth is shallower than the thickness of the well region 30. Also, the impurity concentration of the ion-implanted N exceeds the second conductivity type impurity concentration of the well region 30 in the range of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . Of the regions into which N has been implanted in this step, the region showing the first conductivity type becomes the source region 40.

  Next, an implantation mask is formed on the surface of the drift layer 20 using a photoresist or the like, and Al, which is a second conductivity type impurity, is ion-implanted in the center of the source region 40 to remove the implantation mask. The region into which Al is implanted by this step becomes the well contact region 35. The well contact region 35 is provided in order to obtain good electrical contact between the well region 30 and the source ohmic electrode 70. The second conductivity type impurity concentration of the well contact region 35 is the second conductivity type of the well region 30. It is desirable to set the concentration higher than the impurity concentration. When ion-implanting p-type impurities in this step, it is desirable to heat the SiC substrate 10 or the drift layer 20 to 150 ° C. or higher for the purpose of reducing the resistance of the well contact region 35.

  Next, annealing is performed at 1300 to 1900 ° C. for 30 seconds to 1 hour in an inert gas atmosphere such as argon (Ar) gas by a heat treatment apparatus. By this annealing, ion-implanted N and Al are electrically activated.

  Subsequently, a field insulating film made of a silicon dioxide film having a thickness of about 0.5 to 2 μm is formed in a region other than the position substantially corresponding to the above-described active region by using a CVD method, a photolithography technique, or the like. At this time, for example, after the field insulating film is formed on the entire surface, the field insulating film at a position substantially corresponding to the cell region may be removed by photolithography, etching, or the like.

  Subsequently, the silicon carbide surface not covered with the field insulating film is thermally oxidized to form silicon oxide as the gate insulating film 50 having a desired thickness. Next, a polycrystalline silicon film having conductivity is formed on the gate insulating film 50 by a low pressure CVD method, and the gate electrode 60 is formed by patterning this. Subsequently, an interlayer insulating film 55 is formed by a low pressure CVD method. Subsequently, contact holes reaching the well contact region 35 and the source region 40 of the unit cell through the interlayer insulating film 55 and the gate insulating film 50 are formed, and at the same time, well contact holes (see FIG. (Not shown).

  Next, after forming a metal film containing Ni as a main component by sputtering or the like, heat treatment is performed at a temperature of 600 to 1100 ° C. to form a metal film containing Ni as a main component and a silicon carbide layer in the contact hole. By reacting, silicide is formed between the silicon carbide layer and the metal film. Subsequently, the metal film remaining on the interlayer insulating film 55 is removed by wet etching using sulfuric acid, nitric acid, hydrochloric acid, or a mixed solution of these with hydrogen peroxide. Thereby, the source ohmic electrode 70 is formed.

  Subsequently, a back surface ohmic electrode 71 is formed on the second main surface by forming a metal mainly composed of Ni on the back surface (second main surface) of the SiC substrate 10 and performing heat treatment.

  Next, the interlayer insulating film 55 at a position that becomes a gate contact hole (not shown) is removed by patterning using a photoresist or the like.

  Thereafter, a wiring metal such as Al is formed on the surface of the SiC substrate 10 by sputtering or vapor deposition, and the source electrode 80 is formed by processing it into a predetermined shape by photolithography. Furthermore, a drain electrode 85, which is a metal film, is formed on the surface of the back ohmic electrode 71 formed on the second main surface of the SiC substrate 10, and the MOSFET shown in FIG. 1 is completed.

<A-4. Simulation results>
Next, the verification result by simulation about the effect of performing ion implantation from an oblique direction with respect to the implantation surface in forming the well region of the MOSFET will be described.

  First, the concentration profile of the well region was calculated when ion implantation was performed at an implantation angle of −30 ° to 30 ° for each of the 4 ° off and 8 ° off SiC substrates. Here, when the implantation angle is negative, it is when the implantation direction is tilted in the off direction of the substrate, that is, in the <11-20> direction (c-axis direction), and when the implantation angle is positive, the off direction. When the injection direction is tilted in the opposite direction, that is, in the <-1-120> direction. With respect to the obtained concentration profile, the depth of the well region having the second conductivity type impurity concentration of the same concentration as the first conductivity type impurity concentration of the drift layer is defined as the tail of the concentration profile, and this value is set as an implantation angle of 0 °. FIG. 5 and FIG. 6 show the relationship with the injection angle relative to the reference. FIG. 5 shows the results for the SiC substrate with 4 ° off, and FIG. 6 shows the results for the SiC substrate with 8 ° off.

  From the results shown in FIGS. 5 and 6, when the implantation angle is set to 4 °, −11 ° to −15 °, and 19 ° to 23 °, the tailing of the concentration profile due to channeling is large for a 4 ° off SiC substrate. Become. For an SiC substrate that is 8 ° off, if the implantation angle is 8 °, −7 ° to −11 °, or 23 ° to 27 °, the tailing of the concentration profile due to channeling increases. That is, channeling is noticeable when the angle from the c-axis of the crystal plane serving as the implantation surface is 0 ° and ± 17 °. Therefore, in order to reduce the tail of the concentration profile as compared with the case where the implantation angle is not set, for a SiC substrate with 4 ° off, −18 ° or less, that is, 18 ° or more in the c-axis direction, 8 It is desirable to set an implantation angle of -14 ° or less, that is, 14 ° or more in the c-axis direction for a SiC substrate that is off. Even for substrates having off-angles other than 4 ° and 8 °, tailing of the concentration profile can be reduced by setting the implantation angle to be 22 ° or more from the c-axis.

Next, with respect to a SiC substrate that is 4 ° off, the well region is formed by performing oblique implantation at an implantation angle of 27 ° in the off direction of the substrate, and when the well region is formed without performing oblique implantation (implantation angle 0 °). For each of the cases where the region was formed, the on-resistance Ron of the MOSFET was calculated using simulation. FIG. 7 shows the impurity concentration profile of the well region. In FIG. 7, the horizontal axis represents the ion implantation depth, and the vertical axis represents the impurity concentration in the well region. FIG. 8 shows current-voltage characteristics in the on state. In FIG. 8, the horizontal axis indicates the drain voltage, and the vertical axis indicates the drain current density. FIG. 9 shows the on-resistance Ron calculated from the current-voltage characteristics of FIG. In FIG. 9, the horizontal axis represents the ion implantation angle, and the vertical axis represents the on-resistance Ron. The ion implantation of the well region 30 is assumed to be an acceleration energy of 1000 keV and an implantation amount of 1 × 10 ¹⁴ cm ^−3, and other parameters are assumed to be MOSFET elements used for in-vehicle use or general industry.

  From the results of FIG. 7, it can be seen that by performing oblique ion implantation, the change in the impurity concentration profile of the well region becomes steep and the JFET length is shortened. This is because secondary channeling is suppressed. Further, from the results of FIGS. 8 and 9, it can be seen that the on-resistance is reduced by performing the oblique ion implantation. This is because by performing oblique ion implantation in a direction parallel to the sidewall of the implantation mask, the JFET length is shortened without increasing the channel resistance, and thus the JFET resistance is reduced.

<A-5. Modification>
In the above description, the implantation mask 31 for forming the well region 30 is formed in a stripe shape parallel to the off direction of the substrate 10 (FIG. 2). However, the implantation mask 31 does not necessarily have a stripe shape, and may be formed by a plurality of rectangles as shown in FIG. In this case, the longitudinal direction of the implantation mask 31 is parallel to the off direction of the substrate 10, and the ion implantation direction is parallel to the longitudinal side wall of the implantation mask 31. By performing oblique ion implantation in this direction, both channel resistance and JFET length can be reduced.

  Moreover, although the silicon carbide semiconductor device of this Embodiment was demonstrated as MOSFET, other semiconductor devices provided with insulated gate structures, such as IGBT, may be sufficient.

<A-6. Effect>
The silicon carbide semiconductor device according to the first embodiment is separated from the first conductivity type SiC substrate 10, the first conductivity type drift layer 20 on the main surface of the SiC substrate 10, and the surface layer of the drift layer 20. A well region 30 of a second conductivity type provided to the drift region 20 from 1 × 10 ¹⁸ cm ^{−3 in} the well region 30 when the second conductivity type impurity concentration is 400 nm or less in the depth direction. Having a retrograde profile that decreases to a concentration equal to the first conductivity type impurity concentration at. When the impurity concentration of the well region 30 is low on the surface, the channel resistance is reduced, and when it is 1 × 10 ¹⁸ cm ⁻³ or more at a certain depth, punch-through is suppressed, and then sharply within a range of 400 nm or less. By decreasing, the JFET length is reduced, so that the JFET resistance is reduced. Therefore, both reduction in channel resistance and reduction in JFET resistance can be achieved.

  SiC substrate 10 has a principal surface with an off-angle with respect to the (0001) plane and a polytype of 4H. The well region 30 is provided in a stripe shape. The silicon carbide semiconductor device is a MOSFET or an IGBT.

  In the method for manufacturing a silicon carbide semiconductor device according to the first embodiment, first conductivity type drift layer 20 is formed on the main surface of first conductivity type SiC substrate 10, and is separated from the surface layer of drift layer 20. The well region 30 of the second conductivity type provided is formed. In the well region 30, a rectangular implantation mask 31 is formed on the drift layer 20, and ions are implanted in a direction parallel to the longitudinal side wall of the implantation mask 31 and from an oblique direction with respect to the implantation surface of the drift layer 20. Therefore, the change in the impurity concentration profile becomes steep in the well region, and both the channel resistance and the JFET length can be reduced.

  Further, the main surface of SiC substrate 10 has an off angle in the off direction with respect to the (0001) plane, and the ion implantation for forming well region 30 is performed in a direction parallel to the off direction. And JFET length can be reduced.

  The angle of the ion implantation with respect to the implantation surface when forming the well region 30 is set to be equal to or larger than the angle obtained by subtracting the off angle from 22 ° in the off direction from the normal line of the implantation surface. As a result, the tail of the profile of the impurity concentration due to ion implantation can be reduced, and the well region can be formed shallow, so that the JFET resistance can be reduced.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  10 SiC substrate, 20 drift layer, 21 separation region, 30 well region, 31 implantation mask, 35 well contact region, 40 source region, 50 gate insulating film, 55 interlayer insulating film, 60 gate electrode, 70 source ohmic electrode, 71 back surface Ohmic electrode, 80 source electrode, 85 drain electrode, 100 MOSFET.

Claims (7)

A first conductivity type silicon carbide substrate;
A first conductivity type drift layer on a main surface of the silicon carbide substrate;
A second conductivity type well region provided on a surface layer of the drift layer so as to be spaced apart from each other;
The well region has a retrograde profile in which the second conductivity type impurity concentration decreases from 1 × 10 ¹⁸ cm ⁻³ to a concentration equal to the first conductivity type impurity concentration in the drift layer in a depth direction of 400 nm or less. Have
Silicon carbide semiconductor device. In the silicon carbide substrate, the plane orientation of the main surface has an off angle with respect to the (0001) plane, and the polytype is 4H.
The silicon carbide semiconductor device according to claim 1. The well region is provided in a stripe shape,
The silicon carbide semiconductor device according to claim 1 or 2. The silicon carbide semiconductor device is a MOSFET or an IGBT,
The silicon carbide semiconductor device according to claim 1. Forming a first conductivity type drift layer on a main surface of the first conductivity type silicon carbide substrate;
Forming a second conductivity type well region spaced apart from each other on a surface layer of the drift layer;
A method for manufacturing a silicon carbide semiconductor device, comprising:
The well region is formed by forming a rectangular implantation mask on the drift layer, and performing ion implantation in a direction parallel to a longitudinal side wall of the implantation mask and from an oblique direction with respect to the implantation surface of the drift layer. It is formed,
A method for manufacturing a silicon carbide semiconductor device. The main surface of the silicon carbide substrate has an off angle in the off direction with respect to the (0001) plane,
The ion implantation is performed in a direction parallel to the off direction.
A method for manufacturing a silicon carbide semiconductor device according to claim 5. An angle of the ion implantation with respect to the implantation surface is equal to or more than an angle obtained by subtracting the off angle from 22 ° in the off direction from a normal line of the implantation surface.
A method for manufacturing a silicon carbide semiconductor device according to claim 6.

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