JP2001144288A - Silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To further reduce MOSFET the on-state resistance. SOLUTION: A current, flowing through a channel region formed on a surface channel layer 5, is set so as to flow in a [11-20] direction. In this way, by having the direction of a current flowing through the channel region set as the direction of [11-20], where channel mobility becomes maximum, the channel resistance can be reduced, and a MOSFET can be further decreased in the on-state resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a storage type MOSFE.
The present invention relates to a silicon carbide semiconductor device such as a T-type or inversion type MOSFET, and particularly to a vertical power MOSFET for high power.

[0002]

2. Description of the Related Art Conventionally, a planar type MO using silicon carbide
An SFET is disclosed in Japanese Patent Application Laid-Open No. 10-308510.

FIG. 5 is a cross-sectional view of this planar type MOSFET.
Will be described.

An n ⁺ type substrate 1 made of silicon carbide has an upper surface as a main surface 1a and a lower surface opposite to the main surface 1a as a back surface 1a.
b. On the main surface 1a of the n ⁺ type substrate 1,
An n ⁻ -type epitaxial layer (hereinafter, referred to as an n ⁻ -type epi layer) 2 made of silicon carbide having a lower dopant concentration than the substrate 1 is stacked.

At this time, the main surface 1a of the n ⁺ type substrate 1 and the upper surface of the n ⁻ type epi layer 2 are (0001) Si plane or (11-20) a plane. This is (0001)
By using a Si surface, a low surface state density can be obtained,
This is because a crystal having a low surface state density and completely no helical transition can be obtained by using the (11-20) a-plane.

A p-type base region 3 having a predetermined depth is formed in a predetermined region in the surface layer portion of n ⁻ -type epi layer 2. This p-type base region 3 is formed using B as a dopant, and has a concentration of about 1 × 10 ¹⁷ cm ⁻³ or more. An n ⁺ -type source region 4 shallower than the base region 3 is formed in a predetermined region of the surface layer of the p-type base region 3.

Furthermore, n ⁺ -type source region 4 and the n ^- so as to connect the type epi layer 2, the surface portion of the p-type base region 3 n
^The -type SiC layer 5 is extended. This n ⁻ -type SiC layer 5 is formed by epitaxial growth.
The crystal of the epitaxial film is 4H, 6H, 3C. The n ⁻ -type SiC layer 5 functions as a channel forming layer during operation of the device. Hereinafter, n ^- type Si
The C layer 5 is called a surface channel layer.

The surface channel layer 5 is formed using N (nitrogen) as a dopant, and the dopant concentration is as low as about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ , for example. , N ⁻ -type epi layer 2 and p-type base region 3 are lower than the dopant concentration. Thereby, low on-resistance is achieved.

The n ⁻ -type epi layer 2 located between the p-type base regions 3 constitutes a so-called J-FET section 6.

A gate oxide film 7 is formed on the upper surface of surface channel layer 5 and the upper surface of n ⁺ type source region 4 by thermal oxidation. Further, a polysilicon gate electrode 8 is formed on gate oxide film 7. The polysilicon gate electrode 8 is covered with an insulating film 9. L as the insulating film 9
TO (Low Temperature Oxide)
A membrane is used. A source electrode 10 is formed on the insulating film 9, and the source electrode 10 is an n ⁺ type source region 4.
And p-type base region 3. Further, a drain electrode layer 11 is formed on the back surface 1b of the n ⁺ type substrate 1.

The planar type MOSF constructed as described above
Since the ET operates in the accumulation mode in which the channel is induced without inverting the conductivity type of the channel forming layer, the channel mobility can be increased as compared with the MOSFET in the inversion mode in which the conductivity type is inverted, and the on-resistance is reduced. Can be done.

[0012]

SUMMARY OF THE INVENTION However, MOS
It is desired to further reduce the on-resistance of the FET.

The present invention has been made in view of the above problems, and has as its object to further reduce the on-resistance of a silicon carbide semiconductor device.

[0014]

Means for Solving the Problems The present inventors have proposed MOSF.
Various experiments were conducted to further reduce the on-resistance of the ET. As a result, it was found that the channel mobility affecting the on-resistance had a plane orientation dependency. This plane orientation dependency will be described.

First, a plurality of lateral MOSFETs shown in FIG. 6 were formed on a (0001) plane substrate, and the dependence of the channel mobility on the plane direction was examined. Lateral type M formed here
In the OSFET, a source 101 and a drain 102 are arranged in a predetermined direction, a gate electrode 103 is formed on a portion between the source 101 and the drain 102, and a channel region is formed between the source 101 and the drain 102. It is. And such a lateral type MOSF
A plurality of ETs are formed, and a source 101 of each MOSFET,
Assuming that the angle between the arrangement direction of the drains 102 and the <11-20> direction is θ, the channel mobility of each MOSFET was examined so that the angle θ of each MOSFET became a different value.

As a result, the channel mobility showed a plane direction dependency as shown in FIG. That is, when the current direction is substantially parallel to [11-20], the channel mobility increases. Therefore, if the current direction is substantially parallel to [11-20], it can be said that a low on-resistance can be obtained.

In general, an off-substrate having a crystal surface shifted from the substrate surface is used for a silicon carbide substrate for manufacturing reasons, but the channel mobility has direction dependence also in the off-direction of the off-substrate. are doing.

As shown in FIG. 8, a plurality of lateral MOSFETs having the same structure as in FIG. 7 are formed, and the direction of the current flowing in the channel region of each MOSFET is changed in angle with respect to the off direction of the off-substrate. The directional dependence of the degree was evaluated. FIG. 9 shows the result.

As shown in this figure, it can be seen that the channel mobility decreases when the current direction approaches parallel to the off direction, and increases when the current direction is perpendicular to the off substrate. This is because, as can be seen from the schematic diagram of the off-substrate shown in FIG. 10, there are steps on the surface of the off-substrate 110 and the surface of the epitaxial layer 111 formed on the surface, so that the step crosses this step. Then, it becomes difficult for the current to flow.

Therefore, the invention according to claim 1 is characterized in that the direction of the current flowing through the channel region formed under the gate electrode (8) is set to [11-20]. Further, the invention according to claim 2 is characterized in that the direction of the current flowing through the channel region formed in the surface channel layer (5) is set to [11-20].

As described above, by setting the direction of the current flowing through the channel region to the [11-20] direction in which the channel mobility is maximized, the channel resistance can be reduced, and the on-resistance can be further reduced in the MOS. Can be achieved.

In the invention according to claim 3 or 4,
The lateral MOSFET is characterized in that the direction of the current flowing through the channel region is set to [11-20].

As described above, even in the lateral type MOSFET, the channel mobility becomes maximum [11-20].
By setting the direction, it is possible to obtain the same effect as the first or second aspect of the present invention.

According to a fifth aspect of the present invention, both the base region and the source region have a polygonal planar shape, and at least one side of the polygon is [1-10].
0].

As described above, the base region and the source region are formed by polygons, and at least one side of the polygon is [1--
100], it is possible to easily design the planar shape of the base region and the source region while obtaining the effect of claim 1 or 2.

For example, the polygon may be a hexagon whose interior angles are substantially equal.
In this case, since all the directions of the current flowing through the channel region can be set in the [11-20] direction, the channel resistance can be reduced, and the on-resistance of the MOSFET can be further reduced.

According to the seventh aspect of the present invention, the semiconductor substrate is an off-substrate in which the direction of the normal to the main surface has a predetermined angle with respect to the <0001> direction, and the direction of the current flowing through the channel region is The off direction is set in a plane including the direction of the surface normal and the <0001> normal and perpendicular to the off direction perpendicular to the normal of the main surface. It is characterized by.

As described above, by setting the direction of the current flowing through the channel region to be perpendicular to the off direction,
The channel mobility can be increased without being affected by the unevenness of the off-substrate. This makes it possible to further reduce the on-resistance of the MOSFET.

According to the present invention, both the base region and the source region have a stripe-shaped planar shape, and the long sides of the stripe shape are set parallel to the off direction. It is characterized by having.

As described above, by making the long sides of the stripe shape parallel to the off direction, that is, by making the channel region perpendicular to the off direction, the same effect as the invention according to claim 7 is obtained. And the planar shape can be easily designed.

Note that the reference numerals in parentheses of the above means indicate the correspondence with specific means described in the embodiments described later.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 (a) is a plan view and a sectional view of a storage type n-channel type planar MOSFET (vertical power MOSFET) to which an embodiment of the present invention is applied. ) And (b). FIG.
Directionality corresponding to the structure of the vertical power MOSFET is shown above the plane of FIG.

Hereinafter, a vertical power MOSF based on FIG.
The structure of the ET will be described. Since the vertical power MOSFET according to the present embodiment has substantially the same configuration as that of the conventional power MOSFET shown in FIG. 5, the same components as those in FIG. 5 are denoted by the same reference numerals, and only different portions will be described.

The vertical power MOSFET according to the present embodiment
In T, the p-type base region 3 and the n ⁺ -type source region 4 have a hexagonal shape having the same internal angle as shown in FIG. 1A, and a plurality of hexagons are regularly arranged at a pitch width a. Has become. Each side S1, S2, S3, S4, S5, S6 of the p-type base region 3 constituting this hexagon, and each side R1, R2, R3, R of the n ⁺ type source region 4
4, R5 and R6 are all set substantially parallel to the [1-100] direction.

Therefore, the directions 51, 52, 53, 54, 5 of the current flowing from the n ⁺ type source region 4 to the surface channel layer
5, 56 are set in parallel with [11-20].

An off substrate is used for the n ⁺ type substrate 1, and the off direction of the main surface 1 is set to <0-110>. Therefore, main surface 1a of n ⁺ type substrate 1
The n ⁻ -type epi layer 2 epitaxially grown on the substrate also takes over the shape of the main surface 1a, and the surface of the n ⁻ -type epi layer 2 is in the same off direction.

Therefore, the current directions 51 and 54 flowing from the n ⁺ type source region 4 to the surface channel layer 5 are set perpendicular to the off direction of the n ⁻ type epi layer 2.

The vertical power MOSFE thus configured
T has a current direction of [11-20] (that is, <2-1-
10>, <11-20>, <-12-10>, <-21
10>, <-1-120>, and <1-210>), the channel mobility can be increased and the on-resistance can be reduced as described above. Can be.

In addition, since the current direction is perpendicular to the off direction of the off substrate, as described above,
The influence of the step can be prevented, and the channel mobility can be increased. For this reason, the on-resistance can be further reduced.

Since the planar shapes of the p-type base region 3 and the n ⁺ -type source region 4 are hexagonal, it is possible to easily design these planar shapes.

(Second Embodiment) In the above embodiment, the case where one embodiment of the present invention is applied to an accumulation type vertical power MOSFET has been described. However, in this embodiment, the present invention is applied to an inversion type vertical power MOSFET. A case where one embodiment of the present invention is applied will be described.

FIGS. 2A and 2B are a plan view and a cross-sectional view, respectively, of an inverted vertical power MOSFET according to the present embodiment. Since the inversion type MOSFET is almost the same as the storage type MOSFET, the same components are denoted by the same reference numerals as those in FIG. 1 and only different portions will be described.

In this embodiment, a gate oxide film 7 is formed on the surface of a portion of the p-type base region 3 between the n ⁺ -type source region 4 and the n ⁻ -type epi layer 2. A channel region is formed on the surface of the p-type base region 3 located below. That is, the surface channel layer 5 is eliminated from the inverted vertical power MOSFET shown in FIG.

In such a configuration, the planar shapes of the p-type base region 3 and the n ⁺ -type source region 4 are hexagons having the same internal angle as shown in FIG. 2A, and the hexagons are regularly formed with a pitch width a. It has a structure of multiple arrangements. Each side S1, S2, of the p-type base region 3 constituting this hexagon
S3, S4, S5, S6 and each side R1, R2, R3, R4, R5, R6 of the n ⁺ type source region 4 are all [1
−100] direction.

Accordingly, the directions 51, 5 of the current flowing from the n ⁺ type source region 4 to the channel region of the p-type base region 3
Since 2, 53, 54, 55, and 56 are set in parallel to [11-20], channel mobility can be increased as in the first embodiment, and on-resistance can be reduced. .

An off-substrate having an off-direction similar to that of the first embodiment is used as the n ⁺ type substrate 1.
^- off direction of the surface of the type epi layer 2 is in the <0-110>.

Accordingly, the current directions 51 and 54 flowing from the n ⁺ type source region 4 to the surface channel layer 5 are set perpendicular to the off direction of the n ⁻ type epi layer 2, and the channel direction is the same as in the first embodiment. The mobility can be increased, and the on-resistance can be further reduced.

As described above, the inverting vertical power MOSF
In the ET, as in the first embodiment, the current direction is set to [1].
1-20], or set perpendicular to the off direction, the on-resistance can be reduced.

Third Embodiment FIGS. 3A and 3B are a plan view and a cross-sectional view, respectively, of an n-channel vertical power MOSFET according to a third embodiment of the present invention.
In the present embodiment, the layout of the vertical power MOSFET having the cross-sectional structure shown in FIG. 1B is changed. The basic configuration of the vertical power MOSFET is the same as that of the first embodiment. I will explain only.

In this embodiment, the p-type base regions 3 and n
^{The +} type source region 4 has a stripe shape extending in one direction (perpendicular to the plane of FIG. 3B), and the stripe shape is regularly arranged with a pitch width a.

As in the first embodiment, an off substrate whose off direction is set to <0-110> is used as the n ⁺ type substrate 1. Therefore, the n ⁺ -type substrate epitaxially grown on 1 n ^- -type epitaxial layer 2 is also n ⁺ -type substrate 1
And the surface of the n ⁻ -type epi layer 2 is in the same off direction.

Then, each side S1, S2 of the p-type base region 3 forming the stripe shape and the n ⁺ -type source region 4
Are set so that the sides R1 and R2 are parallel to <0-110>.

That is, the direction 61, 62 of the current flowing from the n ⁺ type source region 4 to the surface channel layer 5 is <2-1-1.
0> and perpendicular to the off direction.

As described above, in the directions 61 and 62 of the current flowing through the channel region, the channel mobility is maximum [11-
20], the channel resistance can be reduced, and the on-resistance can be reduced. Further, since the directions 61 and 62 of the current flowing through the channel region are perpendicular to the off direction, the channel mobility can be further increased and the on-resistance can be further reduced.

In this embodiment, the storage type vertical power MOSFET has been described. However, the p-type base region 3 and the n ⁺ type source region 4 of the inverted type vertical power MOSFET are also formed in a stripe shape. By setting each side of the stripe shape to be parallel to <0-110>, the same effect as in the present embodiment can be obtained.

Further, since the p-type base region and the n ⁺ -type source region 4 are formed in a stripe shape, their planar shapes can be easily designed.

(Fourth Embodiment) An n-channel lateral power MOSFET according to a fourth embodiment of the present invention.
FIGS. 4A and 4B are a plan view and a cross-sectional view of T (horizontal power MOSFET), respectively. Note that FIG. 4B corresponds to a cross section taken along the line AA in FIG. 4A, but the scale is different from that of FIG. 4A for easy understanding of the cross-sectional configuration.

As shown in FIG. 4, the lateral power MOSFET
T is formed using n ⁺ type substrate 31 made of silicon carbide and having a back surface 31b opposite to main surface 31a and main surface 31b. As the n ⁺ type substrate 31, an off substrate whose off direction is set to <0-110> is used. An n ⁻ -type epi layer 32 is grown on the n ⁺ -type substrate 31. The n ⁻ type epi layer 32 is formed on the n ⁺ type substrate 3
1, the surface of the n ⁻ -type epi layer 2 is in the same off direction.

A p-type well region 33 is formed in the surface layer of the n ⁺ -type epi layer 32. In the surface layer portion of the p-type well region 33, an n ⁺ -type source region 34 and an n ⁺ -type drain region 35 are formed separately. These n ⁺ type source region 34 and n ⁺ type drain region 35 are [11-
20] direction.

A surface channel layer 36 made of a low-concentration n ⁻ -type layer is formed so as to connect the n ⁺ -type source region 34 and the n ⁺ -type drain region 35. Therefore, n
⁺ Through the surface channel layer 36 from the source region 34 n ⁺
Direction of the current flowing through the drain region 35 is <2-1-1.
0>.

On the surface of the surface channel layer 36, a polysilicon gate electrode 38 is formed via a gate oxide film 37. The upper surface of the n ⁻ -type epi layer 32 including the polysilicon gate electrode 38 is covered with an insulating film 39. Then, the source electrode 40 and the drain electrode 41 are electrically connected to the n ⁺ -type source region 34 and the n ⁺ -type drain region 35 via the contact holes formed in the insulating film 39, respectively.

The surface of the p-type well region 33 has p
^{A +} -type layer 42 is formed, and the p-type well region 33 is fixed at the same potential as the n ⁺ -type substrate 31 via a substrate electrode 43 electrically connected to the p ⁺ -type layer 42. ing.

The lateral power MOSF constructed as described above
In ET, since the direction of the current flowing through the surface channel layer 36 is set to the [11-20] direction in which the channel mobility is maximized, the channel mobility can be increased, and the on-resistance can be reduced. it can.

Furthermore, since the direction of the current flowing from the n ⁺ type source region 34 to the n ⁺ type drain region 35 via the surface channel layer 36 is parallel to <2-1-10>, the channel region Can be set perpendicular to the off direction. Thereby, the channel mobility can be further increased, and the on-resistance can be further reduced.

In this embodiment, the storage type lateral power MO
Although the SFET has been described, the inversion type lateral power MO
The same effect as in the present embodiment can be obtained for the SFET as well if the n ⁺ -type source region and the n ⁺ -type drain region are arranged substantially parallel to the [11-20] direction.

(Other Embodiments) In the first and second embodiments, the p-type base region 3 and the n ⁺ -type source region 4 are hexagonal, but may be other polygons. However, in the case of a hexagon, all the directions of the current flowing through the channel region are set in the [11-20] direction, so that the channel resistance can be reduced as compared with other polygons.

When indicating the plane orientation, etc., a bar "-" should normally be added above a desired number. However, in this specification, a bar is added before the desired number due to the limitation of expression means. Shall be attached.

[Brief description of the drawings]

FIG. 1 is a vertical power MO according to a first embodiment of the present invention.
FIG. 3 is a diagram schematically illustrating an SFET.

FIG. 2 shows a vertical power MO according to a second embodiment of the present invention.
FIG. 3 is a diagram schematically illustrating an SFET.

FIG. 3 is a vertical power MO according to a third embodiment of the present invention.
FIG. 3 is a diagram schematically illustrating an SFET.

FIG. 4 shows a lateral power MO according to a fourth embodiment of the present invention.
FIG. 3 is a diagram schematically illustrating an SFET.

FIG. 5 is a diagram showing a cross-sectional configuration of a conventional vertical power MOSFET.

FIG. 6 shows a MOSFE prototyped by the inventors for an experiment.
It is a figure for explaining T.

FIG. 7 is a diagram showing the result of examining the plane orientation dependence of channel mobility using the MOSFET shown in FIG. 6;

FIG. 8 shows a MOSFE prototyped by the inventors for an experiment.
It is a figure for explaining T.

9 is a diagram showing the direction dependency of the channel mobility on the off direction using the MOSFET shown in FIG.

FIG. 10 is a diagram illustrating an off-substrate used for a silicon carbide semiconductor device.

[Explanation of symbols]

1 ... n ⁺ -type substrate, 2 ... n ^-- type epi layer, 3 ... p-type base region, 4 ... n ⁺ -type source region, 5 ... surface channel layer, 7 ...
Gate oxide film, 8 gate electrode, 9 insulating film, 10 source electrode, 11 drain electrode.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 652F (72) Inventor Nobuyuki Oya 1-1-1, Showa-cho, Kariya-shi, Aichi Pref. F term (reference) 5F040 DA22 DC02 DC10 EA05 EC07 EM00

Claims (9)

[Claims] 1. A semiconductor substrate (1) of a first conductivity type having a main surface (1a) and a back surface (1b) opposite to the main surface and made of silicon carbide; and on a main surface of the semiconductor substrate. A first conductivity type semiconductor layer (2) made of silicon carbide having higher resistance than the semiconductor substrate; and a second conductivity type formed in a predetermined region of a surface portion of the semiconductor layer and having a predetermined depth. And a first conductivity type source region (4) formed in a predetermined region of a surface portion of the base region and shallower than a depth of the base region.
A gate insulating film formed on a portion of the base region sandwiched between the source region and the semiconductor layer;
And a gate electrode (8) formed on the gate insulating film.
A silicon carbide semiconductor device comprising: a source electrode (10) formed to be in contact with the base region and the source region; and a drain electrode (11) formed on a back surface of the semiconductor substrate (1). A silicon carbide semiconductor device, wherein a direction of a current flowing through a channel region formed below the gate electrode is set to [11-20]. 2. A semiconductor substrate (1) of a first conductivity type having a main surface (1a) and a back surface (1b) opposite to the main surface, the semiconductor substrate being made of silicon carbide, and on a main surface of the semiconductor substrate. A first conductivity type semiconductor layer (2) made of silicon carbide having higher resistance than the semiconductor substrate; and a second conductivity type formed in a predetermined region of a surface portion of the semiconductor layer and having a predetermined depth. And a first conductivity type source region (4) formed in a predetermined region of a surface portion of the base region and shallower than a depth of the base region.
A surface channel layer (5) made of silicon carbide formed at a surface portion of the base region and a surface portion of the semiconductor layer so as to connect the source region and the semiconductor layer; A gate insulating film (7) formed on the surface; and a gate electrode (8) formed on the gate insulating film
A silicon carbide semiconductor device comprising: a source electrode (10) formed to be in contact with the base region and the source region; and a drain electrode (11) formed on a back surface of the semiconductor substrate (1). The direction of a current flowing through a channel region formed in the surface channel layer is set to [11-20]. 3. A silicon carbide substrate having a main surface (31a) and a back surface (31b) opposite to the main surface, and comprising a semiconductor layer (32) of a first conductivity type on the main surface side. A semiconductor substrate (31); a second conductivity type well region (33) formed in a predetermined region of a surface portion of the semiconductor layer; and a depth region of the well region formed in a predetermined region of the surface layer portion of the well region. Source region of the first conductivity type (3
4) and a drain region (35); a gate insulating film (37) formed on the well region between the source region and the drain region; and a gate formed on the gate insulating film. Electrode (38)
And a source electrode (4) electrically connected to the source region.
0), a drain electrode (41) electrically connected to the drain region, and a substrate electrode (43) formed on the well region to fix the potential of the well region. 2. The silicon carbide semiconductor device according to claim 1, wherein a direction of a current flowing through a channel region formed below the gate electrode is set to [11-20]. 4. A silicon carbide substrate having a main surface (31a) and a back surface (31b) opposite to the main surface, and comprising a semiconductor layer (32) of a first conductivity type on the main surface side. A semiconductor substrate (31); a second conductivity type well region (33) formed in a predetermined region of a surface portion of the semiconductor layer; and a depth region of the well region formed in a predetermined region of the surface layer portion of the well region. Source region of the first conductivity type (3
4) and a drain region (35); a surface channel layer (36) made of silicon carbide formed on a surface portion of the well region located between the source region and the drain region; A gate insulating film (37) formed on the surface; and a gate electrode (38) formed on the gate insulating film.
And a source electrode (4) electrically connected to the source region.
0), a drain electrode (41) electrically connected to the drain region, and a substrate electrode (43) formed on the well region to fix the potential of the well region. 2. The silicon carbide semiconductor device according to claim 1, wherein a direction of a current flowing through a channel region formed in the surface channel layer is set to [11-20]. 5. A planar shape of each of the base region and the source region is a polygon, and at least one side of the polygon is set to [1-100]. The silicon carbide semiconductor device according to claim 1 or 2, wherein: 6. The silicon carbide semiconductor device according to claim 5, wherein said polygon is a hexagon whose interior angles are substantially equal. 7. The semiconductor substrate is an off-substrate in which a direction of a normal to the main surface has a predetermined angle with respect to a <0001> direction, and a direction of a current flowing through the channel region is:
The off direction is set so as to be in a plane including the direction of the normal to the main surface and the <0001> normal and perpendicular to the off direction perpendicular to the normal of the main surface. The silicon carbide semiconductor device according to claim 1, 2, 5, or 6. 8. The base region and the source region both have a planar shape in the form of a stripe, and the long sides of the stripe are set parallel to the off direction. The silicon carbide semiconductor device according to claim 7. 9. A semiconductor substrate (1) of a first conductivity type having a main surface (1a) and a back surface (1b) opposite to the main surface and made of silicon carbide, and on a main surface of the semiconductor substrate. A first conductivity type semiconductor layer (2) made of silicon carbide having higher resistance than the semiconductor substrate; and a second conductivity type formed in a predetermined region of a surface portion of the semiconductor layer and having a predetermined depth. And a first conductivity type source region (4) formed in a predetermined region of a surface portion of the base region and shallower than a depth of the base region.
A gate insulating film formed on a portion of the base region sandwiched between the source region and the semiconductor layer;
And a gate electrode (8) formed on the gate insulating film.
A silicon carbide semiconductor device comprising: a source electrode (10) formed to be in contact with the base region and the source region; and a drain electrode (11) formed on a back surface of the semiconductor substrate (1). The base region and the source region both have a hexagonal planar shape, and each side of the hexagon is [1
-100].