JP2009049260A - Lateral semiconductor device with high driving capacity using trench structure - Google Patents

Lateral semiconductor device with high driving capacity using trench structure Download PDF

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JP2009049260A
JP2009049260A JP2007215552A JP2007215552A JP2009049260A JP 2009049260 A JP2009049260 A JP 2009049260A JP 2007215552 A JP2007215552 A JP 2007215552A JP 2007215552 A JP2007215552 A JP 2007215552A JP 2009049260 A JP2009049260 A JP 2009049260A
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trench
gate
view
sectional
semiconductor device
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Tomomitsu Risaki
智光 理崎
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Seiko Instruments Inc
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Seiko Instruments Inc
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Priority to PCT/JP2008/064852 priority patent/WO2009025308A1/en
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Abstract

<P>PROBLEM TO BE SOLVED: To further improve a driving capacity without increasing an element area, with respect to a lateral MOS with a high driving capacity, wherein the gate width per unit area is increased by forming a plurality of trenches horizontally in a gate length direction. <P>SOLUTION: In the lateral MOS with a high driving capacity, where the gate width per unit area is increased by forming a plurality of trenches 007 horizontally in a gate length direction, as shown in figures (Fig.(a) is plan view and Fig.(b) is bird's-eye view), trench patterns are laid out so that all surfaces of trench uneven portions are [100], and gate surfaces are all set to [100]. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、高駆動能力が要求される半導体装置に関する。   The present invention relates to a semiconductor device that requires high drive capability.

時代とともに半導体装置は微細加工技術を駆使することにより、能力を下げずにより小さく作成できるようになった。高駆動能力を有する半導体素子においてもその流れは例外ではなく、微細加工技術を駆使することにより単位面積当たりのオン抵抗の低減が図られてきた。しかしながら、素子を微細化することによって生じる耐圧の低下は、微細加工による更なる駆動能力の向上に歯止めをかけていることも事実である。この微細化と耐圧のトレードオフを打破するために、これまでさまざまな構造の素子が提案されており、現在主流な構造としては、高耐圧かつ高駆動能力を有するPower MOS FETを例にとると、トレンチゲートMOSがあげられる。トレンチゲートMOSは高耐圧かつ高駆動能力を有するDMOSの中でも最も集積度の高いものでる。しかしながら、トレンチゲートMOSは基板の深さ方向に電流を流す縦型MOS構造であり、素子単体としては非常に優れた性能を有しているが、ICとのオンチップ化には不利である。ICとのオンチップ化を考慮すると、やはり従来の横型MOS構造を選ばざるを得ない。耐圧を低下させずに更に単位面積当たりのオン抵抗を低減する方法として、ゲート部を凸部と凹部を有するトレンチ構造にすることによってゲート幅を稼ぐ横型トレンチゲート型トランジスタが考案されている（例えば、特許文献１参照）。図４に従来技術の概念図を示す。ここで、図４(a)は平面図、図４(b)は図４(a)の線分4B-4B'の断面図、図４(c)は図４(a)の線分4C-4C'に沿った断面図、図４(d)は(a)の線分4D-4D'に沿った断面図である。ここで図４(a)において図を見易くするためトレンチ外部のゲート電極003とゲート絶縁膜004は透明にしてある。太線はゲート電極003のエッジを示している。ゲート部をトレンチ構造にすることにより横型MOSの単位平面積当たりのゲート幅を拡げオン抵抗を低減する技術である。
特許３４０５６８１号公報 特開２００６−２９４６４５号公報 特開２００６−４９８２６号公報 With the times, semiconductor devices can be made smaller without reducing their capabilities by making full use of microfabrication technology. The flow of semiconductor devices having high driving capability is no exception, and the on-resistance per unit area has been reduced by making full use of microfabrication technology. However, it is also true that the decrease in breakdown voltage caused by miniaturization of the element has stopped the further improvement of driving capability by microfabrication. In order to overcome this trade-off between miniaturization and withstand voltage, devices with various structures have been proposed so far. As a mainstream structure, a power MOS FET with high withstand voltage and high drive capability is taken as an example. And trench gate MOS. The trench gate MOS is the most integrated type of DMOS having a high breakdown voltage and a high driving capability. However, the trench gate MOS has a vertical MOS structure in which a current flows in the depth direction of the substrate and has a very excellent performance as a single element, but is disadvantageous for on-chip integration with an IC. Considering on-chip integration with the IC, the conventional lateral MOS structure must still be selected. As a method for further reducing the on-resistance per unit area without lowering the breakdown voltage, a lateral trench gate type transistor has been devised that increases the gate width by forming the gate portion into a trench structure having a convex portion and a concave portion (for example, , See Patent Document 1). FIG. 4 shows a conceptual diagram of the prior art. 4 (a) is a plan view, FIG. 4 (b) is a cross-sectional view of line 4B-4B ′ of FIG. 4 (a), and FIG. 4 (c) is a line 4C- of FIG. 4 (a). FIG. 4D is a cross-sectional view taken along the line 4D-4D ′ in FIG. Here, in order to make the drawing easier to see in FIG. 4A, the gate electrode 003 and the gate insulating film 004 outside the trench are transparent. The thick line indicates the edge of the gate electrode 003. This is a technique for reducing the on-resistance by increasing the gate width per unit plane area of the lateral MOS by making the gate portion a trench structure.
Japanese Patent No. 3405682 JP 2006-294645 A JP 2006-49826 A

しかし、上記の構成には１つの問題点がある。通常MOSを作る際には、酸化膜質向上の為ウエハ表面にSi面[100]を使用し、結晶方位を示すオリエンテーションフラット（ＯＦ）はキャリア移動度の高い[110]を利用し、MOSのソース・ドレインをＯＦに対し垂直または平行に設置する。しかしながら、上記の構成において同ウエハを利用し、図１４(a)に示すように、トレンチをＯＦに対して垂直または水平に設置してしまうと、トレンチ側面に関して[110]のSi面が露出し、その面がゲート面になりゲート酸化膜質が劣化する。また、図１４(b)に示すように、トレンチ上部および底部のゲート面は基板表面と平行であるため[100]のSi面になり、トレンチ側面に対して別の結晶面がゲート面となる。一般的に、酸化膜の成長具合は結晶面によって差があるため、トレンチ側面のゲート酸化膜厚（図１４(c)のdV）とトレンチ底面および上面のゲート酸化膜厚（図１４(c)のdH）は厚さが異なる。作成時には薄い方のゲート酸化膜が所望の耐圧を持つようにゲート酸化膜を成長させるため、厚いゲート酸化膜領域の駆動能力が低下し、効率の良いデバイスを作成することができない。   However, the above configuration has one problem. When making MOS, the Si surface [100] is used on the wafer surface to improve the oxide film quality, and the orientation flat (OF) showing the crystal orientation uses [110], which has high carrier mobility.・ Install the drain vertically or parallel to the OF. However, if the wafer is used in the above configuration and the trench is installed vertically or horizontally with respect to the OF as shown in FIG. 14A, the Si surface of [110] is exposed with respect to the side surface of the trench. The surface becomes the gate surface, and the gate oxide film quality deteriorates. Further, as shown in FIG. 14 (b), the gate surfaces at the top and bottom of the trench are parallel to the substrate surface, so that they are [100] Si surfaces, and another crystal plane is the gate surface with respect to the trench side surfaces. . In general, since the degree of growth of the oxide film varies depending on the crystal plane, the gate oxide film thickness on the trench side surface (dV in FIG. 14C) and the gate oxide film thickness on the trench bottom and top surfaces (FIG. 14C). DH) vary in thickness. Since the gate oxide film is grown so that the thinner gate oxide film has a desired withstand voltage at the time of production, the driving capability of the thick gate oxide film region is lowered, and an efficient device cannot be produced.

n型もしくはp型半導体基板表面から一定の深さに設けられた高抵抗p型半導体のウェル領域と、前記ウェル領域の表面から途中の深さまでの複数本のトレンチと、前記トレンチが形成する凹凸部の表面に設けられたゲート絶縁膜と、前記トレンチ内部に埋め込まれたゲート電極とを有する構造において、前記トレンチ凹凸部全ての半導体表面が結晶面[100]となる半導体装置とした。   A well region of a high resistance p-type semiconductor provided at a certain depth from the surface of the n-type or p-type semiconductor substrate, a plurality of trenches from the surface of the well region to a midway depth, and irregularities formed by the trenches In the structure having the gate insulating film provided on the surface of the portion and the gate electrode embedded in the trench, a semiconductor device in which the semiconductor surface of all the concave and convex portions of the trench becomes a crystal plane [100].

例えばトレンチ上面および底面が[100]でトレンチ側面が[110]のようなゲート面に複数の結晶面を利用するMOSに比べ、本発明のMOSはトレンチ凹凸全ての半導体表面を結晶面[100]としているため、ゲート酸化膜質が向上し、MOSの信頼性が向上するとともに、酸化膜を薄くすることができるため駆動能力が向上する。また、ゲート面を[100]結晶面しか用いないため、ゲート酸化膜厚の均一性が良く駆動能力が向上する。   For example, compared to a MOS that uses a plurality of crystal planes for the gate surface such as [100] for the top and bottom surfaces of the trench and [110] for the side surfaces of the trench, the MOS of the present invention has a crystal surface [100] for all the semiconductor surfaces of the trench irregularities. Therefore, the gate oxide film quality is improved, the reliability of the MOS is improved, and the oxide film can be thinned, so that the driving capability is improved. Moreover, since only the [100] crystal plane is used as the gate surface, the uniformity of the gate oxide film thickness is good and the driving capability is improved.

図１は本発明の代表的な実施例である。   FIG. 1 shows a typical embodiment of the present invention.

ここで、図１(a)は平面図、図１(b)は(a)の鳥瞰図である。図１(a)において、図を見易くするためトレンチ外部のゲート電極003とゲート絶縁膜004は透明にしてある。太線はゲート電極003のエッジを示している。ここで、それぞれの図に面方位を表す軸を示している。このようにトレンチ上面、底面、側面に結晶面[100]を採用することにより、ゲート酸化膜質が向上すると共に、ゲート酸化膜厚の均一性向上が得られ、信頼性と駆動能力が向上する。   Here, FIG. 1A is a plan view, and FIG. 1B is a bird's-eye view of FIG. In FIG. 1A, the gate electrode 003 and the gate insulating film 004 outside the trench are made transparent to make the drawing easier to see. The thick line indicates the edge of the gate electrode 003. Here, the axis | shaft showing a surface orientation is shown in each figure. By adopting the crystal plane [100] on the top, bottom, and side surfaces of the trench in this way, the gate oxide film quality is improved and the uniformity of the gate oxide film thickness is improved, and the reliability and driving ability are improved.

トレンチ上面、底面、側面に結晶面[100]を採用するための一つの方法は、図１５(a)に示すようにウエハ表面が[100]でＯＦが[110]ではなく[100]のウエハを用いればよい。二つめの方法は、図(b)に示すようにウエハ表面が[100]でＯＦが[110]のウエハに45°傾けてトレンチをパターニングすればよい。   One method for adopting the crystal plane [100] on the top, bottom and side surfaces of the trench is as shown in FIG. 15 (a) where the wafer surface is [100] and the OF is not [110] but [100]. May be used. In the second method, as shown in FIG. 2B, the trench may be patterned by tilting the wafer surface by 45 ° with respect to the wafer whose surface is [100] and OF is [110].

また、図２(a)は図１(a)の線分2A-2A'の断面図、図２(b)は図１(a)の線分2B-2B'の断面図、図３(a)は図１(a)の線分3A-3A'の断面図、図３(b)は図１(a)の線分3B-3B'の断面図である。図４に示す従来例において、ゲート電極003がトレンチ部全体を覆っているが、図１から図３に示す本発明では、トレンチの両端付近がゲート電極003に覆われていない構造となっている。このような構造において、l3を大きくすることによって（l2が大きくなる）、ソース及びドレイン領域とチャネルの接触面積が大きくすることが可能となる。   2 (a) is a cross-sectional view of line 2A-2A 'in FIG. 1 (a), FIG. 2 (b) is a cross-sectional view of line 2B-2B' in FIG. 1 (a), and FIG. ) Is a cross-sectional view taken along line 3A-3A 'in FIG. 1 (a), and FIG. 3 (b) is a cross-sectional view taken along line 3B-3B' in FIG. 1 (a). In the conventional example shown in FIG. 4, the gate electrode 003 covers the entire trench portion, but in the present invention shown in FIGS. 1 to 3, the vicinity of both ends of the trench is not covered with the gate electrode 003. . In such a structure, it is possible to increase the contact area between the source and drain regions and the channel by increasing l3 (l2 increases).

次に、製造法について記す。図６は本発明の製造法の一例である。図６(a)に示すように、表面付近にウェル領域005を形成したn型もしくはp型高抵抗半導体基板006に多数本のトレンチを形成する。ここで、トレンチの深さをウェル領域005の深さより深くすると、基板にリーク電流が流れてしまうため安易にトレンチの深さを深くすることは出来ないが、ウェル領域005を作成する為のイオン注入を、図１０(a)に示すように前記トレンチ領域作成直後の多方向からの斜めイオン注入によって行うことにより、更にトレンチ深さを深くすることが可能となる。なぜなら、左右の斜めイオン注入017によってトレンチ側面とトレンチ上面にイオンが注入され、図示していない手前と奥からの斜めイオン注入によってトレンチ上面と底面にイオンが注入され、その後の熱拡散によって図１０(b)に示すようにトレンチ底部より深くなるように形成されるからである。この手法を用いることで、ウェル領域005を作成した後にトレンチ領域を作成する手法よりも確実にトレンチを深く形成することができ、単位面積あたりのゲート幅を増加させることが可能となる。   Next, the manufacturing method will be described. FIG. 6 shows an example of the production method of the present invention. As shown in FIG. 6A, a large number of trenches are formed in an n-type or p-type high resistance semiconductor substrate 006 having a well region 005 formed in the vicinity of the surface. Here, if the depth of the trench is made deeper than the depth of the well region 005, a leakage current flows through the substrate, so that the depth of the trench cannot be easily increased. As shown in FIG. 10A, the trench depth can be further increased by performing oblique ion implantation from multiple directions immediately after the formation of the trench region. This is because ions are implanted into the trench side surface and the upper surface of the trench by oblique ion implantation 017 on the left and right sides, and ions are implanted into the upper and bottom surfaces of the trench by oblique ion implantation from the front and back (not shown). This is because it is formed deeper than the bottom of the trench as shown in FIG. By using this method, the trench can be formed deeper than the method of creating the trench region after creating the well region 005, and the gate width per unit area can be increased.

ただし、上記の方法でもトレンチ深さに限界はある。斜めイオン注入の角度θを変えずに単純にトレンチ深さを深くすると、図１１(a)に示すようにトレンチ底部領域のトレンチ側面にイオンが注入されない部分が生じ、熱拡散をしても図１１(b)に示すようにウェル領域005がトレンチ全体を囲まなくなる。一方、トレンチ底部領域のトレンチ側面にイオンが注入されるように斜めイオン注入角度θを小さくすると、図１２に示すようにトレンチ側面にイオンが十分に注入されず熱拡散後のウェルのイオン濃度プロファイルが一定でなくなる。   However, there is a limit to the trench depth even in the above method. If the trench depth is simply increased without changing the angle θ of the oblique ion implantation, a portion where ions are not implanted is generated on the side surface of the trench in the bottom region of the trench as shown in FIG. As shown in FIG. 11 (b), the well region 005 does not surround the entire trench. On the other hand, if the oblique ion implantation angle θ is reduced so that ions are implanted into the trench side surface in the trench bottom region, ions are not sufficiently implanted into the trench side surface as shown in FIG. Is not constant.

しかし、前記斜めイオン注入とエピタキシャル技術を組み合わせることで、トレンチ深さを上記限界以上に深くすることが可能となる。図１３(a)のように、半導体基板006の表面にウェルと同じ導電型となるようにイオン注入を施した領域016を形成する。その後図１３(b)のようにエピタキシャル成長により半導体膜を堆積させる。その後図１３(c)のようにトレンチ構造を作成し、図１３(d)のように多方向からによる斜めイオン注入を行う。エピタキシャル層と半導体基板間にイオン注入層が存在する為、熱拡散を施すことにより図１３(e)に示すようにトレンチ全体を囲むウェルを形成することが可能となる。この手法を用いれば、さらにトレンチ深さを深くすることが可能となり、更に単位面積あたりのゲート幅を増加させることが可能となる。   However, by combining the oblique ion implantation and the epitaxial technique, the trench depth can be made deeper than the above limit. As shown in FIG. 13A, a region 016 is formed on the surface of the semiconductor substrate 006 so as to have the same conductivity type as the well. Thereafter, a semiconductor film is deposited by epitaxial growth as shown in FIG. Thereafter, a trench structure is formed as shown in FIG. 13C, and oblique ion implantation is performed from multiple directions as shown in FIG. 13D. Since an ion implantation layer exists between the epitaxial layer and the semiconductor substrate, it is possible to form a well surrounding the entire trench as shown in FIG. 13 (e) by performing thermal diffusion. If this method is used, the trench depth can be further increased, and the gate width per unit area can be further increased.

次に図６(b)に示すように、基板表面を酸化してゲート絶縁膜004とゲート電極膜003を順に形成し、チャネルとする領域上のゲート電極膜003のみを残し、その他のゲート電極膜003をエッチングする。このとき、図５に示すようなソース及びドレイン領域とチャネルの接触面積の縮小によってオン抵抗低減が阻害されない程度に長さl3のトレンチ両端上部のゲート電極003もエッチバックし、トレンチ内部に埋め込まれているゲート電極003がd2>0になるようにする。   Next, as shown in FIG. 6B, the substrate surface is oxidized to form a gate insulating film 004 and a gate electrode film 003 in order, leaving only the gate electrode film 003 on the channel region, and other gate electrodes. The film 003 is etched. At this time, the gate electrode 003 at both upper ends of the trench having a length of l3 is also etched back to the extent that the reduction of the on-resistance is not hindered by the reduction of the contact area between the source and drain regions and the channel as shown in FIG. The gate electrode 003 is set so that d2> 0.

次に、図６(c)に示すように、イオン注入および不純物拡散によりソース領域001及びドレイン領域002を作成する。仮にd1<d2となり、ソース領域001及びドレイン領域002とチャネル部が離れてしまう場合には、斜めイオン注入をすることによりソース及びドレイン領域を図７に示すように形成すればよい。ここで図７は図１(a)の線分2B-2B'の断面図である。最後に、図６(c)に示す構造表面にパッシベーション膜を形成し、ソース、ゲート、ドレイン部にコンタクトホールを作成し、それぞれの電極を取出し完成する。上記の実施例において、導電型を反転することによってp-ch型MOS構造も同様に作成することができることは言うまでも無く、ツインウェル手法を用いれば、１チップで高駆動能力を有するCMOS構造を作成することも、IC混載も容易に可能となる。以上が、本発明の基本構造及び基本製造法である。   Next, as shown in FIG. 6C, a source region 001 and a drain region 002 are formed by ion implantation and impurity diffusion. If d1 <d2 and the source region 001 and the drain region 002 are separated from the channel portion, the source and drain regions may be formed as shown in FIG. 7 by performing oblique ion implantation. FIG. 7 is a cross-sectional view taken along line 2B-2B ′ in FIG. Finally, a passivation film is formed on the structure surface shown in FIG. 6 (c), contact holes are formed in the source, gate, and drain portions, and the respective electrodes are taken out and completed. In the above embodiment, it is needless to say that a p-ch type MOS structure can be formed in the same manner by inverting the conductivity type. If the twin well method is used, a CMOS structure having a high driving capability with one chip. Can be created easily, and IC can be mixed easily. The above is the basic structure and the basic manufacturing method of the present invention.

ここからは、上記の基本構造の応用について述べる。   From now on, the application of the above basic structure will be described.

通常のプレーナ型MOSにおいて、耐圧向上のため、基本構造をベースとし、さまざまな構造が存在する。本発明に関しても同様に、基本構造（図1）をベースとし、図８に示すようDDD（Double Diffused Drain）構造のものや、図９に示すようなLDMOS (Lateral Double diffused MOS) 構造などの従来技術との併合が可能であるため、容易に耐圧向上が図れる。   In ordinary planar MOS, there are various structures based on the basic structure to improve the breakdown voltage. Similarly, the present invention is based on the basic structure (FIG. 1), and has a DDD (Double Diffused Drain) structure as shown in FIG. 8 and an LDMOS (Lateral Double diffused MOS) structure as shown in FIG. Since it can be merged with technology, the breakdown voltage can be easily improved.

また、図１に示す凸部007の幅を1000A程度にすることによって、MOSがオン状態になる際に凸部内部が全て空乏化し、サブスレッショルド特性が向上する。したがってソース・ドレイン間のリークが減少し、閾値を下げることが可能となり、結果的に更に駆動能力を向上させることが可能となる。   Further, by setting the width of the convex portion 007 shown in FIG. 1 to about 1000 A, when the MOS is turned on, the entire convex portion is depleted and the subthreshold characteristic is improved. Therefore, the leakage between the source and the drain is reduced, the threshold value can be lowered, and as a result, the driving capability can be further improved.

以上、本発明の実施形態を説明したが、本発明は上記の実施形態に限定されるものではなく、本発明はその要旨を逸脱しない範囲で変形して実施できる。   As mentioned above, although embodiment of this invention was described, this invention is not limited to said embodiment, This invention can be deform | transformed and implemented in the range which does not deviate from the summary.

本発明の基本構造を示す図。(a) 平面図。(b) 鳥瞰図。The figure which shows the basic structure of this invention. (a) Plan view. (b) Bird's eye view. 図１(a)の断面図(a) 線分2A-2A'の断面図。(b) 線分2B-2B'の断面図。Sectional drawing of Fig.1 (a) (a) Sectional drawing of line segment 2A-2A '. (b) Sectional view of line 2B-2B '. 図１(a)の断面図。(a) 線分3A-3A'の断面図。(b) 線分3B-3B'の断面図。Sectional drawing of Fig.1 (a). (a) Sectional drawing of line segment 3A-3A '. (b) Sectional view of line segment 3B-3B '. 従来技術の実施例を示す図。(a) 平面図。(b) 図４(a)の線分4B-4B'の断面図。(c) 図４(a)の線分4C-4C'の断面図。(d) 図４(a)の線分4D4D'の断面図。The figure which shows the Example of a prior art. (a) Plan view. FIG. 4B is a cross-sectional view taken along the line 4B-4B ′ in FIG. (c) Sectional view of line segment 4C-4C ′ in FIG. (d) Sectional drawing of line segment 4D4D 'of Fig.4 (a). 図４のソース領域001もしくはドレイン領域002の鳥瞰図。色の濃い部分はチャネルを表す。FIG. 5 is a bird's-eye view of the source region 001 or the drain region 002 in FIG. 4. The dark part represents the channel. 本発明の製造工程を示した鳥瞰図。The bird's-eye view which showed the manufacturing process of this invention. d1<d2の場合の図１(a)の線分2B-2B'の断面図。Sectional drawing of line segment 2B-2B 'of Fig.1 (a) in the case of d1 <d2. DDD構造を有する本発明の鳥瞰図。The bird's-eye view of this invention which has DDD structure. LDMOS構造を有する本発明の鳥瞰図。The bird's-eye view of this invention which has LDMOS structure. トレンチ深さが比較的浅い場合の断面図。(a)多方向斜めイオン注入直後の断面図。(b)他方高斜めイオン注入後、イオンを熱拡散した断面図。Sectional drawing when the trench depth is relatively shallow. (a) Sectional view immediately after multidirectional oblique ion implantation. (b) Cross-sectional view in which ions are thermally diffused after high oblique ion implantation. トレンチ深さが深くイオン注入角度θが大きい場合の断面図。(a)多方向斜めイオン注入直後の断面図。(b)他方高斜めイオン注入後、イオンを熱拡散した断面図。Sectional drawing when trench depth is deep and ion implantation angle (theta) is large. (a) Sectional view immediately after multidirectional oblique ion implantation. (b) Cross-sectional view in which ions are thermally diffused after high oblique ion implantation. トレンチ深さが深くイオン注入角度θが小さいイオン注入直後の断面図。Sectional drawing immediately after ion implantation with a deep trench depth and small ion implantation angle (theta). エピタキシャル技術と斜めイオン注入法を用いたウェルの作成法。(a) 半導体基板表面にイオン注入を施した断面図。(b) 図１３(a)の基板表面にエピタキシャル成長によって半導体膜を形成した断面図。(c) 図１３(b)にトレンチ構造を形成した断面図。(d) 図１３(c)に多方向斜めイオン注入を施した断面図。(e) 図１３(d)に熱拡散を施した断面図。Well creation method using epitaxial technology and oblique ion implantation. (a) Sectional drawing which ion-implanted to the semiconductor substrate surface. FIG. 13B is a sectional view in which a semiconductor film is formed by epitaxial growth on the substrate surface in FIG. (c) Sectional view in which a trench structure is formed in FIG. (d) Sectional view of FIG. 13 (c) subjected to multidirectional oblique ion implantation. (e) Sectional view of FIG. 13 (d) with thermal diffusion. 従来技術のトレンチレイアウトおよびそのトレンチ断面図。(a) ウエハの平面図。(b) 線分3A-3A'（3B-3B'）の断面図。(c) 同図(b)に熱酸化を施した図。The trench layout of the prior art, and its trench sectional view. (a) Plan view of wafer. (b) Sectional drawing of line segment 3A-3A '(3B-3B'). (c) The figure which thermally oxidized in the figure (b). 本発明のトレンチレイアウト図。(a) ウエハ表面[100]、ＯＦ[100]を用いた場合。(b) ウエハ表面[100]、ＯＦ[110]を用いた場合。The trench layout figure of this invention. (a) When using wafer surface [100] and OF [100]. (b) When using wafer surface [100] and OF [110].

符号の説明Explanation of symbols

001 ソース領域
002 ドレイン領域
003 ゲート電極
004 ゲート絶縁膜
005 ウェル領域
006 高抵抗半導体基板
007 凸部
008 凹部
009 高抵抗n型半導体領域
010 高抵抗n型半導体基板
016 ウェルと同じ導電型となるようイオン注入を施された領域
017 イオン注入の方向
018 エピタキシャル成長による半導体膜
019 電流
020 チャネル部と接している部分
021 トレンチパターン
022 ウエハ 001 Source area
002 Drain region
003 Gate electrode
004 Gate insulation film
005 Well region
006 High resistance semiconductor substrate
007 Convex
008 recess
009 High resistance n-type semiconductor region
010 High resistance n-type semiconductor substrate
016 Ion-implanted region with the same conductivity type as the well
017 Direction of ion implantation
018 Semiconductor film by epitaxial growth
019 current
020 The part in contact with the channel
021 trench pattern
022 Wafer

Claims (3)

n型もしくはp型の半導体基板の表面から一定の深さに設けられた高抵抗p型半導体のウェル領域と、前記ウェル領域の表面から途中の深さまでの複数本のトレンチと、前記トレンチが形成する凹凸部の表面に設けられたゲート絶縁膜と、前記トレンチ内部に埋め込まれたゲート電極とを有する構造において、前記トレンチ凹凸部全の半導体表面が結晶面[100]となる半導体装置。   A well region of a high-resistance p-type semiconductor provided at a certain depth from the surface of an n-type or p-type semiconductor substrate, a plurality of trenches from the surface of the well region to an intermediate depth, and the trench formed A semiconductor device having a structure including a gate insulating film provided on a surface of a concavo-convex portion and a gate electrode embedded in the trench, wherein the semiconductor surface of the entire concavo-convex portion is a crystal plane [100]. 前記トレンチは矩形であり、前記半導体基板は基板表面の面方位が[100]でＯＦの方位が[100]であり、前記トレンチは各辺がＯＦに対して平行あるいは垂直となるように配置されたことを特徴とする請求項１に記載の半導体装置。   The trench is rectangular, the semiconductor substrate has a [100] plane orientation of the substrate surface and an OF orientation of [100], and the trench is arranged so that each side is parallel or perpendicular to the OF. The semiconductor device according to claim 1. 前記トレンチは矩形であり、前記半導体基板は基板表面の面方位が[100]でＯＦの方位が[110]であり、前記トレンチは各辺がＯＦに対して４５度の角度をなすように配置されたことを特徴とする請求項１に記載の半導体装置。   The trench is rectangular, the semiconductor substrate has a surface orientation of [100] and an OF orientation of [110], and the trench is arranged so that each side forms an angle of 45 degrees with respect to the OF. The semiconductor device according to claim 1, wherein:
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JP2013098402A (en) * 2011-11-02 2013-05-20 Renesas Electronics Corp Semiconductor device and semiconductor device manufacturing method
US10483391B2 (en) 2016-12-28 2019-11-19 Renesas Electronics Corporation Semiconductor device and method for manufacturing the same
WO2021186911A1 (en) * 2020-03-18 2021-09-23 ソニーセミコンダクタソリューションズ株式会社 Imaging device and electronic apparatus

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JPS62126675A (en) * 1985-11-27 1987-06-08 Toshiba Corp Semiconductor device and manufacture thereof
JPS63228710A (en) * 1987-03-18 1988-09-22 Toshiba Corp Semiconductor device
JPS63250852A (en) * 1987-04-08 1988-10-18 Sony Corp Semiconductor device
JPH06209106A (en) * 1993-01-12 1994-07-26 Matsushita Electron Corp Semiconductor device
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KR100641365B1 (en) * 2005-09-12 2006-11-01 삼성전자주식회사 Mos transistors having an optimized channel plane orientation, semiconductor devices including the same and methods of fabricating the same

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* Cited by examiner, † Cited by third party
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JP2013098402A (en) * 2011-11-02 2013-05-20 Renesas Electronics Corp Semiconductor device and semiconductor device manufacturing method
US10483391B2 (en) 2016-12-28 2019-11-19 Renesas Electronics Corporation Semiconductor device and method for manufacturing the same
WO2021186911A1 (en) * 2020-03-18 2021-09-23 ソニーセミコンダクタソリューションズ株式会社 Imaging device and electronic apparatus

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