TW200929540A - Lateral semiconductor device with high driving capacity using trench structure - Google Patents

Lateral semiconductor device with high driving capacity using trench structure Download PDF

Info

Publication number
TW200929540A
TW200929540A TW97131935A TW97131935A TW200929540A TW 200929540 A TW200929540 A TW 200929540A TW 97131935 A TW97131935 A TW 97131935A TW 97131935 A TW97131935 A TW 97131935A TW 200929540 A TW200929540 A TW 200929540A
Authority
TW
Taiwan
Prior art keywords
trench
gate
view
sectional
cross
Prior art date
Application number
TW97131935A
Other languages
Chinese (zh)
Inventor
Tomomitsu Risaki
Original Assignee
Seiko Instr Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instr Inc filed Critical Seiko Instr Inc
Publication of TW200929540A publication Critical patent/TW200929540A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

To further improve a driving capacity without increasing an element area, with respect to a lateral MOS with a high driving capacity, wherein the gate width per unit area is increased by forming a plurality of trenches horizontally in a gate length direction. In the lateral MOS with a high driving capacity, where the gate width per unit area is increased by forming a plurality of trenches 007 horizontally in a gate length direction, as shown in figures (Fig.(a) is plan view and Fig.(b) is bird's-eye view), trench patterns are laid out so that all surfaces of trench uneven portions are [100], and gate surfaces are all set to [100].

Description

200929540 九、發明說明 【發明所屬之技術領域】 本發明係關於要求高驅動能力之半導體裝置。 【先前技術】 近年來半導體裝置藉由運用微細加工技術，而成爲不 會降低能力且可以製作成更小型。即使在具有高驅動能力 ❹ 之半導體元件中，其流程也不例外，藉由運用微細加工技 術，以謀求降低每單位面積之接通電阻。但是，由於元件 微細化而產生耐壓下降，而制止了藉由微細加工來更加提 高驅動能力也係事實。200929540 IX. Description of the Invention [Technical Field] The present invention relates to a semiconductor device requiring high driving capability. [Prior Art] In recent years, semiconductor devices have been manufactured by using microfabrication technology without being reduced in capacity and can be made smaller. Even in semiconductor devices with high driving capability, the flow is no exception, and micro-machining technology is used to reduce the on-resistance per unit area. However, it is a fact that the withstand voltage is lowered due to the miniaturization of the components, and the driving ability is further improved by microfabrication.

爲了折衷該微細化和耐壓，至今提案有各種構造之元 件，以現在主流之構造而言，當以具有高耐壓並且高驅動 倉I力的Power MOS FET爲例時，貝IJ可舉出溝渠閘極MOS 。溝渠閘極MOS於具有高耐壓且高驅動能力之DMOS中 β 也爲積體度最高者。但是，溝渠閘極MOS爲使電流流通 於基板之深度方向之縱型MOS構造，以元件單體而言雖 然具有非常優良之性能，但是不利於與1C之晶載化。當 考慮到與1C之晶載化時，則不得不選以往之橫型MOS構 造。 以不降低耐壓又要降低每單位面積之接通電阻的方法 而言，提案有藉由將閘極部設爲具有凸部和凹部之溝渠構 造，來爭取閘極寬度之橫型溝渠型電晶體（例如參照專利 文獻1至3)。第4圖爲表示以往技術之槪念圖。在此， -4- 200929540 第4圖（a)爲平面圖，第4圖（b )爲線4B-4B’之剖面 圖，第4圖（c )爲沿著線4C-4C’之剖面圖，第4圖（d )爲沿著（a)之線4D-4D’之剖面圖。 橫型溝渠閘極型電晶體係由被配置成與電晶體之通道 方向平行之多數溝渠，上述電晶體係被配置在設置於η型 或ρ型之高電阻半導體基板006之表面之ρ型阱區域005 上；和藉由溝渠所規定之凹部008及位於凹部之兩側的凸 〇 部007 ;和被設置在凹部及凸部之表面的閘極絕緣膜004 ;和塡充凹部並且配置在凸部之閘極絕緣膜之上的閘極電 極〇〇3;和以與溝渠組合之方式被配置在夾著閘極電極之 兩側的阱區域表面的源極區域001及汲極區域002。在此 ，在第4圖（a)中，爲了容易觀看圖式，使溝渠外部之 閘極電極〇〇3和閘極絕緣膜004透明。粗線表示閘極電極 003之邊緣。藉由將閘極部設爲溝渠構造，爲擴寬橫型 MOS之每單位面積之閘極寬度降低接通電阻之技術。圖 〇 中之虛線〇 1 9表示流入電晶體之電流的路徑。 〔專利文獻1〕日本專利340568 1號公報 〔專利文獻2〕日本特開2006-294645號公報 〔專利文獻3〕日本特開2006-49826號公報 【發明內容】 (發明所欲解決之課題） 但是，上述構成則有一個問題點。通常於製作MOS 之時，爲了提升氧化膜質而在晶圓表面使用Si面{100}’ -5- 200929540 表示結晶方位之晶向切平邊（OF )利用載體移動度高之 [110]，將M0S之源極、汲極設置成對OF呈垂直或平行 。但是，在上述構成中，利用同晶圓，如第14圖（a)所 示般，當將溝渠設置成對OF呈垂直或水平之時，關於溝 渠側面露出{ 1 1 0}之Si面，其面成爲閘極面，閘極氧化膜 質劣化。再者，如第14圖（b)所示般，因溝渠上部及底 部之閘極面與基板表面平行，固成爲{100}之Si面，相對 〇 於溝渠側面另外之結晶面成爲閘極面。一般而言，氧化膜 之生長狀況由於結晶面而具有差異，故溝渠側面之閘極氧 化膜厚（第14圖（c)之dv)和溝渠底面及上面之閘極 氧化膜厚（第14圖（c)之dH)爲厚度不同。於作成時 ，因以薄的閘極氧化膜持有所欲之耐壓之方式，使閘極氧 化膜生長，故厚的閘極氧化膜區域之驅動能力下降，無法 作成效率佳之裝置。 ϋ (用以解決課題之手段） 半導體裝置之構造爲具有：被設置成從η型或ρ型之 半導體基板表面具有一定深度之高電阻Ρ型半導體之阱區 域，和從上述阱區域表面至上述半導體基板之途中深度被 平行設置於連結源極和汲極之方向之多數條溝渠，和被設 置在上述溝渠所形成之凹凸部表面之閘極絕緣膜，和被埋 入至上述溝渠內部之閘極電極，構成上述溝渠凹凸部之所 有半導體表面成爲結晶面{100}。 200929540 〔發明效果〕 相較於例如溝渠上面及底面爲{100}溝渠側面爲{110} 般之聞極面利用多數結晶面之MOS，本發明之]V10S因將 溝渠凹凸所有半導體表面設爲結晶面{100}，故提升聞極 氧化膜質，並提昇MOS之信賴性，並且可以使氧化膜薄 化，依此提高驅動能力。再者，因閘極面僅使用{100}結 晶面，故閘極氧化膜厚之均勻性佳，提高驅動能力。 【實施方式】 第1圖係表示本發明之代表性實施例的橫型MOS電 晶體。 在此，第1圖（a)爲平面圖，第1圖（b)爲（a) 之鳥瞰圖。對於與第4圖所示之先行技術對應之構成要素 賦予相同符號。在第1圖（a)中，爲了容易觀看圖，使 溝渠外部之閘極電極〇 〇 3和閘極絕緣膜〇 〇 4透明。粗線表 〇 示閘極電極003之邊緣。在此，在各個圖面顯示表示面方 位之軸。如此一來，在溝渠上面、底面、側面採用結晶面 {1 0 0 }，依此提升閘極氧化膜質，並取得閘極氧化膜厚較 隹均勻性，提高信賴性和驅動能力。 用以在溝渠上面、底面、側面採用結晶面{1 0 0 }之一 個方法係如第15圖（a)所7^般，並不是晶圓表面爲 {100}OF爲[11〇]’若使用[100]之晶圓即可。第二種方法 則係如圖（b )所示般’若45°傾斜於晶圓表面爲{ 100} OF 爲[1 1 0]之晶圓而圖案製作溝渠即可。 200929540 再者，第2圖（a)爲第1圖（a)之線2A-2A’之剖 面圖，第2圖（b)爲第1圖（a)之線2B_2B’之剖面圖 ，第3圖（a)爲第1圖（a)之線3A-3A’之剖面圖，第3 圖（b)爲第1圖（a)之線3B-3B’之剖面圖。在第4圖 所示之以往例中，雖然閘極電極003覆蓋溝渠部全體，但 是在第1圖至第3圖所示之本發明中，爲溝渠之兩端附近 不被閘極電極003覆蓋之構成。在如此之構造中，藉由增 〇 大13(12變大），可增大源極及汲極區域和通道之接觸 面積。 接著，針對製造法予以敘述。第6圖爲本發明之製造 法之一例。如第6圖（a)所示般，在表面附近形成有阱 區域005之η型或p型高電阻半導體基板〇〇6形成多數條 溝渠。在此，當使溝渠之深度較阱區域005之深度深時， 因洩漏電流流入至基板，故無法容易加深溝渠之深度，但 是可如第10圖（a)所示般藉由來自上述溝渠區域作成後 © 之多方向的傾斜離子注入，執行用以作成阱區域005之離 子注入，則能夠使溝渠深度變得更深。該是因爲藉由左右 之傾斜離子注入017在溝渠側面和溝渠上面注入離子，並 藉由來自無圖示之前方和後方之傾斜離子注入，在溝渠上 面和底面注入離子，依據之後的熱擴散，如第10圖（b) 所示般，形成較溝渠底部更深之故。藉由使用該手法，可 以較於作成阱區域005之後作成溝渠區域之手法更確實形 成深溝渠，可增加每單位面積之閘極寬度。 但是，在上述方法中溝渠深度也有界限。當不改變傾 -8 - 200929540 斜注入之角度0單純加深溝渠深度時，則如第1 1圖（a ) 所示般’在溝渠底部區域之溝渠側面產生不注入離子之部 分，即使執行熱擴散也如第11圖（b)所示般阱區域005 不包圍溝渠全體。另外，當以在溝渠底部區域之溝渠側面 被注入離子之方式縮小傾斜離子注入角度0時，則如第 12圖所示般，溝渠側面不充分注入離子，熱擴散後之阱 之離子濃度外形則爲非一定。 〇 但是，藉由組合上述傾斜離子注入和磊晶技術，可將 溝渠深度加深至上述界限以上。如第13圖（a)所示般， 在半導體基板0 0 6之表面以成爲與阱相同之導電型之方式 ，形成施有離子注入之區域016。之後，如第13圖（b) 所示般，藉由磊晶成長堆積半導體膜。之後如第13圖（c )般作成溝渠構造，如第13圖（d)般執行多方向之傾斜 離子注入。因在磊晶層和半導體基板間存在離子注入層， 故藉由施予熱擴散，如第13圖（e)所示般，可形成包圍 Ο 溝渠全體之阱。若藉由該手法，則可更加深溝渠深度，並 且更可增加每單位面積之閘極寬度。 接著，如第6圖（b)所示般，氧化基板表面而依序 形成閘極絕緣膜004和閘極電極膜003，並且僅殘留當作 通道之區域上之閘極電極膜003，並蝕刻其他之閘極電極 膜003。此時，藉由如第5圖所示般，縮小源極及汲極區 域和通道之接觸部份020之面積，以不阻礙接通電阻降低 之程度，也回蝕長度13之溝渠兩端上部之閘極電極〇〇3 ，並且被埋入至溝渠內部之閘極電極〇〇3設爲d2> 0。 200929540 接著，如第6圖（c)所示般，藉由離子注入及雜質 擴散作成源極區域〇〇1及汲極區域002。假設成爲dl < d2 ，於源極區域001及汲極區域002和通道部分離之時，若 藉由實施傾斜離子注入，如第7圖所示般形成源極及汲極 區域即可。在此，第7圖爲第1圖（a)之線2B-2B’之剖 面圖。最後，在第6圖（c)所示之構造表面形成鈍化膜 ，在源極、閘極、汲極部作成接觸孔，取出各個電極而完 〇 成。在上述實施例中，當然可以藉由使導電型反轉而同樣 作成P通道型MOS構造，若使用雙阱手法時，也容易實 施以1晶片作成具有高驅動能力之CMOS構造，或1C混 載。以上爲本發明之基本構造及基本製造法。 自此針對上述基本構造之應用予以敘述。In order to compromise the miniaturization and withstand voltage, various components have been proposed so far. In the current mainstream configuration, when a Power MOS FET having a high withstand voltage and a high drive chamber I force is taken as an example, the case can be cited. Ditch gate MOS. The trench gate MOS is also the highest in the DMOS with high withstand voltage and high driving capability. However, the trench gate MOS is a vertical MOS structure in which a current flows in the depth direction of the substrate, and although it has excellent performance as a component alone, it is disadvantageous to crystallizing with 1C. When considering the crystallization with 1C, the conventional lateral MOS structure has to be selected. In order to reduce the withstand voltage and reduce the on-resistance per unit area, it is proposed to obtain the gate width of the gate width by setting the gate portion as a trench structure having a convex portion and a concave portion. Crystals (for example, refer to Patent Documents 1 to 3). Fig. 4 is a view showing a conventional technique. Here, -4-200929540 Fig. 4(a) is a plan view, Fig. 4(b) is a cross-sectional view of line 4B-4B', and Fig. 4(c) is a cross-sectional view along line 4C-4C', Fig. 4(d) is a cross-sectional view taken along line 4D-4D' of (a). The lateral trench gate-type electro-crystal system is composed of a plurality of trenches arranged in parallel with the channel direction of the transistor, and the above-mentioned electro-crystalline system is disposed on a p-type well provided on the surface of the n-type or p-type high-resistance semiconductor substrate 006. a region 005; and a recess 008 defined by the trench and a ridge portion 007 located on both sides of the recess; and a gate insulating film 004 disposed on the surface of the recess and the protrusion; and a recessed portion and disposed in the convex portion The gate electrode 〇〇3 on the gate insulating film of the portion; and the source region 001 and the drain region 002 disposed on the surface of the well region sandwiching both sides of the gate electrode in combination with the trench. Here, in Fig. 4(a), in order to facilitate the viewing of the pattern, the gate electrode 〇〇3 and the gate insulating film 004 outside the trench are made transparent. The thick line indicates the edge of the gate electrode 003. By setting the gate portion to the trench structure, the technique of reducing the on-resistance for widening the gate width per unit area of the lateral MOS is employed. The dotted line 〇 1 9 in Fig. 表示 indicates the path of the current flowing into the transistor. [Patent Document 1] Japanese Patent Laid-Open Publication No. Hei. No. Hei. No. 2006-294645 (Patent Document 3). The above composition has a problem. Generally, when MOS is used, in order to enhance the oxide film quality, the Si surface is used on the surface of the wafer {100}' -5-200929540, and the crystal orientation of the crystal orientation (OF) is highly utilized by the carrier [110]. The source and drain of the M0S are set to be perpendicular or parallel to the OF. However, in the above configuration, the same wafer is used, and as shown in FIG. 14(a), when the trench is set to be perpendicular or horizontal to the OF, the Si surface of the {1 1 0} is exposed on the side of the trench, The surface of the gate becomes the gate surface, and the gate oxide film is deteriorated. Furthermore, as shown in Fig. 14(b), since the gate surface of the upper and lower sides of the trench is parallel to the surface of the substrate, it is solidified as the Si surface of {100}, and the other crystal surface is opposite to the side of the trench to become the gate surface. . In general, the growth state of the oxide film differs due to the crystal face, so the gate oxide film thickness on the side of the trench (dv in Fig. 14(c)) and the gate oxide film thickness on the bottom surface and the top of the trench (Fig. 14) (c) of dH) is different in thickness. In the case of the formation, since the gate oxide film is grown by the thin gate oxide film having the desired withstand voltage, the driving ability of the thick gate oxide film region is lowered, and the device cannot be made efficient. ϋ (Means for Solving the Problem) The semiconductor device is configured to have a well region of a high-resistance Ρ-type semiconductor having a certain depth from an n-type or p-type semiconductor substrate surface, and from the surface of the well region to the above The depth of the semiconductor substrate is parallel to a plurality of trenches in the direction connecting the source and the drain, and a gate insulating film provided on the surface of the uneven portion formed by the trench, and a gate buried in the trench The electrode electrode, which constitutes the uneven portion of the trench, has a crystal surface {100}. 200929540 [Effect of the Invention] Compared with, for example, the top surface of the trench and the bottom surface of the trench are {110}, the surface of the trench is {110}, and the MOS of the majority of the crystal surface is used. The V10S of the present invention is formed by crystallizing all the semiconductor surfaces of the trench. Face {100}, so as to enhance the oxidized film quality, and enhance the reliability of MOS, and can make the oxide film thinner, thereby improving the driving ability. Furthermore, since only the {100} crystal plane is used for the gate surface, the uniformity of the gate oxide film thickness is good, and the driving ability is improved. [Embodiment] Fig. 1 shows a lateral MOS transistor of a representative embodiment of the present invention. Here, Fig. 1(a) is a plan view, and Fig. 1(b) is a bird's eye view of (a). The same components are assigned to the components corresponding to the prior art shown in Fig. 4. In Fig. 1(a), in order to facilitate viewing of the figure, the gate electrode 〇 3 and the gate insulating film 〇 4 outside the trench are made transparent. The thick line table shows the edge of the gate electrode 003. Here, the axis indicating the plane of the face is displayed on each drawing. In this way, the crystal surface {1 0 0 } is used on the top, bottom surface and side surface of the trench, thereby improving the oxide film quality of the gate, and obtaining the uniformity of the gate oxide film thickness, thereby improving the reliability and the driving ability. One method for using the crystal face {1 0 0 } on the top, bottom, and side of the trench is as shown in Fig. 15(a), and the surface of the wafer is not {100}OF is [11〇]' Use the wafer of [100]. The second method is as shown in Figure (b). If the 45° is tilted to the wafer with a {100} OF [1 1 0] wafer, the trench can be patterned. 200929540 In addition, Fig. 2(a) is a cross-sectional view taken along line 2A-2A' of Fig. 1(a), and Fig. 2(b) is a cross-sectional view taken along line 2B_2B' of Fig. 1(a), 3rd Fig. (a) is a cross-sectional view taken along line 3A-3A' of Fig. 1(a), and Fig. 3(b) is a cross-sectional view taken along line 3B-3B' of Fig. 1(a). In the conventional example shown in Fig. 4, the gate electrode 003 covers the entire trench portion, but in the present invention shown in Figs. 1 to 3, the vicinity of both ends of the trench is not covered by the gate electrode 003. The composition. In such a configuration, the contact area between the source and drain regions and the channel can be increased by increasing the maximum 13 (12 becomes larger). Next, the manufacturing method will be described. Fig. 6 is an example of the manufacturing method of the present invention. As shown in Fig. 6(a), an n-type or p-type high resistance semiconductor substrate 〇〇6 having a well region 005 formed in the vicinity of the surface forms a plurality of trenches. Here, when the depth of the trench is made deeper than the depth of the well region 005, the leakage current flows into the substrate, so that the depth of the trench cannot be easily deepened, but can be derived from the trench region as shown in Fig. 10(a). The oblique ion implantation in the multi-direction of the post © is performed, and ion implantation for forming the well region 005 is performed to make the trench depth deeper. This is because the ions are implanted on the side of the trench and the trench by the left and right oblique ion implantation 017, and ions are implanted on the top and bottom of the trench by oblique ion implantation from the front and the rear of the figure, according to the subsequent heat diffusion. As shown in Figure 10(b), it forms deeper than the bottom of the trench. By using this method, it is possible to form a deep trench more reliably than the method of forming the trench region after the well region 005 is formed, and the gate width per unit area can be increased. However, in the above method, the depth of the trench is also limited. When the tilting angle is not changed - 200929540 The angle of the oblique injection is 0. If the depth of the trench is simply deepened, as shown in Fig. 1 (a), the portion of the trench at the bottom of the trench is not implanted with ions, even if thermal diffusion is performed. Also, as shown in Fig. 11(b), the well region 005 does not surround the entire trench. In addition, when the oblique ion implantation angle is reduced by implanting ions on the side of the trench in the bottom region of the trench, as shown in Fig. 12, the side of the trench is not sufficiently implanted, and the ion concentration of the well after thermal diffusion is Not necessarily. 〇 However, by combining the above-described oblique ion implantation and epitaxial techniques, the depth of the trench can be deepened above the above limit. As shown in Fig. 13(a), a region 016 to which ion implantation is applied is formed on the surface of the semiconductor substrate 060 so as to have the same conductivity type as that of the well. Thereafter, as shown in Fig. 13(b), the semiconductor film is deposited by epitaxial growth. Thereafter, a trench structure is formed as shown in Fig. 13 (c), and oblique ion implantation in multiple directions is performed as shown in Fig. 13 (d). Since the ion implantation layer exists between the epitaxial layer and the semiconductor substrate, by applying thermal diffusion, as shown in Fig. 13(e), a well surrounding the entire trench can be formed. By this method, the depth of the trench can be deeper, and the gate width per unit area can be increased. Next, as shown in FIG. 6(b), the gate insulating film 004 and the gate electrode film 003 are sequentially formed on the surface of the substrate, and only the gate electrode film 003 on the region serving as the channel remains, and is etched. Other gate electrode film 003. At this time, by reducing the area of the contact portion 020 between the source and drain regions and the channel as shown in FIG. 5, the upper end of the trench at the length 13 is also etched back without hindering the decrease in the on-resistance. The gate electrode 〇〇3 is buried, and the gate electrode 〇〇3 buried inside the trench is set to d2 > 200929540 Next, as shown in Fig. 6(c), the source region 〇〇1 and the drain region 002 are formed by ion implantation and impurity diffusion. If dl < d2 is assumed, when the source region 001 and the drain region 002 are separated from the channel portion, the source and drain regions may be formed as shown in Fig. 7 by performing oblique ion implantation. Here, Fig. 7 is a cross-sectional view taken along line 2B-2B' of Fig. 1(a). Finally, a passivation film is formed on the surface of the structure shown in Fig. 6(c), and contact holes are formed in the source, gate, and drain portions, and the respective electrodes are taken out and completed. In the above embodiment, of course, the P-channel MOS structure can be similarly formed by inverting the conductivity type. When the double-well method is used, it is also easy to implement a CMOS structure having high driving capability with 1 wafer or 1C hybrid. The above is the basic structure and basic manufacturing method of the present invention. Since then, the application of the above basic structure has been described.

在通常之平面型MOS中，爲了提高耐壓，以基本構 造爲基準，存在各種構造。即使關於本發明，因也相同以 基本構造（第1圖）爲基準，可合倂第8圖所示之DDD © ( Double Diffused Drain)構造，或第 9 圖所示之 LDMOS (Lateral Double diffused MOS )構造等之以往技術，故 容易謀求提高耐壓。 再者，藉由將第1圖所示之凸部 00 7之寬度設爲 1000A左右，於MOS成爲接通（ON)狀態之時，凸部內 部所有呈現空乏化，提高次臨限特性。因此，減少源極、 汲極間之洩漏，可降低臨限値，其結果可更提高驅動能力 〇 以上，雖然說明本發明之實施型態，但是本發明並不 -10- 200929540 限定於上述實施型態’本發明可在不脫離其主旨之範圍下 加以變形而實施。 〔產業上之利用可行性〕 本發明所涉及之具有高驅動能力之半導體裝置可以廣 泛使用於驅動較多電流所需之1C或是LSI等之半導體積 體電路。 〇 【圖式簡單說明】 第1圖爲表示本發明之基本構造之圖式。（a)爲平 面圖。（b )爲鳥瞰圖。 第2圖爲第1圖（a)之剖面圖，（a)爲線2A-2A’ 之剖面圖。（b )爲線2 B - 2 B ’之剖面圖。 第3圖爲第1圖（a)之剖面圖。（b)爲線3A-3A’ 之剖面圖。（b )爲線3B-3B’之剖面圖。 Ο 第4圖爲表示先行技術之實施例。（a)爲平面圖。 (b )爲第4圖（a )之線4B-4B’之剖面圖。（c )爲第4 圖（a)之線4C-4C’之剖面圖。（d)爲第4圖（a)之線 4D-4D’之剖面圖。 第5圖爲第4圖之源極區域001或是汲極區域〇〇2之 鳥瞰圖。 第6圖爲表示本發明之製造工程之鳥瞰圖。 第7圖爲dl<d2之時之第1圖（a)之線2B-2B’之 剖面圖。 -11 - 200929540 第8圖爲具有DDD構造之本發明之鳥瞰圖。 第9圖爲具有LDMOS構造之本發明之鳥瞰圖。 第10圖爲溝渠深度爲比較淺之時之剖面圖。（a)爲 多方向傾斜離子注入之後的剖面圖。（b )爲另一方高傾 斜離子注入後，使離子熱擴散之剖面圖。 第11圖爲溝渠深度爲深離子注入角度0大之時的剖 面圖。（a )爲多方向傾斜離子注入之後的剖面圖。（b ) 〇 爲另一方高傾斜離子注入後，使離子熱擴散之剖面圖。 第12圖爲溝渠深度爲深離子注入角度0小之離子注 入後的剖面圖。 第1 3圖爲使用磊晶技術和傾斜離子注入法之阱之作 成法。（a)爲對半導體基板表面施予離子注入之剖面圖 。（b)爲藉由磊晶生長法在第13圖（a)之基板表面形 成半導體膜之剖面圖。（c)爲在第13圖（b)形成溝渠 構造之剖面圖。（d)爲對第13圖（c)施予多方向離子 ❹ 注入之剖面圖。（e)爲對第13圖（d)施予熱擴散之剖 面圖。 第14圖爲表示先行技術之溝渠佈置及其溝渠剖面圖 。（a)爲晶圓之平面圖。（b )爲線3A-3A’（ 3B-3B’） 之剖面圖。（c)爲對同圖（b)施予熱氧化之圖式。 第15圖爲表示本發明之溝渠佈置圖。（a)爲使用晶 圓表面{100}、〇F[100]之情形。（a)爲使用晶圓表面 {100}、OF[l 10]之情形。 -12- 200929540 【主要元件符號說明】 0 0 1 :源極區域 0 0 2 :汲極區域 0 0 3 :閘極電極 004 :閘極絕緣膜 0 0 5 :拼區域 〇〇6 :高電阻半導體基板 Ο 007 :凸部 0 0 8 :凹部 009 :高電阻η型半導體區域 010:高電阻η型半導體基板 016:施予離子注入使成爲與阱相同之導電型的區域 017:離子注入之方向 018:藉由磊晶生長之半導體膜 〇 1 9 :電流路徑 Ο 020 :與通道部接觸之部分 021 :溝渠圖案 022 :晶圓 -13-In the conventional planar MOS, in order to increase the withstand voltage, various structures exist based on the basic structure. Even in the present invention, the DDD © ( Double Diffused Drain) structure shown in Fig. 8 or the LDMOS (Lateral Double diffused MOS shown in Fig. 9) can be combined with the basic structure (Fig. 1). In the prior art such as the structure, it is easy to increase the withstand voltage. Further, when the width of the convex portion 00 7 shown in Fig. 1 is set to about 1000 A, when the MOS is turned on (ON), all the inside of the convex portion is depleted, and the secondary threshold characteristic is improved. Therefore, the leakage between the source and the drain can be reduced, and the threshold can be reduced. As a result, the driving ability can be further improved. Although the embodiment of the present invention is described, the present invention is not limited to the above-mentioned implementation. The invention may be practiced without departing from the spirit and scope of the invention. [Industrial Applicability] The semiconductor device having high driving capability according to the present invention can be widely used for a semiconductor integrated circuit such as 1C or LSI which is required to drive a large amount of current. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing the basic structure of the present invention. (a) is a plan view. (b) is a bird's eye view. Fig. 2 is a cross-sectional view of Fig. 1(a), and Fig. 2(a) is a cross-sectional view of line 2A-2A'. (b) is a cross-sectional view of line 2 B - 2 B '. Fig. 3 is a cross-sectional view of Fig. 1(a). (b) is a cross-sectional view of the line 3A-3A'. (b) is a cross-sectional view of the line 3B-3B'. Ο Figure 4 shows an embodiment of the prior art. (a) is a plan view. (b) is a cross-sectional view taken along line 4B-4B' of Fig. 4(a). (c) is a cross-sectional view taken along line 4C-4C' of Fig. 4(a). (d) is a cross-sectional view of the line 4D-4D' of Fig. 4(a). Figure 5 is a bird's eye view of the source region 001 or the drain region 〇〇2 of Fig. 4. Figure 6 is a bird's eye view showing the manufacturing process of the present invention. Fig. 7 is a cross-sectional view taken along line 2B-2B' of Fig. 1(a) at the time of dl<d2. -11 - 200929540 Figure 8 is a bird's eye view of the present invention having a DDD configuration. Figure 9 is a bird's eye view of the present invention having an LDMOS configuration. Figure 10 is a cross-sectional view of the trench when the depth is relatively shallow. (a) is a cross-sectional view after multi-directional oblique ion implantation. (b) A cross-sectional view of the ion which is thermally diffused after the other high-inclined ion implantation. Figure 11 is a cross-sectional view showing the depth of the trench as a deep ion implantation angle of 0. (a) is a cross-sectional view after oblique ion implantation in multiple directions. (b) 剖面 A cross-sectional view of the ion that is thermally diffused after the other high-inclined ion implantation. Fig. 12 is a cross-sectional view showing the depth of the trench after ion implantation with a deep ion implantation angle of 0. Fig. 13 is a diagram showing the formation of a well using an epitaxial technique and a tilted ion implantation method. (a) is a cross-sectional view in which ion implantation is applied to the surface of the semiconductor substrate. (b) is a cross-sectional view showing a semiconductor film formed on the surface of the substrate of Fig. 13(a) by an epitaxial growth method. (c) is a cross-sectional view showing the structure of the trench in Fig. 13(b). (d) is a cross-sectional view of the multi-directional ion implantation given to Fig. 13(c). (e) is a cross-sectional view of the heat diffusion of Fig. 13(d). Figure 14 is a diagram showing the trench arrangement of the prior art and its trench profile. (a) is a plan view of the wafer. (b) is a cross-sectional view of the line 3A-3A' (3B-3B'). (c) is a diagram for applying thermal oxidation to the same figure (b). Fig. 15 is a view showing the arrangement of the ditch of the present invention. (a) In the case of using the crystal surface {100}, 〇F[100]. (a) In the case of using the wafer surface {100}, OF[l 10]. -12- 200929540 [Explanation of main component symbols] 0 0 1 : Source region 0 0 2 : Deuterium region 0 0 3 : Gate electrode 004: Gate insulating film 0 0 5: Plot region 〇〇 6: High-resistance semiconductor Substrate Ο 007 : convex portion 0 0 8 : recessed portion 009 : high-resistance n-type semiconductor region 010 : high-resistance n-type semiconductor substrate 016 : ion implantation is performed to make the same conductivity type region as the well 017 : ion implantation direction 018 : Semiconductor film by epitaxial growth 〇1 9 : Current path Ο 020 : Portion in contact with the channel portion 021 : Ditch pattern 022 : Wafer-13-

Claims (1)

200929540 十、申請專利範圍 1. 半導體裝置，其構造具有··被設置成從η型或p型 之半導體基板表面具有一定深度之高電阻ρ型半導體之阱 區域’和從上述阱區域表面至上述半導體基板之途中深度 被平行設置於連結源極和汲極之方向之多數條溝渠，和被 設置在上述溝渠所形成之凹凸部表面之閘極絕緣膜，和被 埋入至上述溝渠內部之閘極電極，構成上述溝渠凹凸部之 〇 所有半導體表面成爲結晶面{ 1 0 0 }。 2. 如申請專利範圍第1項所記載之半導體裝置，其中 ’上述溝渠爲矩形，上述半導體基板係基板表面之面方位 爲{100}，晶向切平邊之方位爲[1〇〇]，上述溝渠係被配置 成各邊對上述晶向切平邊呈平行或垂直。 3 ·如申請專利範圍第1項所記載之半導體裝置，其中 ，上述溝渠爲矩形，上述半導體基板係基板表面之面方位 爲{100}，晶向切平邊之方位爲[110]，上述溝渠係被配置 ® 成各邊對上述晶向切平邊構成45度之角度。 -14-200929540 X. Patent Application Area 1. A semiconductor device having a structure in which a well region of a high-resistance p-type semiconductor having a certain depth from an n-type or p-type semiconductor substrate surface and a surface from the surface of the well region described above The depth of the semiconductor substrate is parallel to a plurality of trenches in the direction connecting the source and the drain, and a gate insulating film provided on the surface of the uneven portion formed by the trench, and a gate buried in the trench The electrode of the electrode, which constitutes the uneven portion of the trench, has a crystal surface {1 0 0 }. 2. The semiconductor device according to claim 1, wherein the trench is rectangular, the surface orientation of the surface of the semiconductor substrate is {100}, and the orientation of the crystal plane is [1〇〇], The above-mentioned ditch system is arranged such that each side is parallel or perpendicular to the flat side of the crystal direction. The semiconductor device according to the first aspect of the invention, wherein the trench is rectangular, the surface orientation of the surface of the semiconductor substrate is {100}, and the orientation of the crystal cut plane is [110], the trench It is configured to form an angle of 45 degrees to the sides of the above-mentioned crystal orientation. -14-
TW97131935A 2007-08-22 2008-08-21 Lateral semiconductor device with high driving capacity using trench structure TW200929540A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007215552A JP2009049260A (en) 2007-08-22 2007-08-22 Lateral semiconductor device with high driving capacity using trench structure

Publications (1)

Publication Number Publication Date
TW200929540A true TW200929540A (en) 2009-07-01

Family

ID=40378207

Family Applications (1)

Application Number Title Priority Date Filing Date
TW97131935A TW200929540A (en) 2007-08-22 2008-08-21 Lateral semiconductor device with high driving capacity using trench structure

Country Status (3)

Country Link
JP (1) JP2009049260A (en)
TW (1) TW200929540A (en)
WO (1) WO2009025308A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6084357B2 (en) * 2011-11-02 2017-02-22 ルネサスエレクトロニクス株式会社 Semiconductor device
JP6726092B2 (en) 2016-12-28 2020-07-22 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
CN117410301A (en) * 2020-03-18 2024-01-16 索尼半导体解决方案公司 Imaging device and electronic equipment

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62126675A (en) * 1985-11-27 1987-06-08 Toshiba Corp Semiconductor device and manufacture thereof
JPS63228710A (en) * 1987-03-18 1988-09-22 Toshiba Corp Semiconductor device
JPS63250852A (en) * 1987-04-08 1988-10-18 Sony Corp Semiconductor device
JPH06209106A (en) * 1993-01-12 1994-07-26 Matsushita Electron Corp Semiconductor device
JPH08264764A (en) * 1995-03-22 1996-10-11 Toshiba Corp Semiconductor device
KR100641365B1 (en) * 2005-09-12 2006-11-01 삼성전자주식회사 Mos transistors having an optimized channel plane orientation, semiconductor devices including the same and methods of fabricating the same

Also Published As

Publication number Publication date
JP2009049260A (en) 2009-03-05
WO2009025308A1 (en) 2009-02-26

Similar Documents

Publication Publication Date Title
JP4976658B2 (en) Manufacturing method of semiconductor device
JP5110776B2 (en) Manufacturing method of semiconductor device
US5701026A (en) Lateral trench MISFET
US9378959B2 (en) Method of manufacturing insulated gate transistor semiconductor device
JP2007300034A (en) Semiconductor device, and its fabrication process
TW200845391A (en) Semiconductor device and method of manufacturing the same
JP2011204808A (en) Semiconductor device and method of manufacturing the same
JP2006019518A (en) Horizontal trench mosfet
JP2013179333A (en) Semiconductor device
JP5486654B2 (en) Semiconductor device
TW201606857A (en) Method of manufacturing semiconductor device
US8088662B2 (en) Fabrication method of trenched metal-oxide-semiconductor device
TWI445171B (en) Semiconductor device and manufacturing method thereof
US8399915B2 (en) Semiconductor device
JP2020136416A (en) Semiconductor device and semiconductor device manufacturing method
TW200929540A (en) Lateral semiconductor device with high driving capacity using trench structure
US20170213909A1 (en) Method for Fabricating a Shallow and Narrow Trench FET
JP2004241768A (en) Semiconductor device
TW200945586A (en) Semiconductor device and method of manufacturing the same
JP2011238899A (en) Method of manufacturing semiconductor device
JP2006332232A (en) Semiconductor device and manufacturing method thereof
JP7508764B2 (en) Super-junction silicon carbide semiconductor device and method for manufacturing the super-junction silicon carbide semiconductor device
JP5486673B2 (en) Semiconductor device
JP2008053468A (en) Lateral semiconductor device with high driving capacity using trench structure
KR100760010B1 (en) Electronic power semiconductor device to be improved change rate of voltage which depends on time