JP5567711B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP5567711B2
JP5567711B2 JP2013096846A JP2013096846A JP5567711B2 JP 5567711 B2 JP5567711 B2 JP 5567711B2 JP 2013096846 A JP2013096846 A JP 2013096846A JP 2013096846 A JP2013096846 A JP 2013096846A JP 5567711 B2 JP5567711 B2 JP 5567711B2
Authority
JP
Japan
Prior art keywords
gate electrode
trench
region
drain region
source region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2013096846A
Other languages
Japanese (ja)
Other versions
JP2013179333A (en
Inventor
雅幸 橋谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2013096846A priority Critical patent/JP5567711B2/en
Publication of JP2013179333A publication Critical patent/JP2013179333A/en
Application granted granted Critical
Publication of JP5567711B2 publication Critical patent/JP5567711B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

本発明は、高駆動能力を要するＭＯＳトランジスタを含む半導体装置に関する。   The present invention relates to a semiconductor device including a MOS transistor that requires high drive capability.

MOSトランジスタは電子技術において中核を担う電子素子であって、MOSトランジスタの小型化と高駆動能力化は、重要である。MOSトランジスタを高駆動能力化する方法の１つとして、ゲート幅を長くしてオン抵抗を低減させる方法があるが、ゲート幅を広くするとMOSトランジスタの占有面積が大きくなるという問題があった。その解決のために、横型MOS構造のMOSトランジスタの専有面積の増加を抑えながらゲート幅を広くする技術が提案されている。（例えば、特許文献１参照）
以下、図４を用いて、従来の半導体装置について説明する。図４（ａ）の斜視図は、ウェル１１にトレンチ構造３を設け、ゲート絶縁膜６を介してトレンチ構造を有するトレンチ部の内部およびトレンチが形成されていないプレーナー部の上面にゲート電極７を形成したものである。ウェル１１の表面部分において、ゲート電極７の一方の側にはソース領域９が設けられており、他方の側にはドレイン領域１０が設けられている。図４（ｂ）は、図４（ａ）のA−A断面図であり、プレーナー部を示している。図４（ｃ）は、図４（ａ）のＢ−Ｂ断面図であり、チャネルに垂直な方向の断面図である。Ｂ−Ｂ断面図に示したように、トレンチ部３の内部にゲート電極７が形成されているため、ゲート電極７の下に位置するゲート絶縁膜６が形成する曲線の長さの総延長がゲート幅となる。 MOS transistors are electronic elements that play a central role in electronic technology, and miniaturization and high drive capability of MOS transistors are important. One method for increasing the driving capability of a MOS transistor is to increase the gate width to reduce the on-resistance. However, if the gate width is increased, there is a problem that the area occupied by the MOS transistor increases. In order to solve this problem, a technique for widening the gate width while suppressing an increase in the area occupied by the MOS transistor having the lateral MOS structure has been proposed. (For example, see Patent Document 1)
Hereinafter, a conventional semiconductor device will be described with reference to FIG. 4A, the trench structure 3 is provided in the well 11, and the gate electrode 7 is provided inside the trench portion having the trench structure via the gate insulating film 6 and on the upper surface of the planar portion where the trench is not formed. Formed. In the surface portion of the well 11, a source region 9 is provided on one side of the gate electrode 7, and a drain region 10 is provided on the other side. FIG. 4B is a cross-sectional view taken along the line AA in FIG. 4A and shows a planar portion. FIG. 4C is a cross-sectional view taken along the line BB in FIG. 4A, and is a cross-sectional view in a direction perpendicular to the channel. As shown in the BB cross-sectional view, since the gate electrode 7 is formed inside the trench portion 3, the total length of the curve formed by the gate insulating film 6 located under the gate electrode 7 is increased. This is the gate width.

このように、この技術では、ゲート部を凸部と凹部を有するトレンチ構造にすることによって、表面でのゲート電極７の長さに対して、実効的なゲート幅の長さを長くすることができ、これによって、MOSトランジスタの耐圧を低下させずに単位面積あたりのオン抵抗を低減することができる。   As described above, in this technique, the effective gate width can be increased with respect to the length of the gate electrode 7 on the surface by forming the gate portion into a trench structure having a convex portion and a concave portion. Thus, the on-resistance per unit area can be reduced without lowering the breakdown voltage of the MOS transistor.

特開２００６−４９８２６号公報JP 2006-49826 A

以上述べた半導体装置の構造では、想定したよりも駆動能力が実際には得られないという問題があった。そして、ゲート長によって、駆動能力が異なり、ゲート長が短くなると、駆動能力が低下する傾向を示すということが分かった。   In the structure of the semiconductor device described above, there has been a problem that the driving ability cannot actually be obtained as expected. It has been found that the driving ability varies depending on the gate length, and that the driving ability tends to decrease as the gate length becomes shorter.

これは、ソースドレイン間に生じたチャネルのうち、図４（ｄ）に示した経路A（トレンチ部３が形成されていないプレーナー部）に電流が多く流れ、ソースとドレインを結ぶ向きであるチャネルに平行なトレンチ部８の側面を流れる経路Bやトレンチ部８の底面を介して流れる経路Cにはあまり電流が流れないことが原因であると推察できる。そのため、ゲート長が短いほど、経路Aに電流が集中するようになり、このことが、ゲート長が短くなると駆動能力が低下する原因であると考えられる。   This is a channel in which a large amount of current flows through the path A shown in FIG. 4D (planar part where the trench part 3 is not formed) among the channels generated between the source and the drain and connects the source and the drain. It can be inferred that the current does not flow so much in the path B flowing through the side surface of the trench portion 8 parallel to the bottom surface and the path C flowing through the bottom surface of the trench portion 8. For this reason, the shorter the gate length, the more the current is concentrated in the path A, which is considered to be the cause of the decrease in driving capability when the gate length is shortened.

本発明の目的は、トレンチ構造を有する半導体装置の駆動能力を向上させることである。   An object of the present invention is to improve the driving capability of a semiconductor device having a trench structure.

上記課題を解決するために、本発明は次の手段を用いた。
（１）第１導電型半導体基板に形成された、トレンチ部とプレーナー部とを交互に有して、ゲート幅方向に断続的に深さが変化するトレンチ構造と、ゲート絶縁膜を介して、前記トレンチ部の内部を充填しているとともに、前記プレーナー部の上面に形成されたゲート電極と、前記ゲート電極の一方の側の前記第１導電型半導体基板に形成された第２導電型のソース領域と、前記ゲート電極の他方の側の前記第１導電型半導体基板に形成された第２導電型のドレイン領域と、前記ソース領域および前記ドレイン領域にはさまれたチャネル領域と、を備えた半導体装置において、
前記ソース領域および前記ドレイン領域は、前記トレンチ部の内部においては前記ゲート電極に対してノンセルフアラインに配置され、前記プレーナー部の上面においては前記ゲート電極に対してセルフアラインに配置されており、
前記ソース領域および前記ドレイン領域において、前記トレンチ部を挟んで向き合う部分は、当該トレンチ構造の上面から底部と同じあるいはそれ以上に達する深さを有し、
前記ソース領域および前記ドレイン領域の表面に配置された前記ゲート絶縁膜の厚さは、前記チャネル領域の表面に配置された前記ゲート絶縁膜の厚さよりも厚いことを特徴とする半導体装置とした。
（２）第１導電型半導体基板と、前記第１導電型半導体基板の表面近傍に離間して配置された第２導電型のソース領域およびドレイン領域と、前記ソース領域および前記ドレイン領域の間に配置された第１のチャネル領域となる平坦なプレーナー部と、前記プレーナー部に沿って配置された、その側面および底面が第２のチャネル領域となる、一定の深さを有するトレンチ部と、前記プレーナー部および前記トレンチ部の表面に設けられたゲート絶縁膜と、前記ゲート絶縁膜の上に設けられたゲート電極と、からなる半導体装置であって、
前記ゲート電極は前記トレンチ部の内部を充填しているとともに、前記プレーナー部の上面に形成され、
前記ソース領域および前記ドレイン領域は、前記トレンチ部の内部においては前記ゲート電極に対してノンセルフアラインに配置され、前記プレーナー部の上面においては前記ゲート電極に対してセルフアラインに配置されており、
前記ソース領域および前記ドレイン領域において、前記トレンチ部を介して向き合う部分の拡散領域の深さは当該トレンチ構造の上面から底部と同じあるいはそれ以上に達する深さを有し、
前記ソース領域および前記ドレイン領域の表面に配置された前記ゲート絶縁膜の厚さは、前記第２のチャネル領域の表面に配置された前記ゲート絶縁膜の厚さよりも厚いことを特徴とする半導体装置とした。 In order to solve the above problems, the present invention uses the following means.
(1) A trench structure that is alternately formed in the first conductivity type semiconductor substrate and has a trench portion and a planar portion, and the depth changes intermittently in the gate width direction, and a gate insulating film, A gate electrode formed on an upper surface of the planar portion and a second conductivity type source formed on the first conductivity type semiconductor substrate on one side of the gate electrode and filling the inside of the trench portion A drain region of a second conductivity type formed in the first conductivity type semiconductor substrate on the other side of the gate electrode, and a channel region sandwiched between the source region and the drain region. In semiconductor devices,
The source region and the drain region are arranged in a non-self-aligned manner with respect to the gate electrode inside the trench portion, and are arranged in a self-aligned manner with respect to the gate electrode on the upper surface of the planar portion,
In the source region and the drain region, the portions facing each other across the trench portion have a depth reaching the same as or more than the bottom portion from the upper surface of the trench structure,
The semiconductor device is characterized in that the thickness of the gate insulating film disposed on the surfaces of the source region and the drain region is thicker than the thickness of the gate insulating film disposed on the surface of the channel region.
(2) A first conductive type semiconductor substrate, a second conductive type source region and drain region that are spaced apart in the vicinity of the surface of the first conductive type semiconductor substrate, and between the source region and the drain region. A flat planar portion serving as a first channel region, a trench portion having a certain depth, the side surface and the bottom surface of which are disposed along the planar portion serving as a second channel region; A semiconductor device comprising: a gate insulating film provided on a surface of the planar part and the trench part; and a gate electrode provided on the gate insulating film,
The gate electrode fills the inside of the trench part and is formed on the upper surface of the planar part,
The source region and the drain region are arranged in a non-self-aligned manner with respect to the gate electrode inside the trench portion, and are arranged in a self-aligned manner with respect to the gate electrode on the upper surface of the planar portion,
In the source region and the drain region, the depth of the diffusion region of the portion facing through the trench portion has a depth reaching the same as or more than the bottom portion from the upper surface of the trench structure,
A thickness of the gate insulating film disposed on the surfaces of the source region and the drain region is greater than a thickness of the gate insulating film disposed on the surface of the second channel region. It was.

本発明によれば、上述の半導体装置のソース領域およびドレイン領域の一部において、ゲート電極形成前のトレンチ部にフォトレジスト膜を塗布しパターニングし、イオン注入をおこなうことでトレンチ部上面から底部にかけて深く拡散させた領域を形成することが可能である。これによって、トレンチ部トランジスタのゲート電極に対して深い位置までソース領域およびドレイン領域が形成されることになるため、ゲート幅方向に断続的に深さが変化する凹部上部への電流集中を緩和させ、電流をトレンチ部側面および底面にも流すことが可能となることから、半導体装置の駆動能力を向上させることが可能となる。   According to the present invention, in a part of the source region and the drain region of the semiconductor device described above, a photoresist film is applied and patterned on the trench portion before forming the gate electrode, and ion implantation is performed so that the trench portion is formed from the top surface to the bottom portion. It is possible to form a deeply diffused region. As a result, since the source region and the drain region are formed to a deep position with respect to the gate electrode of the trench transistor, the current concentration on the upper portion of the recess whose depth changes intermittently in the gate width direction is reduced. Since the current can also flow through the side surface and the bottom surface of the trench portion, the driving capability of the semiconductor device can be improved.

本発明の第１の実施例を示す模式的断面図フローである。It is a typical sectional view flow showing the 1st example of the present invention. 第１の実施例を示す模式的断面図フローにおけるイオン注入工程の模式図である。It is a schematic diagram of the ion implantation process in the schematic cross-sectional view flow showing the first embodiment. 第１の実施例および第２の実施例で得られる半導体装置の断面模式図および平面模式図である。It is the cross-sectional schematic diagram and plane schematic diagram of the semiconductor device obtained by the 1st Example and the 2nd Example. 従来技術とその課題を示す断面図と模式図である。It is sectional drawing and a schematic diagram which show a prior art and its subject. 第３の実施例で得られる半導体装置の平面模式図である。It is a plane schematic diagram of the semiconductor device obtained by the 3rd example.

以下、本発明の実施の形態を図面に基づいて説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１は本発明の半導体装置の製造方法の第１の実施例を示す模式的断面図による工程順のフローである。   FIG. 1 is a flow chart in order of steps according to a schematic cross-sectional view showing a first embodiment of a method of manufacturing a semiconductor device of the present invention.

図１（A）は、第１導電型半導体基板である、例えばホウ素を添加した抵抗率２０Ωcmから３０Ωcmの不純物濃度を有するP型半導体基板１に、LOCOS法により厚膜酸化膜２として、例えば膜厚５００nmから１μmの熱酸化膜を所望の領域に形成したものである。基板の導電型は本発明の本質とは関係ない。続いて図１（B）に示すように、第１導電型半導体基板にトレンチ構造３を例えば数百nmから数μmの深さに形成する。トレンチ構造３を形成する溝状の凹部は一つだけ配置されることもあれば、図面の紙面と垂直方向に平行に並んで複数個配置されることもある。その後、トレンチ構造３の内部を構成する半導体基板表面を含むおよび半導体基板表面に酸化膜４を例えば膜厚数百Åで形成する。   FIG. 1A shows a first oxide semiconductor substrate, for example, a P-type semiconductor substrate 1 having an impurity concentration of 20 Ωcm to 30 Ωcm doped with boron, for example, as a thick oxide film 2 by a LOCOS method. A thermal oxide film having a thickness of 500 nm to 1 μm is formed in a desired region. The conductivity type of the substrate is not related to the essence of the present invention. Subsequently, as shown in FIG. 1B, the trench structure 3 is formed in the first conductivity type semiconductor substrate to a depth of, for example, several hundred nm to several μm. Only one groove-like recess forming the trench structure 3 may be arranged, or a plurality of grooves may be arranged side by side in a direction perpendicular to the drawing sheet. Thereafter, an oxide film 4 is formed with a film thickness of, for example, several hundreds of parts including and on the surface of the semiconductor substrate constituting the inside of the trench structure 3.

その後、図１（C）に示すように、レジスト膜５を塗布し、図１（D）に示すように、ソース領域およびドレイン領域への不純物添加がトレンチ構造３の上面から底面と同じかそれ以上にかけて深く形成できるように、ソース領域およびドレイン領域のレジスト膜５をパターニングして不用部分を除去する。ここでのレジスト膜に替え、窒化膜、多結晶シリコン膜をマスクとしてパターニングすることも可能である。その後、図１（E）に示すように不純物として、例えば砒素を好ましくは１×１０13atoms/cm2から１×１０16atoms/cm2のドーズ量でウェハをスピン(回転)させながらイオン注入をおこなう。 After that, as shown in FIG. 1C, a resist film 5 is applied, and as shown in FIG. 1D, the impurity addition to the source region and the drain region is the same as the top surface to the bottom surface of the trench structure 3. The resist film 5 in the source and drain regions is patterned to remove unnecessary portions so that it can be formed deeply as described above. Instead of the resist film here, it is also possible to perform patterning using a nitride film or a polycrystalline silicon film as a mask. Thereafter, as shown in FIG. 1E, as the impurity, for example, arsenic is preferably ion-implanted while spinning (rotating) the wafer at a dose of 1 × 10 13 atoms / cm 2 to 1 × 10 16 atoms / cm 2. To do.

この工程については図２を用いて詳細に説明する。図２は図１（E）のトレンチ構造内へのイオン注入工程を示す模式図であり、図２（A）はソース領域側を示し、図２（B）は、図２（Ａ）に対しウェハを１８０°回転させた時のドレイン領域側を示すものである。図２（A）に示すように、トレンチ構造３の側面から底面に不純物添加され、このウェハをスピン（回転）させながら、低角度のイオン注入入射角度でのイオン注入をおこなうので、図２（B）に示すように、ソース領域側であるレジスト膜５の反対側に位置するドレイン領域にも側面から底部に不純物添加が可能となる。さらに、図１（E）を上から見た図が図３（A）であり、図１（E）は図３（A）に示すA-A部の断面図となっている。その後、レジスト膜５および酸化膜４を除去する。   This process will be described in detail with reference to FIG. 2A and 2B are schematic views showing an ion implantation process into the trench structure of FIG. 1E, FIG. 2A shows the source region side, and FIG. It shows the drain region side when the wafer is rotated 180 °. As shown in FIG. 2A, impurities are added from the side surface to the bottom surface of the trench structure 3, and while the wafer is spun (rotated), ion implantation is performed at a low ion implantation incident angle. As shown in B), impurities can be added from the side to the bottom of the drain region located on the opposite side of the resist film 5 on the source region side. Further, FIG. 3A is a top view of FIG. 1E, and FIG. 1E is a cross-sectional view of the AA portion shown in FIG. Thereafter, the resist film 5 and the oxide film 4 are removed.

次に、図１（F）に示すように、ゲート絶縁膜６を、例えば膜厚十〜数百ｎｍの熱酸化膜で形成した後、ゲート絶縁膜６上に多結晶シリコンゲート膜を好ましくは膜厚を１００nm〜５００nm堆積し、プリデポジションあるいはイオン注入法により不純物を導入してゲート電極７とする。ここで、熱酸化膜であるゲート絶縁膜６を形成するのに同じくして、イオン注入により添加した不純物の拡散および活性化をおこなう。この工程で、拡散したソース領域９およびドレイン領域１０の双方は、トレンチ構造３の上面から底部と同じかそれ以上にかけて深い位置に拡散する。さらにここでは、上述のイオン注入による不純物添加が高濃度の場合、ソース領域９およびドレイン領域１０のそれぞれの表面において熱酸化膜が厚くなることから、自動的にゲートとドレイン間での容量を低減することが可能である。   Next, as shown in FIG. 1F, after forming the gate insulating film 6 with a thermal oxide film having a film thickness of, for example, 10 to several hundred nm, a polycrystalline silicon gate film is preferably formed on the gate insulating film 6. A film thickness of 100 nm to 500 nm is deposited, and an impurity is introduced by predeposition or ion implantation to form a gate electrode 7. Here, the impurity added by ion implantation is diffused and activated in the same manner as the formation of the gate insulating film 6 which is a thermal oxide film. In this step, both the diffused source region 9 and drain region 10 diffuse to a deep position from the top surface of the trench structure 3 to the same as or more than the bottom portion. Further, here, when the impurity addition by the above-described ion implantation is high concentration, the thermal oxide film becomes thick on the surface of each of the source region 9 and the drain region 10, so that the capacity between the gate and the drain is automatically reduced. Is possible.

一方で、レジスト膜８でゲート電極１０のパターニングをおこなうことで図１（G）に示すような構造が整う。引き続き、図１（G）に示すように、ゲート電極１０に対しセルフアライン法でソース領域およびドレイン領域を形成するための不純物添加を行う。ソース領域およびドレイン領域の不純物添加は例えば砒素を好ましくは１×１０15atoms/cm2から１×１０16atoms/cm2のドーズ量でイオン注入する。この工程までで、トレンチ構造３を有するMOSトランジスタの形態が整う。その後、８００℃〜１０００℃で数時間熱処理することで、図１（H）に示すように、ソース領域９およびドレイン領域１０を形成する。 On the other hand, by patterning the gate electrode 10 with the resist film 8, the structure as shown in FIG. Subsequently, as shown in FIG. 1G, impurities are added to the gate electrode 10 for forming a source region and a drain region by a self-alignment method. For example, arsenic is preferably ion-implanted at a dose of 1 × 10 15 atoms / cm 2 to 1 × 10 16 atoms / cm 2 . Up to this step, the form of the MOS transistor having the trench structure 3 is completed. After that, heat treatment is performed at 800 ° C. to 1000 ° C. for several hours, so that the source region 9 and the drain region 10 are formed as illustrated in FIG.

また、第２の実施例として、上述したようなトレンチ構造３の上面から底部と同じかそれ以上にかけて深く形成するためのソース領域９およびドレイン領域１０の不純物添加を、ゲート絶縁膜６を形成後におこなうことが可能である。   Further, as the second embodiment, the impurity addition of the source region 9 and the drain region 10 for forming deeply from the top surface to the bottom of the trench structure 3 as described above or after the gate insulating film 6 is formed. It is possible to do.

上述までの第１の実施例あるいは第２の実施例で得られる半導体装置の平面図は図３（B）に示すとおりである。図３（B）のA-A断面図を図３（C）に、図３（B）のＢ−Ｂ断面図を図３（D）にそれぞれ示す。図３（C）より、トレンチ構造３を有するトレンチ部トランジスタ１２において、ゲート電極７付近のソース領域９およびドレイン領域１０においてトレンチ構造３の上面から底部と同じかそれ以上深くにかけて形成し、一方で、図３（D）からは、プレーナー部トランジスタ１３ではゲート電極７付近においてもソース領域９およびドレイン領域１０の全域において同程度の深さになるように形成させる。   A plan view of the semiconductor device obtained in the first embodiment or the second embodiment up to the above is as shown in FIG. 3A is a cross-sectional view taken along the line AA in FIG. 3B, and FIG. 3D is a cross-sectional view taken along the line BB in FIG. 3C, in the trench transistor 12 having the trench structure 3, the source region 9 and the drain region 10 near the gate electrode 7 are formed from the top surface of the trench structure 3 to the same or deeper than the bottom portion, From FIG. 3D, the planar transistor 13 is formed to have the same depth in the entire source region 9 and drain region 10 even in the vicinity of the gate electrode 7.

図５は、第３の実施例で得られる半導体装置の平面模式図である。図３（Ｂ）と異なる点はソース領域およびドレイン領域表面のコンタクトの位置である。図３（Ｂ）ではトレンチ部コンタクトとプレーナー部コンタクトが一列に並んで配置されているが、本実施例ではプレーナー部コンタクト１５は寄生抵抗などを小さくするためにゲート電極７からの距離をトレンチ部コンタクト１４とゲート電極との距離よりも短くした。   FIG. 5 is a schematic plan view of the semiconductor device obtained in the third embodiment. The difference from FIG. 3B is the position of the contact on the surface of the source region and drain region. In FIG. 3B, the trench contact and the planar contact are arranged in a line, but in this embodiment, the planar contact 15 has a distance from the gate electrode 7 to reduce the parasitic resistance. The distance was shorter than the distance between the contact 14 and the gate electrode.

以上のように、本発明においては、トレンチ構造を有するトレンチ部トランジスタ１２においてトレンチ部３の上面から底部と同じかそれ以上にかけて深くすることで、ゲート幅方向に断続的に深さが変化する凹部上部への電流集中を緩和させ、電流をトレンチ部側面および底面にも流すことが可能となり、半導体装置の駆動能力を向上させることが可能となる。   As described above, in the present invention, in the trench transistor 12 having a trench structure, the depth is intermittently changed in the gate width direction by deepening from the top surface of the trench portion 3 to the same as or more than the bottom portion. Current concentration on the upper part can be alleviated, and the current can be allowed to flow also to the side and bottom surfaces of the trench part, so that the driving capability of the semiconductor device can be improved.

１ 半導体基板
２、４ 酸化膜
３ トレンチ構造
５、８ レジスト膜
６ ゲート絶縁膜
７ ゲート電極
９ ソース領域
１０ ドレイン領域
１１ ウェル
１２ トレンチ部トランジスタ
１３ プレーナー部トランジスタ
１４ トレンチ部コンタクト
１５ プレーナー部コンタクト DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2, 4 Oxide film 3 Trench structure 5, 8 Resist film 6 Gate insulating film 7 Gate electrode 9 Source region 10 Drain region 11 Well 12 Trench part transistor 13 Planar part transistor 14 Trench part contact 15 Planar part contact

Claims (2)

第１導電型半導体基板に形成された、トレンチ部とプレーナー部とを交互に有して、ゲート幅方向に断続的に深さが変化するトレンチ構造と、
ゲート絶縁膜を介して、前記トレンチ部の内部を充填しているとともに、前記プレーナー部の上面に形成されたゲート電極と、
前記ゲート電極の一方の側の前記第１導電型半導体基板に形成された第２導電型のソース領域と、
前記ゲート電極の他方の側の前記第１導電型半導体基板に形成された第２導電型のドレイン領域と、
前記ソース領域および前記ドレイン領域にはさまれたチャネル領域と、
を備えた半導体装置において、
前記ソース領域および前記ドレイン領域は、前記トレンチ部の内部においては前記ゲート電極に対してノンセルフアラインに配置され、前記プレーナー部の上面においては前記ゲート電極に対してセルフアラインに配置されており、
前記ソース領域および前記ドレイン領域において、前記トレンチ部を挟んで向き合う部分は、当該トレンチ構造の上面から底部と同じあるいはそれ以上に達する深さを有し、
前記ゲート絶縁膜と同時に前記ソース領域および前記ドレイン領域の表面に配置された熱酸化膜の厚さは、前記チャネル領域の表面に配置された前記ゲート絶縁膜の厚さよりも厚く、
前記プレーナー部の前記ソース領域および前記ドレイン領域表面のコンタクトと前記ゲート電極との距離は、前記トレンチ部の前記ソース領域および前記ドレイン領域表面のコンタクトと前記ゲート電極との距離よりも短いことを特徴とする半導体装置。 A trench structure formed in the first conductivity type semiconductor substrate, having alternately trench portions and planar portions, the depth of which is intermittently changed in the gate width direction;
A gate electrode is formed on the upper surface of the planar portion while filling the inside of the trench portion via a gate insulating film,
A second conductivity type source region formed on the first conductivity type semiconductor substrate on one side of the gate electrode;
A drain region of a second conductivity type formed in the first conductivity type semiconductor substrate on the other side of the gate electrode;
A channel region sandwiched between the source region and the drain region;
In a semiconductor device comprising:
The source region and the drain region are arranged in a non-self-aligned manner with respect to the gate electrode inside the trench portion, and are arranged in a self-aligned manner with respect to the gate electrode on the upper surface of the planar portion,
In the source region and the drain region, the portions facing each other across the trench portion have a depth reaching the same as or more than the bottom portion from the upper surface of the trench structure,
The thickness of the gate insulating film and disposed on the source region and the surface of the drain region at the same time a thermal oxide film, rather thick than the thickness of the gate insulating film disposed on a surface of the channel region,
The source region and the distance between the contact and the gate electrode of the drain region surface of the planar portion, the short Ikoto than the distance between the contact and the gate electrode of the source region and the drain region surface of the trench portion A featured semiconductor device. 第１導電型半導体基板と、
前記第１導電型半導体基板の表面近傍に離間して配置された第２導電型のソース領域およびドレイン領域と、
前記ソース領域および前記ドレイン領域の間に配置された第１のチャネル領域となる平坦なプレーナー部と、
前記プレーナー部に沿って配置された、その側面および底面が第２のチャネル領域となる、一定の深さを有するトレンチ部と、
前記プレーナー部および前記トレンチ部の表面に設けられたゲート絶縁膜と、
前記ゲート絶縁膜の上に設けられたゲート電極と、からなる半導体装置であって、
前記ゲート電極は前記トレンチ部の内部を充填しているとともに、前記プレーナー部の上面に形成され、
前記ソース領域および前記ドレイン領域は、前記トレンチ部の内部においては前記ゲート電極に対してノンセルフアラインに配置され、前記プレーナー部の上面においては前記ゲート電極に対してセルフアラインに配置されており、
前記ソース領域および前記ドレイン領域において、前記トレンチ部を介して向き合う部分の拡散領域の深さは当該トレンチ構造の上面から底部と同じあるいはそれ以上に達する深さを有し、
前記ゲート絶縁膜と同時に前記ソース領域および前記ドレイン領域の表面に配置された熱酸化膜の厚さは、前記第２のチャネル領域の表面に配置された前記ゲート絶縁膜の厚さよりも厚く、
前記プレーナー部の前記ソース領域および前記ドレイン領域表面のコンタクトと前記ゲート電極との距離は、前記トレンチ部の前記ソース領域および前記ドレイン領域表面のコンタクトと前記ゲート電極との距離よりも短いことを特徴とする半導体装置。 A first conductivity type semiconductor substrate;
A source region and a drain region of a second conductivity type that are spaced apart in the vicinity of the surface of the first conductivity type semiconductor substrate;
A flat planar portion serving as a first channel region disposed between the source region and the drain region;
A trench portion having a certain depth, the side surface and the bottom surface of which are arranged along the planar portion, and which serve as a second channel region;
A gate insulating film provided on the surfaces of the planar part and the trench part;
A semiconductor device comprising a gate electrode provided on the gate insulating film,
The gate electrode fills the inside of the trench part and is formed on the upper surface of the planar part,
The source region and the drain region are arranged in a non-self-aligned manner with respect to the gate electrode inside the trench portion, and are arranged in a self-aligned manner with respect to the gate electrode on the upper surface of the planar portion,
In the source region and the drain region, the depth of the diffusion region of the portion facing through the trench portion has a depth reaching the same as or more than the bottom portion from the upper surface of the trench structure,
The thickness of the gate insulating film at the same time as the source region and the thermal oxide film disposed on a surface of said drain region, rather thick than the thickness of the gate insulating film disposed on a surface of the second channel region,
The source region and the distance between the contact and the gate electrode of the drain region surface of the planar portion, the short Ikoto than the distance between the contact and the gate electrode of the source region and the drain region surface of the trench portion A featured semiconductor device.
JP2013096846A 2007-07-27 2013-05-02 Semiconductor device Expired - Fee Related JP5567711B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013096846A JP5567711B2 (en) 2007-07-27 2013-05-02 Semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007195493 2007-07-27
JP2007195493 2007-07-27
JP2013096846A JP5567711B2 (en) 2007-07-27 2013-05-02 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2008174498A Division JP5314949B2 (en) 2007-07-27 2008-07-03 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2013179333A JP2013179333A (en) 2013-09-09
JP5567711B2 true JP5567711B2 (en) 2014-08-06

Family

ID=40307796

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2008174498A Expired - Fee Related JP5314949B2 (en) 2007-07-27 2008-07-03 Manufacturing method of semiconductor device
JP2013096846A Expired - Fee Related JP5567711B2 (en) 2007-07-27 2013-05-02 Semiconductor device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2008174498A Expired - Fee Related JP5314949B2 (en) 2007-07-27 2008-07-03 Manufacturing method of semiconductor device

Country Status (4)

Country Link
JP (2) JP5314949B2 (en)
KR (1) KR101546537B1 (en)
CN (1) CN101355104B (en)
TW (1) TWI445094B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5378925B2 (en) 2009-09-24 2013-12-25 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP5498107B2 (en) 2009-09-24 2014-05-21 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US8558320B2 (en) * 2009-12-15 2013-10-15 Qualcomm Incorporated Systems and methods employing a physically asymmetric semiconductor device having symmetrical electrical behavior
JP2012204799A (en) * 2011-03-28 2012-10-22 Toshiba Corp Semiconductor memory device and method of manufacturing the same
CN103280455B (en) * 2013-04-28 2016-05-18 苏州市职业大学 Horizontal proliferation type low on-resistance MOS device
CN104465726B (en) * 2013-09-17 2017-08-11 世界先进积体电路股份有限公司 Semiconductor device and its manufacture method
US9773902B2 (en) 2013-11-25 2017-09-26 Vanguard International Semiconductor Corporation Trench-gate semiconductor device and method for forming the same
JP2019016668A (en) * 2017-07-05 2019-01-31 三菱電機株式会社 Silicon carbide semiconductor device and manufacturing method of the same, and power conversion device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770713B2 (en) * 1987-02-12 1995-07-31 松下電器産業株式会社 MOS semiconductor device and manufacturing method thereof
JPH0223670A (en) * 1988-07-12 1990-01-25 Seiko Epson Corp Semiconductor device
JPH02134871A (en) * 1988-11-15 1990-05-23 Mitsubishi Electric Corp Semiconductor device
JPH02166771A (en) * 1988-12-20 1990-06-27 Ricoh Co Ltd Semiconductor integrated circuit device
JPH033272A (en) * 1989-05-30 1991-01-09 Mitsubishi Electric Corp Semiconductor device
JPH0575121A (en) * 1991-09-18 1993-03-26 Fujitsu Ltd Semiconductor device
JPH05160401A (en) * 1991-12-05 1993-06-25 Sharp Corp Mos transistor
JPH08264764A (en) * 1995-03-22 1996-10-11 Toshiba Corp Semiconductor device
US6100146A (en) * 1996-10-30 2000-08-08 Advanced Micro Devices, Inc. Method of forming trench transistor with insulative spacers
US6956263B1 (en) * 1999-12-28 2005-10-18 Intel Corporation Field effect transistor structure with self-aligned raised source/drain extensions
JP4031677B2 (en) * 2002-07-05 2008-01-09 シャープ株式会社 Manufacturing method of semiconductor device
JP5110776B2 (en) * 2004-07-01 2012-12-26 セイコーインスツル株式会社 Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
KR101546537B1 (en) 2015-08-21
TW200924072A (en) 2009-06-01
CN101355104B (en) 2015-05-20
JP2009054999A (en) 2009-03-12
CN101355104A (en) 2009-01-28
TWI445094B (en) 2014-07-11
JP5314949B2 (en) 2013-10-16
KR20090012160A (en) 2009-02-02
JP2013179333A (en) 2013-09-09

Similar Documents

Publication Publication Date Title
JP5567711B2 (en) Semiconductor device
JP5767430B2 (en) Semiconductor device and manufacturing method of semiconductor device
US20060065928A1 (en) Semiconductor device
JP2009088005A (en) Semiconductor device and method of manufacturing the same
JP5159365B2 (en) Semiconductor device and manufacturing method thereof
JP2006059940A (en) Semiconductor device
KR100854501B1 (en) Mos transistor having a recessed channel region and methods of fabricating the same
US7705399B2 (en) Semiconductor device with field insulation film formed therein
JP5616720B2 (en) Semiconductor device and manufacturing method thereof
US8236648B2 (en) Trench MOS transistor and method of manufacturing the same
US8173509B2 (en) Semiconductor device and method for manufacturing the same
JP2009272453A (en) Transistor, semiconductor apparatus, and method of manufacturing the same
JP2004247541A (en) Semiconductor device and its manufacturing method
KR101530579B1 (en) Semiconductor device and method for manufacturing the same
KR20140001087A (en) Vertical power mosfet and methods of forming the same
JP2009004493A (en) Semiconductor device and its manufacturing method
JP5165954B2 (en) Semiconductor device
TWI760453B (en) Method of manufacturing semiconductor device
JP5719899B2 (en) Semiconductor device
JP5386120B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP4191025B2 (en) Vertical MISFET
JP2004146825A (en) Mos transistor and its manufacturing method
JP2005322723A (en) Semiconductor device, and manufacturing method therefor
JP5014839B2 (en) Method for manufacturing silicon carbide semiconductor device
JP5014622B2 (en) Insulated gate type semiconductor device manufacturing method

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140228

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140304

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140430

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140527

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140619

R150 Certificate of patent or registration of utility model

Ref document number: 5567711

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees