TWI445094B - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- TWI445094B TWI445094B TW097128181A TW97128181A TWI445094B TW I445094 B TWI445094 B TW I445094B TW 097128181 A TW097128181 A TW 097128181A TW 97128181 A TW97128181 A TW 97128181A TW I445094 B TWI445094 B TW I445094B
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- 239000004065 semiconductor Substances 0.000 title claims description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims 1
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 239000011800 void material Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
Description
本發明有關包括需要高驅動性能的金氧半(MOS)電晶體之半導體裝置，與有關該半導體裝置之製造方法。The present invention relates to a semiconductor device including a metal oxide half (MOS) transistor requiring high driving performance, and a method of manufacturing the semiconductor device.
MOS電晶體係電子工學中之核心電子元件。其重要的是達成該MOS電晶體之微型化及其高驅動性能。對該MOS電晶體賦予高驅動性能的方法之一係一閘極寬度之擴展，以減少導通電阻。然而，有一問題係用於該MOS電晶體之大閘極寬度需要一寬廣之佔用面積。當作對於此的一解決方法，已提出一技術，藉此一大閘極寬度被給與，同時抑制該MOS電晶體之佔用面積的增加。(譬如，看日本專利第JP 2006-49826 A號)。The core electronic components in MOS electro-crystal system electronics engineering. It is important to achieve miniaturization of the MOS transistor and its high driving performance. One of the methods of imparting high driving performance to the MOS transistor is an extension of the gate width to reduce the on-resistance. However, there is a problem that the large gate width of the MOS transistor requires a wide footprint. As a solution to this, a technique has been proposed whereby a large gate width is given while suppressing an increase in the occupied area of the MOS transistor. (For example, see Japanese Patent No. JP 2006-49826 A).
下文，將參考圖4A至4D敘述一傳統半導體裝置。如在圖4A之透視圖中所顯示，該傳統半導體裝置包括一提供於井11中之溝渠結構3、及一提供於具有該溝渠結構3的溝渠部份中及在一沒有通過閘極絕緣薄膜6的溝渠之平面部份的頂部表面上之閘極7。於該井11的一表面部份中，該閘極7的一側面係設有一源極區域9，且其另一側面係設有一汲極區域10。圖4B係一取自圖4A沿著剖線A-A之A-A橫截面視圖，且顯示該平面部份。圖4C係於一垂直於通道之方向中取自圖4A沿著剖線B-B之B-B橫截面視圖。如在該B-B橫截面視圖中所顯示，該閘極7係形成在該溝渠部份3中，且因此藉由位於該閘極7下方之閘極絕緣薄膜6所形成的曲線之總延伸長度係一閘極寬度。Hereinafter, a conventional semiconductor device will be described with reference to FIGS. 4A to 4D. As shown in the perspective view of FIG. 4A, the conventional semiconductor device includes a trench structure 3 provided in the well 11, and a trench portion provided in the trench structure 3 and a gate insulating film not passed through The gate 7 on the top surface of the planar portion of the trench. In a surface portion of the well 11, one side of the gate 7 is provided with a source region 9, and the other side thereof is provided with a drain region 10. Figure 4B is a cross-sectional view taken along line A-A of Figure 4A taken along line A-A and showing the planar portion. Figure 4C is a cross-sectional view taken along line B-B of Figure 4A taken along line B-B in a direction perpendicular to the channel. As shown in the BB cross-sectional view, the gate 7 is formed in the trench portion 3, and thus the total extension length of the curve formed by the gate insulating film 6 under the gate 7 is One gate width.
如上面所述，於此技術中，既然該閘極部份具有包括一凸出部份及一凹入部份之溝渠結構，該實際之閘極寬度可為大於僅只在其一平坦表面上所製成之閘極的寬度。據此，每單位面積之導通電阻能被減少，而不會降低MOS電晶體之耐壓。As described above, in this technique, since the gate portion has a trench structure including a convex portion and a concave portion, the actual gate width can be larger than only on a flat surface thereof. The width of the gate made. Accordingly, the on-resistance per unit area can be reduced without lowering the withstand voltage of the MOS transistor.
本發明之發明人已發現一問題，即於上述該半導體裝置之結構中，一實際驅動性能不能抵達該期待之驅動性能。其亦已發現該驅動性能視該閘極長度而定變化，且傾向於在一短閘極長度裝置中為低的。The inventors of the present invention have found a problem that in the structure of the above semiconductor device, an actual driving performance cannot reach the desired driving performance. It has also been found that the drive performance varies depending on the length of the gate and tends to be low in a short gate length device.
其已假定此現象係藉由該源極及該汲極之間所產生的通道中之非均勻電流流動所造成：大部分電流沿著路徑A流動，該路徑A係一平面部份，在此未形成該溝渠部份3；一些電流沿著路徑B流動，該路徑B係該溝渠部份3的一側表面，其係在連接該源極及該汲極之方向中平行於該通道，及沿著路徑C，該路徑C係該溝渠部份3的一底部表面，如圖4D中所示。據此，該電流在該短閘極長度裝置中傾向於集中至該路徑A，其被認為該短閘極長度裝置中之驅動性能降低的成因。It has been assumed that this phenomenon is caused by the non-uniform current flow in the channel created between the source and the drain: most of the current flows along path A, which is a planar portion, where The trench portion 3 is not formed; some current flows along the path B, which is a side surface of the trench portion 3, which is parallel to the channel in a direction connecting the source and the drain, and Along the path C, the path C is a bottom surface of the trench portion 3, as shown in Figure 4D. Accordingly, the current tends to concentrate to the path A in the short gate length device, which is considered to be the cause of the reduced driving performance in the short gate length device.
本發明之一目的係改善一具有溝渠結構的半導體裝置之驅動性能。It is an object of the present invention to improve the driving performance of a semiconductor device having a trench structure.
為了解決該前述之問題，本發明採用以下之機構：In order to solve the aforementioned problems, the present invention employs the following mechanisms:
(1)一半導體裝置包括：一第一導電率型半導體基板；一溝渠結構，其形成在該第一導電率型半導體基板上，且於一閘極寬度方向中具有一連續變化之深度；一閘極，其形成在一藉由該溝渠結構所界定之溝渠部份內，且經由一閘極絕緣薄膜形成在一平面部份之頂部表面上；一第二導電率型之源極區域，其形成在該閘極的一側面上；及該第二導電率型的一汲極區域，其形成在該閘極之另一側面上，其中將該溝渠部份夾在中間且面朝彼此之該源極區域及該汲極區域的部份係具有由該溝渠結構之頂部表面至其底部與較深位置之一的深度；(1) a semiconductor device comprising: a first conductivity type semiconductor substrate; a trench structure formed on the first conductivity type semiconductor substrate and having a continuously varying depth in a gate width direction; a gate formed in a trench portion defined by the trench structure and formed on a top surface of a planar portion via a gate insulating film; a second conductivity type source region Forming on one side of the gate; and a drain region of the second conductivity type formed on the other side of the gate, wherein the trench portion is sandwiched and facing each other The source region and the portion of the drain region have a depth from one of a top surface of the trench structure to a bottom portion thereof and a deeper position;
(2)一半導體裝置包括：一第一導電率型半導體基板；一第二導電率型之源極區域及該第二導電率型之汲極區域，其在該第一導電率型半導體基板之表面附近被設置成彼此隔開；一平面部份，其係平坦的，且被設置於該源極區域及該汲極區域之間，以變成第一通道區域；一溝渠部份，其具有一恆定之深度，並隨著該平面部份設置，且具有一側表面及一用作第二通道區域之底部表面；一閘極絕緣薄膜，其被提供至該平面部份的一表面與該溝渠部份的一表面；及一閘極，其設在該閘極絕緣薄膜上，其中經由該溝渠部份面朝彼此之源極區域及汲極區域的部份包括一擴散區域，該擴散區域具有由該溝渠結構之頂部表面至其底部與較深位置之一的深度；及(2) A semiconductor device comprising: a first conductivity type semiconductor substrate; a second conductivity type source region; and the second conductivity type drain region, wherein the first conductivity type semiconductor substrate The surfaces are disposed to be spaced apart from each other; a planar portion is flat and disposed between the source region and the drain region to become a first channel region; a trench portion having a a constant depth, along with the planar portion, and having a side surface and a bottom surface serving as a second channel region; a gate insulating film provided to a surface of the planar portion and the trench a portion of a surface; and a gate disposed on the gate insulating film, wherein a portion of the source region and the drain region facing each other via the trench portion includes a diffusion region having a depth from one of the top surface of the trench structure to one of its bottom and a deeper position; and
(3)一半導體裝置製造方法，包括：製備一半導體基板；移去一區域的一部份，以變成該半導體基板之由其一表面至其內側的一通道區域，且形成一具有側表面及底部表面之溝渠，以設置一平面部份及一溝渠部份；在該溝渠部份的一表面及該平面部份的一表面上形成一氧化物薄膜；施加一抗蝕劑材料及施行圖案化，以致一雜質能於源極區域方向及汲極區域方向中由該溝渠之頂部表面被導入至其底部表面；離子植入一雜質，用於轉動該半導體基板形成第一源極區域及第一汲極區域；移除該抗蝕劑材料及該氧化物薄膜，且形成一閘極絕緣薄膜；沈積多晶矽，以形成一閘極；及形成第二源極區域及第二汲極區域，以將該閘極夾在其間。(3) A semiconductor device manufacturing method comprising: preparing a semiconductor substrate; removing a portion of a region to become a channel region of the semiconductor substrate from a surface to an inner side thereof, and forming a side surface and a trench on the bottom surface for providing a planar portion and a trench portion; forming an oxide film on a surface of the trench portion and a surface of the planar portion; applying a resist material and performing patterning So that an impurity can be introduced into the bottom surface of the trench from the top surface of the trench in the direction of the source region and the drain region; ion implantation an impurity for rotating the semiconductor substrate to form the first source region and the first a drain region; removing the resist material and the oxide film, and forming a gate insulating film; depositing a polysilicon to form a gate; and forming a second source region and a second drain region to The gate is sandwiched therebetween.
根據本發明，於上述半導體裝置之源極區域的一部份及該汲極區域的一部份中，由該溝渠部份之頂部表面分佈至其底部的深擴散區域之形成係能夠經過一光阻薄膜之施加及圖案化，及在形成該閘極之前離子植入至該溝渠部份。據此，能在一於該閘極寬度方向中具有連續變化深度的凹入部份之頂部減少電流密度，且亦能夠使該電流沿著該溝渠部份之側表面及底部表面流動，增強該半導體裝置之驅動性能。According to the present invention, in a portion of the source region of the semiconductor device and a portion of the drain region, the formation of the deep diffusion region distributed from the top surface of the trench portion to the bottom portion thereof can pass through a light The application and patterning of the resistive film and ion implantation into the trench portion prior to formation of the gate. According to this, the current density can be reduced at the top of the concave portion having the continuously varying depth in the gate width direction, and the current can also flow along the side surface and the bottom surface of the trench portion, enhancing the Drive performance of semiconductor devices.
在下文，將參考該等圖面敘述本發明之具體實施例。圖1A至1H係一製程順序流程之概要剖視圖，顯示本發明之第一具體實施例的半導體裝置製造方法。In the following, specific embodiments of the invention will be described with reference to the drawings. 1A to 1H are schematic cross-sectional views showing a process sequence of a process, showing a method of fabricating a semiconductor device according to a first embodiment of the present invention.
於圖1A中，在第一導電率型半導體基板上，譬如，p型半導體基板1、或一由於硼之加入而具有由20歐姆-公分至30歐姆-公分的電阻係數之雜質密度的半導體基板上，藉由矽的局部氧化(LOCOS)方法形成一厚氧化物薄膜2，諸如一具有500奈米至1微米之厚度的熱氧化物薄膜。該基板之導電率型係與本發明之本質無關。如圖1B所示，一溝渠結構3係形成在該第一導電率型半導體基板上，譬如，具有數百奈米至數微米之深度。然後，氧化物薄膜4係譬如形成於數百埃之厚度中。In FIG. 1A, on a first conductivity type semiconductor substrate, for example, a p-type semiconductor substrate 1, or a semiconductor substrate having an impurity density of 20 ohm-cm to 30 ohm-cm resistivity due to the addition of boron. On top, a thick oxide film 2 such as a thermal oxide film having a thickness of 500 nm to 1 μm is formed by a local oxidation of ruthenium (LOCOS) method. The conductivity type of the substrate is independent of the nature of the invention. As shown in FIG. 1B, a trench structure 3 is formed on the first conductivity type semiconductor substrate, for example, having a depth of several hundred nanometers to several micrometers. Then, the oxide film 4 is formed, for example, in a thickness of several hundred angstroms.
在此之後，如圖1C所示，一抗蝕劑薄膜5被施加，且如在圖1D所示，在一源極區域及一汲極區域中藉由圖案化移除該抗蝕劑薄膜5，以致能由該溝渠結構3的一頂部表面至其底部表面或直至一較深位置施行將雜質加入至該源極區域及該汲極區域。代替該抗蝕劑薄膜5，氮化物薄膜或多晶矽薄膜能被用作一用於圖案化之光罩。在此之後，如圖1E所示，諸如砷之雜質較佳地係藉由自旋(轉動)一晶圓在每平方公分1x1013 個原子至每平方公分1x1016 個原子之劑量被離子植入。Thereafter, as shown in FIG. 1C, a resist film 5 is applied, and as shown in FIG. 1D, the resist film 5 is removed by patterning in a source region and a drain region. So that impurities can be added to the source region and the drain region from a top surface of the trench structure 3 to a bottom surface thereof or up to a deeper position. Instead of the resist film 5, a nitride film or a polysilicon film can be used as a mask for patterning. Thereafter, as shown in FIG. 1E, impurities such as arsenic are preferably ion implanted by spin (rotating) a wafer at a dose of 1 x 10 13 atoms per square centimeter to 1 x 10 16 atoms per square centimeter. .
圖2A及2B詳細地敘述此步驟。圖2A及2B係概要視圖，顯示圖1E之離子植入步驟。圖2A顯示一源極區域側面，且當該晶圓相對於圖2A被轉動180度時，圖2B顯示一汲極區域側面。如在圖2A所顯示，一雜質被加至該溝渠結構3的一側表面及其一底部表面，且在離子植入之低入射角下施行離子植入，同時自旋(轉動)該晶圓。據此，如圖2B所顯示，亦可在該汲極區域上由一側表面至其底部表面施行該雜質之導入，其係位在該源極區域側面上之抗蝕劑薄膜5的一相反側面中。圖3A係圖1E所示裝置之平面圖，其係一A-A剖視圖，顯示圖3A所示之A-A部份。該抗蝕劑薄膜5及該氧化物薄膜4稍後被移除。This step is described in detail in Figures 2A and 2B. 2A and 2B are schematic views showing the ion implantation step of Fig. 1E. 2A shows a side of a source region, and FIG. 2B shows a side of a drain region when the wafer is rotated 180 degrees relative to FIG. 2A. As shown in FIG. 2A, an impurity is applied to one side surface of the trench structure 3 and a bottom surface thereof, and ion implantation is performed at a low incident angle of ion implantation while spinning (rotating) the wafer. . Accordingly, as shown in FIG. 2B, the introduction of the impurity may be performed on the drain region from the one surface to the bottom surface thereof, which is opposite to the resist film 5 on the side of the source region. In the side. Figure 3A is a plan view of the apparatus of Figure 1E, taken along the line A-A, showing the A-A portion of Figure 3A. The resist film 5 and the oxide film 4 are later removed.
隨後，如圖1F所示，一閘極絕緣薄膜6係由譬如具有數百至數千埃厚度之熱氧化物薄膜所形成。然後，多晶矽閘極薄膜較佳地是於100奈米至500奈米之厚度中沉積在該閘極絕緣薄膜6上，且一雜質係藉由預先沉積或一離子植入方法所導入，以獲得一閘極7。在此，藉由該離子植入所導入之雜質係同時於該閘極絕緣薄膜6之形成中擴散及活化，該閘極絕緣薄膜係一熱氧化物薄膜。於此步驟中，已擴散有該雜質之源極區域9及汲極區域10兩者係由該溝渠結構3之頂部表面至其底部或一較深位置進一步擴散。此外，於藉由上述該離子植入在高密度施行該雜質導入之案例中，形成在該源極區域9及該汲極區域10的每一表面上之熱氧化物薄膜變厚。據此，該閘極及該汲極間之電容可被自動地減少。Subsequently, as shown in Fig. 1F, a gate insulating film 6 is formed of, for example, a thermal oxide film having a thickness of several hundreds to several thousand angstroms. Then, the polysilicon gate film is preferably deposited on the gate insulating film 6 in a thickness of from 100 nm to 500 nm, and an impurity is introduced by a pre-deposition or an ion implantation method to obtain A gate 7. Here, the impurity introduced by the ion implantation is simultaneously diffused and activated in the formation of the gate insulating film 6, and the gate insulating film is a thermal oxide film. In this step, both the source region 9 and the drain region 10, to which the impurity has been diffused, are further diffused from the top surface of the trench structure 3 to the bottom or a deeper position thereof. Further, in the case where the impurity implantation is performed at a high density by the ion implantation described above, the thermal oxide film formed on each of the source region 9 and the surface of the drain region 10 becomes thick. Accordingly, the capacitance between the gate and the drain can be automatically reduced.
在另一方面，該閘極7係以一抗蝕劑薄膜8圖案化，以獲得圖1G所示結構。隨後，如圖1G所示，施行雜質加入，以用自行對齊之方式相對於該閘極7形成一源極區域及一汲極區域。於該雜質加入至該源極區域及該汲極區域中，譬如，砷較佳地係在每平方公分1x1015 個原子至每平方公分1x1016 個原子之劑量被離子植入。經過該前述之製程，一具有該溝渠結構3之MOS電晶體被組構。如圖1H所示，在攝氏800度至1000度熱處理達數小時，然後，形成該源極區域9及該汲極區域10。On the other hand, the gate 7 is patterned with a resist film 8 to obtain the structure shown in Fig. 1G. Subsequently, as shown in FIG. 1G, impurity addition is performed to form a source region and a drain region with respect to the gate 7 in a self-aligned manner. The impurities are added to the source region and the drain region. For example, arsenic is preferably ion implanted at a dose of from 1 x 10 15 atoms to 1 x 10 16 atoms per square centimeter. Through the foregoing process, a MOS transistor having the trench structure 3 is structured. As shown in FIG. 1H, the heat treatment is performed at 800 to 1000 degrees Celsius for several hours, and then the source region 9 and the drain region 10 are formed.
當作本發明之第二具體實施例，在形成該閘極絕緣薄膜6之後，能施行如上述該雜質加入至該源極區域9及該汲極區域10，以便由該溝渠結構3之頂部表面至其底部或一較深位置深深地施行。As a second embodiment of the present invention, after the gate insulating film 6 is formed, the impurity can be applied to the source region 9 and the drain region 10 as described above so as to be formed by the top surface of the trench structure 3. Go deep into the bottom or a deeper position.
圖3B顯示本發明的前述第一具體實施例或第二具體實施例中所獲得之半導體裝置的平面圖。圖3C分別係取自圖3B沿著剖線A-A之A-A剖視圖，且圖3D係取自圖3B沿著剖線B-B之B-B剖視圖。參考圖3C，於一具有該溝渠結構3之溝渠部份電晶體12中，一擴散區域係於該閘極7之附近由該溝渠結構3之頂部表面至其底部或一較深位置形成在該源極區域9及該汲極區域10中。同時，參考圖3D，於一平面部份電晶體13中，該擴散區域係於該源極區域9及該汲極區域10中在該閘極7附近完全地形成有一大體上相等之深度。Fig. 3B is a plan view showing the semiconductor device obtained in the foregoing first embodiment or second embodiment of the present invention. 3C is taken along the line A-A of FIG. 3B along the line A-A, and FIG. 3D is taken along the line B-B of FIG. 3B along the line B-B. Referring to FIG. 3C, in a trench portion transistor 12 having the trench structure 3, a diffusion region is formed in the vicinity of the gate 7 from a top surface of the trench structure 3 to a bottom portion thereof or a deeper position. The source region 9 and the drain region 10 are included. Meanwhile, referring to FIG. 3D, in a planar partial transistor 13, the diffusion region is formed in the source region 9 and the drain region 10 completely at a substantially equal depth near the gate 7.
圖5係本發明的第三具體實施例中所獲得之半導體裝置的平面圖。圖5係在該源極區域及該汲極區域上之接點的位置中不同於圖3B。於圖3B中，溝渠部份接點及平面部份接點被配置成一列。然而，於此具體實施例中，為了減少一寄生阻抗，一平面部份接點15及該閘極7間之距離係比溝渠部份接點14及該閘極間之距離較短。Figure 5 is a plan view of a semiconductor device obtained in a third embodiment of the present invention. Figure 5 is different from Figure 3B in the location of the contacts on the source region and the drain region. In FIG. 3B, the trench portion contacts and the planar portion contacts are arranged in a row. However, in this embodiment, in order to reduce a parasitic impedance, the distance between a planar partial contact 15 and the gate 7 is shorter than the distance between the trench portion contact 14 and the gate.
如上面所述，在本發明中，於具有該溝渠結構之溝渠部份電晶體12中，該擴散區域係由該溝渠結構3之頂部表面至其底部或一較深位置所形成。據此，能在一於該閘極寬度方向中具有連續變化深度的凹入部份之頂部減少電流密度，且亦能夠使該電流沿著該溝渠部份之側表面及底部表面流動，增強該半導體裝置之驅動性能。As described above, in the present invention, in the trench portion transistor 12 having the trench structure, the diffusion region is formed by the top surface of the trench structure 3 to the bottom portion or a deeper position. According to this, the current density can be reduced at the top of the concave portion having the continuously varying depth in the gate width direction, and the current can also flow along the side surface and the bottom surface of the trench portion, enhancing the Drive performance of semiconductor devices.
1．．．半導體基板1. . . Semiconductor substrate
2．．．氧化物薄膜2. . . Oxide film
3．．．溝渠結構3. . . Ditch structure
4．．．氧化物薄膜4. . . Oxide film
5．．．抗蝕劑薄膜5. . . Resist film
6．．．閘極絕緣薄膜6. . . Gate insulating film
7．．．閘極7. . . Gate
8．．．抗蝕劑薄膜8. . . Resist film
9．．．源極區域9. . . Source area
10．．．汲極區域10. . . Bungee area
11．．．井11. . . well
12．．．溝渠部份電晶體12. . . Part of the ditch
13．．．平面部份電晶體13. . . Plane partial transistor
14．．．溝渠部份接點14. . . Ditch part joint
15．．．平面部份接點15. . . Plane partial contact
於所附圖面中：In the drawings:
圖1A至1H係一製程順序流程之概要剖視圖，顯示本發明之第一具體實施例；1A to 1H are schematic cross-sectional views showing a process sequence flow, showing a first embodiment of the present invention;
圖2A及2B係該製程順序流程的概要剖視圖中之離子植入步驟的概要視圖，顯示本發明之第一具體實施例；2A and 2B are schematic views of an ion implantation step in a schematic cross-sectional view of the process sequence flow, showing a first embodiment of the present invention;
圖3A及3B係概要平面圖，且圖3C及3D係概要剖視圖，顯示本發明的第一具體實施例及第二具體實施例中所獲得之半導體裝置；3A and 3B are schematic plan views, and FIGS. 3C and 3D are schematic cross-sectional views showing the semiconductor device obtained in the first embodiment and the second embodiment of the present invention;
圖4A至4D係概要視圖及剖視圖，顯示一相關技藝及其問題；及4A to 4D are schematic views and cross-sectional views showing a related art and problems thereof;
圖5係本發明的第三具體實施例中所獲得之半導體裝置的概要平面圖。Figure 5 is a schematic plan view of a semiconductor device obtained in a third embodiment of the present invention.
1．．．半導體基板1. . . Semiconductor substrate
2．．．氧化物薄膜2. . . Oxide film
3．．．溝渠結構3. . . Ditch structure
4．．．氧化物薄膜4. . . Oxide film
5．．．抗蝕劑薄膜5. . . Resist film
6．．．閘極絕緣薄膜6. . . Gate insulating film
7．．．閘極7. . . Gate
9．．．源極區域9. . . Source area
10．．．汲極區域10. . . Bungee area
12．．．溝渠部份電晶體12. . . Part of the ditch
13．．．平面部份電晶體13. . . Plane partial transistor
14．．．溝渠部份接點14. . . Ditch part joint
15．．．平面部份接點15. . . Plane partial contact
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| JP5378925B2 (en) | 2009-09-24 | 2013-12-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US8558320B2 (en) * | 2009-12-15 | 2013-10-15 | Qualcomm Incorporated | Systems and methods employing a physically asymmetric semiconductor device having symmetrical electrical behavior |
| JP2012204799A (en) * | 2011-03-28 | 2012-10-22 | Toshiba Corp | Semiconductor memory device and method of manufacturing the same |
| CN103280455B (en) * | 2013-04-28 | 2016-05-18 | 苏州市职业大学 | Horizontal proliferation type low on-resistance MOS device |
| CN104465726B (en) * | 2013-09-17 | 2017-08-11 | 世界先进积体电路股份有限公司 | Semiconductor device and its manufacture method |
| US9773902B2 (en) | 2013-11-25 | 2017-09-26 | Vanguard International Semiconductor Corporation | Trench-gate semiconductor device and method for forming the same |
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| JPH0223670A (en) * | 1988-07-12 | 1990-01-25 | Seiko Epson Corp | Semiconductor device |
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