JP2011210905A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of a MOS transistor having a trench structure facilitating an appropriate adjustment of a thereshold value of a channel region.SOLUTION: In a MOS transistor having a trench structure in which a concave region with its depth varied in a gate width direction and the concave region of a convex region are formed in the trench structure on a first conductive type semiconductor substrate, and a first conductive doped polysilicon film formed through a sacrifice oxide film formed along the surface of the first conductive type semiconductor substrate is embedded in the trench structure of the concave region and heat treated, diffusing impurities on an upper face of the convex region between the trench structures and on the side face and the bottom face of the concave part region of the trench structure. This facilitates a uniform impurity doping to a channel even for reduced trench pitches.

Description

  The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a MOS transistor having a trench structure, and manufacture of a semiconductor device capable of uniform impurity addition even when the trench pitch is reduced for high driving capability. Regarding the method.

  Currently, in a MOS transistor constituting a power management semiconductor device such as a voltage detector, a constant voltage regulator, or a switching regulator, low voltage operation, low power consumption, or high driving capability is achieved. Has become an important issue. In particular, as one method for increasing the driving capability of a MOS transistor, there is a method of reducing the on-resistance by increasing the gate width, but there is a problem that the area occupied by the MOS transistor increases when the gate width is increased. . On the other hand, a technique for increasing the gate width while having a trench structure and suppressing an increase in the area occupied by the MOS transistor has been proposed. (For example, see Patent Document 1)

The structure and operation of a conventional MOS transistor having a trench structure will be described below with reference to Patent Document 1 with reference to FIG.
FIG. 4A is a schematic plan view of a MOS transistor having a trench structure. FIG. 4B is a cross-sectional view in the gate length direction between DD ′ in FIG. 4A in order to describe the structure. FIG. 4C shows a cross-sectional view in the gate length direction from EE ′ to FF ′ in FIG. Further, FIG. 3D shows a cross-sectional view in the gate width direction between GG ′ in FIG.

  First, FIG. 4B is a cross-sectional view of a portion having no trench structure in a MOS transistor having a trench structure, and an arrow A is a current flowing on the substrate surface as the MOS transistor. On the other hand, FIG. 4C shows, for example, an arrow B and an arrow C as the current flow. The arrow B indicates the current that flows at the convex portion of the trench structure in the back of the gate width direction. Indicates the current flowing at the bottom of the trench structure. As described above, in the MOS transistor having the trench structure, in the ON state, a current flows through the surface and other channels, so that high driving capability can be obtained.

  In addition, in the MOS transistor having the trench structure, as shown in FIG. 4D, the trench structure is deepened and the trench structure adjacent to the width of the upper surface of the convex region 17 between the trench structures of the trench structure 6 is used. It is possible to increase the gate width direction without increasing the planar element area by reducing the distance of the width of the bottom surface of the recess region 18 (hereinafter referred to as the trench pitch), and further increase the driving capability. Is obtained.

  However, in order to achieve high driving capability, for example, when the trench pitch is reduced (for example, 0.7 um), the first conductive type semiconductor substrate inside the convex portion 17 between the trench structures shown in FIG. As a result, the threshold voltage is lowered and low voltage operation is possible. However, the leakage current at the OFF time increases between the second conductivity type source high concentration layer and the second conductivity type drain high concentration diffusion layer. There was a problem. On the other hand, there is a problem that even if an attempt is made to adjust the threshold value by adding impurities to the channel portion, it is difficult to uniformly add impurities to the top surfaces of the convex portions between the trench structures and the side surfaces and bottom surfaces of the concave portions of the trench structures. .

JP 2006-49826 A

  In a conventional MOS transistor having a trench structure aiming at high driving capability, means for reducing the trench pitch and deepening the trench structure have been made. In particular, the reduction of the trench pitch is caused by the inside of the convex substrate between the trench structures. Since all are depleted, there is a problem that the threshold voltage is lowered and the leakage current between the source and the drain is increased. On the other hand, even if it is attempted to adjust the threshold value by adding impurities to the channel region, it is difficult to uniformly add impurities to the top surfaces of the convex portions between the trench structures and the side surfaces and bottom surfaces of the concave portions of the trench structures. It was.

  The present invention has been made in view of the above problems, and an object thereof is to uniformly add impurities even when the trench pitch is reduced.

In order to solve the above problems, the present invention uses the following means.
(1) Formed along the surface of the trench structure, having a concave region and a convex region, the depth of which is intermittently changed in the gate width direction formed in the first conductivity type semiconductor substrate using the trench structure. A gate electrode formed through the gate insulating film, a second conductivity type source high-concentration diffusion layer formed on one side of the gate electrode, and a second layer formed on the other side of the gate electrode. A method of manufacturing a semiconductor device having a conductive drain high-concentration diffusion layer, wherein the side and bottom surfaces of a recessed region of a trench structure whose depth changes intermittently in the gate width direction, and the upper surface of a protruding region between the trench structures Impurities are added to the trench structure of the recess region by embedding a first conductivity type doped polysilicon film formed through a sacrificial oxide film formed along the surface of the first conductivity type semiconductor substrate. Conduction type doped port Side surface and the bottom surface of the recess region of the trench structure in which the silicon film intermittently depth to the gate width direction from the changes, and the method of manufacturing a semiconductor device to diffuse the impurities by heat treatment to the convex region upper surface between the trench structures.

(2) Impurity addition of the concave region and the convex region whose depth intermittently changes in the gate width direction of the semiconductor device is performed through a sacrificial oxide film formed along the surface of the first conductivity type semiconductor substrate. The formed first conductivity type doped polysilicon film is buried in the trench structure of the recess region, and when the conductivity type is P type, the impurity diffusion is a method of manufacturing a semiconductor device in which heat treatment is performed at 850 ° C. to 950 ° C.

(3) The width of the bottom surface of the recess region of the trench structure of the recess region and the convex region of the recess region whose depth intermittently changes in the gate width direction of the semiconductor device and the width of the upper surface of the convex region between the adjacent trench structures The combined trench pitch is 0.6 μm to 1.2 μm, and the depth of the trench structure forming the recessed region is 1 μm to 2 μm.

  As described above, according to the method for manufacturing a semiconductor device of the present invention, it is possible to uniformly add impurities to the top surfaces of the convex portions between the trench structures and the side surfaces and bottom surfaces of the concave portions of the trench structures, and the threshold value of the channel region is appropriately set. Adjustment is possible.

The schematic diagram of the semiconductor device obtained by the manufacturing method of the semiconductor device which shows the feature of the present invention Process flow by schematic gate width direction sectional view showing an embodiment of the present invention Process flow by schematic gate length direction sectional view showing an embodiment of the present invention Cross-sectional view of conventional semiconductor device and schematic diagram explaining operating characteristics

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic view of a semiconductor device obtained by an embodiment of a semiconductor device manufacturing method of the present invention. 1A is a schematic plan view, and FIG. 1B is a schematic cross-sectional view taken along the line AA ′ in the gate width direction of FIG. FIG. 1C is a perspective view taken along the line BB ′ and CC ′ in FIG. 1A, where the horizontal direction is the gate length direction and the depth is the gate width direction. It becomes.

  First, the planar structure of the semiconductor device of the present invention will be described with reference to FIG. A plurality of trench structures 6 are formed in a region on the semiconductor substrate of the first conductivity type surrounded by the LOCOS oxide film 2, and convex regions and concave regions are alternately arranged. A gate insulating film 11 is usually formed of a thermal oxide film on the surface of the convex region and the concave region. The gate electrode 14 is disposed so as to continuously cover the convex region and the concave region, the second conductive type source high-concentration diffusion layer 15 is provided on one side of the gate electrode 11, and the second conductive material is provided on the other side. A type drain high concentration diffusion layer 16 is formed.

FIG. 1B is a schematic cross-sectional view in the channel width direction, and shows convex regions and concave regions alternately arranged in the trench structure 6. A diffused impurity diffusion layer 10 of the first conductivity type is provided in the vicinity of the surface of the trench structure 6 to determine transistor characteristics.
FIG. 1C is a perspective view when cut along the recessed region, and shows a transistor formed by the recessed region.

  Next, an embodiment of the manufacturing method according to the present invention when manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS.

FIG. 2 is a schematic cross-sectional view showing an embodiment of the method for manufacturing a semiconductor device of the present invention, which is the same cross-sectional direction as the cross-sectional schematic view in the gate width direction of FIG.
In FIG. 2A, first, a first conductivity type semiconductor substrate, for example, a P-type semiconductor substrate 1, for example, a boron-doped semiconductor substrate having a resistivity of 20 Ωcm to 30 Ωcm is isolated by LOCOS method (Local Oxidation of Silicon). A LOCOS oxide film 2 is formed.

  Next, as shown in FIG. 2B, the hard masks 3 and 4 are patterned for trench etching. The hard mask here is preferably a laminated structure of a thermal oxide film having a film thickness of several tens of nm and a CVD oxide film having a film thickness of several tens to several hundreds of nm. However, only one of the oxide films can be used as long as the film has a sufficient resistance to subsequent trench etching. Furthermore, there is no problem even if the hard mask here is a resist film or a silicon nitride film. Next, this hard mask is patterned with the resist film 5 to pattern the underlying hard masks 3 and 4. Next, after removing the resist film 5, as shown in FIG. 2C, dry etching is performed to obtain a trench structure 6. Here, the trench pitch, which is the distance between the width of the bottom surface of the concave region of the trench structure and the width of the upper surface of the convex region between adjacent trench structures, and the depth of the trench structure are from 0.6 um to 1 μm. It is desirable that the trench structure has a depth of 1 μm to 2 μm.

  Thereafter, after removing the hard masks 3 and 4, as shown in FIG. 2D, a sacrificial oxide film 7 is formed by thermal oxidation of, for example, several nm to several tens nm, and the sacrificial oxide film is formed. Then, a P-type doped polysilicon film 8 is formed. The doped polysilicon film 8 is a polycrystalline silicon film into which impurities have already been introduced at the time of film formation, and can be formed by introducing an impurity gas such as diborane at the time of film formation of the polycrystalline silicon. The doped polysilicon film 8 in this step can be formed using a low pressure CVD apparatus or the like.

  Subsequently, as shown in FIG. 2E, patterning for removing the unnecessary doped polysilicon film is performed while leaving the doped polysilicon film necessary for the addition of impurities to the channel in the resist film 9. Then, the doped polysilicon film is removed by etching. Here, what leaves the doped polysilicon film is, for example, a MOS transistor having an N-channel trench structure.

  Thereafter, as shown in FIG. 2F, the resist film 9 is removed and heat treatment is performed to form the first conductivity type impurity diffusion layer 10. Here, for example, boron-based impurities (shown by dots for separation in the figure) are thermally diffused into the channel portion. Here, the heat treatment of the doped polysilicon film of the first conductivity type is, for example, in the case of the P type, the protrusion between the trench structures via the sacrificial oxide film 7 by heat treatment at 850 ° C. to 950 ° C. in a nitrogen atmosphere. It can diffuse to the upper surface of the partial region and the side and bottom surfaces of the recessed region of the trench structure.

  In the above-described embodiments shown in FIGS. 2D to 2F, the first conductivity type doped polysilicon film is used for thermal diffusion to the channel portion. A second conductivity type doped polysilicon film by a semiconductor substrate is also possible.

  Next, as shown in FIG. 2G, after all the doped polysilicon film 8 is removed by wet etching, the sacrificial oxide film 7 is also removed by wet etching.

  Thereafter, as shown in FIG. 2 (H), a thermal oxide film having a thickness of, for example, several nanometers to several tens of nanometers is formed on the gate insulating film 11, and the non-doped polycrystalline silicon film 12 is preferably formed thereon. A film is formed with a thickness of 100 nm to 500 nm, and impurities are introduced by predeposition or ion implantation to form a gate electrode. The conductivity type here may be the second conductivity type, for example.

  Through the above steps, the trench structure 6 is provided, and, for example, boron-based impurities 10 are uniformly doped into the upper surface of the convex region between the trench structures and the side surface and the bottom surface of the concave region of the trench structure. Thus, the structure in which the polycrystalline silicon film 12 doped with impurities is formed is prepared.

From here on, the subsequent process flow will be described with reference to the schematic sectional view in the gate length direction of FIG.
In FIG. 3A, patterning is performed on the resist film 13 in order to use the doped polycrystalline silicon film 12 as a gate electrode.

Next, as shown in FIG. 3B, after forming the gate electrode 14, an impurity is added to form a source region and a drain region by a self-alignment method. The application of the self-alignment method here is not related to the essence of the present invention. For example, if the conductivity type is N-type, for example, arsenic or phosphorus is preferably ion-implanted at a dose of 1 × 10 ¹⁵ atoms / cm ² to 1 × 10 ¹⁶ atoms / cm ² . Further, the addition of impurities to the source region and the drain region here can be performed simultaneously under the same conditions as those of the MOS transistor in the same chip that does not have the trench 6.

  Thereafter, as shown in FIG. 3C, heat treatment is performed at 800 ° C. to 1000 ° C. for several hours to form the second conductivity type source high concentration diffusion layer 14 and the second conductivity type drain high concentration diffusion layer 15.

  As described above, the first conductivity type impurity diffusion layer 10, for example, a MOS having a trench structure in which boron-based impurities are uniformly added to the upper surface of the convex region between the trench structures 6 and the side surface and the bottom surface of the concave region of the trench structure 6. A transistor is manufactured.

DESCRIPTION OF SYMBOLS 1 1st conductivity type semiconductor substrate 2 LOCOS oxide film 3, 4 Hard mask 5, 9, 13 Resist film 6 Trench structure 7 Sacrificial oxide film 8 1st conductivity type doped polysilicon film 10 1st conductivity type impurity diffusion layer 11 Gate Insulating film 12 Polycrystalline silicon film 14 Gate electrode 15 Second conductivity type source high-concentration diffusion layer 16 Second conductivity type drain high-concentration diffusion layer 17 Convex region 18 between trench structures Concave region of trench structure

Claims (3)

A gate insulating film formed on the surface of the trench structure, having a concave region and a convex region, the depth of which is intermittently changed in the gate width direction, formed on the first conductivity type semiconductor substrate using the trench structure. A second conductivity type source high concentration diffusion layer formed on one side of the gate electrode, and a second conductivity type drain high concentration formed on the other side of the gate electrode. A method for manufacturing a semiconductor device including a diffusion layer,
Depositing a sacrificial oxide film along the surface of the trench structure;
Burying a first conductivity type doped polysilicon film in the recess region via the sacrificial oxide film;
By the heat treatment, the first conductivity type doped polysilicon film has a first side surface and a bottom surface of the concave region of the trench structure whose depth is intermittently changed in the gate width direction, and an upper surface of the convex region between the trench structures. Diffusing impurities of conductive type;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductivity type impurity is a P type impurity, and the step of diffusing the first conductivity type impurity is 850 ° C. to 950 ° C. 3. .   A trench in which the width of the bottom surface of the concave region of the trench structure of the concave region and the convex region of the concave region whose depth changes intermittently in the gate width direction of the semiconductor device is matched to the width of the upper surface of the convex region between the adjacent trench structures 2. The method of manufacturing a semiconductor device according to claim 1, wherein the pitch is 0.6 μm to 1.2 μm, and the depth of the trench structure forming the recessed region is 1 μm to 2 μm.

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