JP5159365B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5159365B2
JP5159365B2 JP2008044392A JP2008044392A JP5159365B2 JP 5159365 B2 JP5159365 B2 JP 5159365B2 JP 2008044392 A JP2008044392 A JP 2008044392A JP 2008044392 A JP2008044392 A JP 2008044392A JP 5159365 B2 JP5159365 B2 JP 5159365B2
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trench
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semiconductor device
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JP2009206144A (en
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雅幸 橋谷
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Seiko Instruments Inc
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    • H01L29/1025—Channel region of field-effect devices
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    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/1025—Channel region of field-effect devices
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    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
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Description

本発明は、半導体装置およびその製造方法に関する。特に、トレンチを有するＭＯＳトランジスタに関するものであり、埋め込み層を用いて駆動能力の向上を図るものである。   The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a MOS transistor having a trench, and uses a buried layer to improve driving capability.

ＭＯＳトランジスタは電子部品において中核を担う素子であって、ＭＯＳトランジスタの小型化、低消費電力あるいは高駆動能力化は、重要な課題となっている。ＭＯＳトランジスタを高駆動能力化する方法の１つとして、ゲート幅を広くしてオン抵抗を低減させる方法があるが、ゲート幅を広くするとＭＯＳトランジスタの占有面積が大きくなるという問題があった。そこで、これまでにもトレンチを利用してＭＯＳトランジスタの専有面積の増加を抑えながらゲート幅を広くする技術が提案されている。   MOS transistors are the core elements of electronic components, and miniaturization, low power consumption, and high drive capability of MOS transistors are important issues. One method for increasing the driving capability of a MOS transistor is to increase the gate width to reduce the on-resistance, but there is a problem that the area occupied by the MOS transistor increases when the gate width is increased. Thus, there has been proposed a technique for widening the gate width while suppressing an increase in the area occupied by the MOS transistor by using a trench.

従来の半導体装置について図４を基に説明する。   A conventional semiconductor device will be described with reference to FIG.

図４（A）の斜視図に示すように、ＭＯＳトランジスタ幅方向（W方向）にトレンチ１３を有しており、表面でのゲート電極１５の幅に対して、実効的なゲート幅の長さが長くなるので、ＭＯＳトランジスタの耐圧を低下させずに単位面積あたりのオン抵抗を低減することができる。   As shown in the perspective view of FIG. 4A, the trench 13 is provided in the MOS transistor width direction (W direction), and the effective gate width is longer than the width of the gate electrode 15 on the surface. Therefore, the on-resistance per unit area can be reduced without lowering the breakdown voltage of the MOS transistor.

図４（B）はそのＭＯＳトランジスタの平面模式図である。トレンチ１３の断面をA-A'、トレンチ１３を有しない領域の断面をB-B'として、断面図を図４（C）および図４（D）にそれぞれ示す。図４（C）に示される領域は通常のプレーナー型ＭＯＳトランジスタになるので、電流がソース高濃度拡散層１６からドレイン高濃度拡散層１７に流れる場合には、電流経路は図中矢印Aのようになる。一方で、トレンチ１３を有する図４（D）に示される領域ではＭＯＳトランジスタ幅方向の奥行き側面において電流は矢印B、底部においては矢印Cで得られる。（例えば、特許文献１参照）
特開２００６−４９８２６号公報 FIG. 4B is a schematic plan view of the MOS transistor. The cross section of the trench 13 is shown as AA ′, the cross section of the region not having the trench 13 is BB ′, and cross sections are shown in FIGS. Since the region shown in FIG. 4C is a normal planar type MOS transistor, when a current flows from the source high concentration diffusion layer 16 to the drain high concentration diffusion layer 17, the current path is as indicated by an arrow A in the figure. become. On the other hand, in the region shown in FIG. 4D having the trench 13, the current is obtained by the arrow B at the depth side surface in the MOS transistor width direction and by the arrow C at the bottom. (For example, see Patent Document 1)
JP 2006-49826 A

しかしながら、従来技術では、より高駆動能力化を目指すためにトランジスタのL長を縮小する場合、実効的なチャネル長の距離の差が顕著になり、図４（D）の経路Cと図４（C）の経路Aでは、経路Aで示される平面領域が支配的になり、底部Cではほとんど流れなくなる。これにより、トレンチ１３を深く形成して実効的なゲート幅の長さを長くしてオン抵抗を減少させる策をとっても、駆動能力が得られないという問題がある。あわせて、トランジスタのゲート長さ（L方向）を縮小できないため、面積を縮小できない障害も生じてしまう。   However, in the conventional technique, when the L length of the transistor is reduced in order to achieve higher driving capability, the difference in effective channel length distance becomes significant, and the path C in FIG. In the route A of C), the plane area indicated by the route A becomes dominant, and almost no flow occurs at the bottom C. As a result, there is a problem in that the driving ability cannot be obtained even if the trench 13 is formed deep to increase the effective gate width to reduce the on-resistance. At the same time, since the gate length (L direction) of the transistor cannot be reduced, there is a problem that the area cannot be reduced.

このように、図４（A）の構造では、トレンチの深さを深くする、あるいはゲート幅（W方向）を縮小させて実効的なゲート幅を長くしても、ゲート長さ（L長方向）を縮小できないため、想定したよりも駆動能力が得られない、さらには、トランジスタの面積縮小ができないという問題がある。これは、L長の縮小でトレンチ上面、側面および底面での実効的なチャネル長距離の差が顕著になってしまい、優先的にトレンチ上面で電流が流れやすくなるので、トレンチを有する特徴である底面での電流が減少するためである。   Thus, in the structure of FIG. 4A, even if the trench depth is increased or the gate width (W direction) is reduced to increase the effective gate width, the gate length (L length direction) ) Cannot be reduced, the driving ability cannot be obtained more than expected, and the area of the transistor cannot be reduced. This is a feature of having a trench because the reduction in L length makes the difference in effective channel length distance on the top, side and bottom surfaces of the trench noticeable, and current flows preferentially on the top surface of the trench. This is because the current at the bottom surface decreases.

そこで、本発明の目的は、トレンチを有する半導体装置のＭＯＳトランジスタのL長を縮小してもトレンチ底面での電流経路が確保でき、想定した駆動能力が得られるようにすること、つまり駆動能力の減少を抑制することである。   Therefore, an object of the present invention is to ensure a current path at the bottom of the trench even when the L length of the MOS transistor of the semiconductor device having a trench is reduced, and to obtain an assumed drive capability, that is, drive capability. It is to suppress the decrease.

上記課題を解決するために、本発明は次の手段を用いた。
（１）第１導電型半導体基板と、前記第１導電型半導体基板上の所定の領域に形成された第２導電型埋め込み層と、前記第２導電型埋め込み層および前記第１導電型半導体基板の上に形成された第１導電型エピタキシャル成長層と、前記第１導電型エピタキシャル成長層に形成された、形成されるトランジスタのゲート幅方向に並んで配置された、その底部は前記第２導電型埋め込み層に達するトレンチと、ゲート絶縁膜を介して前記トレンチの内部及び上面と前記トレンチに隣接する第１導電型エピタキシャル成長層の表面部分に形成されたゲート電極と、前記ゲート電極の一方の側に形成された第２導電型のソース高濃度拡散層と、前記ゲート電極の他方の側に形成された第２導電型のドレイン高濃度拡散層と、を有する半導体装置とした。
（２）第１導電型半導体基板の所定の領域に第２導電型埋め込み層を形成する工程と、前記第２導電型埋め込み層および前記第１導電型半導体基板の上に第１導電型エピタキシャル成長層を形成する工程と、前記第１導電型エピタキシャル成長層に、形成されるトランジスタのゲート幅方向に並んで、その底部が前記第２導電型埋め込み層に達するようにトレンチを形成する工程と、ゲート絶縁膜を形成する工程と、前記ゲート絶縁膜を介して前記トレンチの内部及び上面と前記トレンチに隣接する第１導電型エピタキシャル成長層の表面部分にゲート電極を形成する工程と、前記ゲート電極の一方の側に第２導電型のソース高濃度拡散層、他方の側に第２導電型のドレイン高濃度拡散層とを形成する工程と、を含む半導体装置の製造方法とした。 In order to solve the above problems, the present invention uses the following means.
(1) A first conductivity type semiconductor substrate, a second conductivity type buried layer formed in a predetermined region on the first conductivity type semiconductor substrate, the second conductivity type buried layer, and the first conductivity type semiconductor substrate The first conductivity type epitaxial growth layer formed on the first conductivity type epitaxial growth layer and the transistor formed on the first conductivity type epitaxial growth layer are arranged side by side in the gate width direction. A trench reaching the layer, a gate electrode formed on the inside and upper surface of the trench and a surface portion of the first conductivity type epitaxial growth layer adjacent to the trench via a gate insulating film, and formed on one side of the gate electrode A second conductive type high concentration source diffusion layer and a second conductive type high concentration drain layer formed on the other side of the gate electrode. .
(2) forming a second conductive type buried layer in a predetermined region of the first conductive type semiconductor substrate; and a first conductive type epitaxial growth layer on the second conductive type buried layer and the first conductive type semiconductor substrate. Forming a trench in the first conductivity type epitaxial growth layer so as to be aligned in the gate width direction of the transistor to be formed so that the bottom portion reaches the second conductivity type buried layer, and gate insulation A step of forming a film, a step of forming a gate electrode inside and on the upper surface of the trench and a surface portion of the first conductivity type epitaxial growth layer adjacent to the trench through the gate insulating film, and one of the gate electrodes Forming a second conductivity type source high-concentration diffusion layer on the side and a second conductivity type drain high-concentration diffusion layer on the other side, and a method for manufacturing a semiconductor device, It was.

本発明は、トレンチを有するＭＯＳトランジスタのL長を縮小しても駆動能力の減少を抑制可能であるという特徴である。トランジスタのL長と同じ距離かそれより短い距離の深さのトレンチを有すること、さらにトレンチの底部に埋め込み層を用いることで、ソース高濃度拡散層下端あるいはドレイン高濃度拡散層下端からトレンチ底面までの実効的なチャネル長を最短L長のトレンチ上面よりも短くすることである。これによって、上記ソースあるいはドレインの高濃度拡散層に接する側面から埋め込み層を用いてトレンチ底面での電流経路を保持させることで駆動能力を向上させる。したがって、ゲート長が縮小された場合でも駆動能力の減少を抑制する効果がある。   The present invention is characterized in that a reduction in driving capability can be suppressed even if the L length of a MOS transistor having a trench is reduced. By having a trench with a depth equal to or shorter than the L length of the transistor and using a buried layer at the bottom of the trench, from the bottom of the source high-concentration diffusion layer or the bottom of the drain high-concentration diffusion layer to the bottom of the trench Is to make the effective channel length shorter than the shortest L-long trench upper surface. Thus, the driving capability is improved by maintaining the current path at the bottom of the trench using the buried layer from the side surface in contact with the high concentration diffusion layer of the source or drain. Therefore, even when the gate length is reduced, there is an effect of suppressing a decrease in driving capability.

以下、本発明の実施の形態を図面に基づいて説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１は本発明の第１の実施例の半導体装置を示す模式図である。図１（A）はトレンチ６を有するＭＯＳトランジスタの平面模式図である。図中のトレンチ６以外のプレーナー型トランジスタの構造にあたるA-A'に沿った断面模式図を図１（B）に示す。図中のトレンチ６のB-B'に沿った断面模式図を図１（C）に示す。図１（B）では、第１導電型の半導体基板１の上の所定の領域にのみ部分的に第２導電型の埋め込み層２が形成され、その上には半導体基板と同じ導電型のエピタキシャル成長層３が形成されている。エピタキシャル成長層３の上表面にはゲート酸化膜７を介してゲート長がＬであるゲート電極８が設けられている。そして、ゲート電極８のゲート長Ｌだけ離れて対面する領域には、一方の領域に第２導電型のソース高濃度拡散層９、そして他方には第２導電型のドレイン高濃度拡散層１０が形成される。この場合のソース高濃度拡散層９とドレイン高濃度拡散層１０との間の電流経路は図中の矢印Ａである。   FIG. 1 is a schematic diagram showing a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a schematic plan view of a MOS transistor having a trench 6. FIG. 1B shows a schematic cross-sectional view along AA ′ corresponding to the structure of the planar transistor other than the trench 6 in the drawing. FIG. 1C shows a schematic cross-sectional view taken along the line BB ′ of the trench 6 in the drawing. In FIG. 1B, a second conductivity type buried layer 2 is partially formed only in a predetermined region on the first conductivity type semiconductor substrate 1, and the same conductivity type epitaxial growth as that of the semiconductor substrate is formed thereon. Layer 3 is formed. A gate electrode 8 having a gate length L is provided on the upper surface of the epitaxial growth layer 3 via a gate oxide film 7. In a region facing the gate electrode 8 apart by the gate length L, the second conductivity type source high concentration diffusion layer 9 is provided in one region, and the second conductivity type drain high concentration diffusion layer 10 is provided in the other region. It is formed. In this case, the current path between the source high concentration diffusion layer 9 and the drain high concentration diffusion layer 10 is an arrow A in the figure.

図１（Ｃ）はトレンチ６を有する領域の断面図であり、第１導電型の半導体基板１の上に部分的に第２導電型の埋め込み層２が形成され、その上には半導体基板と同じ導電型のエピタキシャル成長層３が形成されている。エピタキシャル成長層３にはトレンチ６が埋め込み層２に接するように設けられている。ゲート長方向で埋め込み層２とトレンチ６の長さを比較すると、埋め込み層２の長さはトレンチ６の長さと同等以上であれば良い。トレンチ６の側面にはソース高濃度拡散層９およびドレイン高濃度拡散層１０が形成され、トレンチ６内面とソース高濃度拡散層９表面とドレイン高濃度拡散層１０表面にはゲート絶縁膜７が設けられており、トレンチ６の中にはゲート電極８が充填されている。この構造では、矢印Bで示す電流経路と、ソース高濃度拡散層９から矢印Ｄから埋め込み層２を経由して矢印Ｅからドレイン高濃度拡散層１０に至る電流経路（以下、電流経路Ｃ'と呼ぶ）が考えられる。このとき、ソース高濃度拡散層９と埋め込み層２との距離（＝ドレイン高濃度拡散層１０と埋め込み層２との距離）がゲート長と同等以下の長さであれば、電流経路Ｃ'にも電流が流れやすくなる。このようにすることで、ＭＯＳトランジスタの駆動能力を向上させることができる。   FIG. 1C is a cross-sectional view of a region having a trench 6, in which a second conductivity type buried layer 2 is partially formed on a first conductivity type semiconductor substrate 1, and a semiconductor substrate and An epitaxial growth layer 3 of the same conductivity type is formed. The epitaxial growth layer 3 is provided with a trench 6 in contact with the buried layer 2. When the lengths of the buried layer 2 and the trench 6 are compared in the gate length direction, the length of the buried layer 2 may be equal to or greater than the length of the trench 6. A source high-concentration diffusion layer 9 and a drain high-concentration diffusion layer 10 are formed on the side surfaces of the trench 6, and a gate insulating film 7 is provided on the inner surface of the trench 6, the surface of the source high-concentration diffusion layer 9, and the surface of the drain high-concentration diffusion layer 10. The trench 6 is filled with a gate electrode 8. In this structure, a current path indicated by an arrow B and a current path from the source high-concentration diffusion layer 9 through the buried layer 2 to the drain high-concentration diffusion layer 10 from the arrow D (hereinafter referred to as current path C ′). Can be considered). At this time, if the distance between the source high-concentration diffusion layer 9 and the buried layer 2 (= the distance between the drain high-concentration diffusion layer 10 and the buried layer 2) is equal to or shorter than the gate length, the current path C ′ Even the current will flow easily. By doing so, the driving capability of the MOS transistor can be improved.

図２は第１の実施例の半導体装置を製造するための工程フロー図である。ここでは、図１（Ｃ）に対応する断面図を用いて説明する。   FIG. 2 is a process flow diagram for manufacturing the semiconductor device of the first embodiment. Here, description is made with reference to a cross-sectional view corresponding to FIG.

図２（A）において、まず第１導電型半導体基板、例えばP型半導体基板１、例えばホウ素添加した抵抗率２０Ωcmから３０Ωcmの不純物濃度の半導体基板の所定の領域に、第２導電型埋め込み層２を、例えばN型埋め込み層であれば砒素、燐、アンチモンなどの不純物を用いて濃度は例えば１×１０18atoms/cm3程度の濃度くらいから１×１０21atoms/cm3程度で形成する。なお、第２導電型埋め込み層２が例えばP型埋め込み層ならホウ素などの不純物を用いれば良い。次いで、埋め込み層２を間に挟むように、半導体基板１と埋め込み層２の上に第1導電型エピタキシャル成長層３を形成する。成長層の膜厚は例えば数μmから数十μmである。エピタキシャル成長層３の表面にはLOCOS法によりLOCOS酸化膜４を形成させる。 In FIG. 2A, first, a second conductivity type buried layer 2 is formed in a predetermined region of a first conductivity type semiconductor substrate, for example, a P type semiconductor substrate 1, for example, a semiconductor substrate having a boron-doped resistivity of 20 Ωcm to 30 Ωcm. For example, in the case of an N-type buried layer, an impurity such as arsenic, phosphorus, or antimony is formed with a concentration of, for example, about 1 × 10 18 atoms / cm 3 to about 1 × 10 21 atoms / cm 3 . For example, if the second conductivity type buried layer 2 is a P-type buried layer, an impurity such as boron may be used. Next, a first conductivity type epitaxial growth layer 3 is formed on the semiconductor substrate 1 and the buried layer 2 so as to sandwich the buried layer 2 therebetween. The film thickness of the growth layer is, for example, several μm to several tens μm. A LOCOS oxide film 4 is formed on the surface of the epitaxial growth layer 3 by the LOCOS method.

次に図２（B）に示すように、トレンチエッチングのためにマスク５でパターニングをおこなう。このマスク５は、例えば膜厚は数十nm〜数百nmの熱酸化膜、あるいは膜厚は数百nm〜１μmとした堆積酸化膜のどちらでも可能であり、熱酸化膜および堆積酸化膜の積層構造でも可能である。さらに、マスク５はレジスト膜あるいは窒化膜でも問題はない。パターニングされたマスク５を用いてエッチングによりトレンチ６を形成する。このとき、トレンチ６は埋め込み層２に接するように形成する。その後マスク５を除去した後、図２（C）に示すようにゲート絶縁膜７、例えば膜厚が数百〜数千Åの熱酸化膜を形成する。さらにここでは、上述の第２導電型埋め込み層２の濃度が中濃度から高濃度程度の場合、第２導電型埋め込み層２の表面において熱酸化膜厚が厚くなることから、自動的にゲート絶縁膜７と第２導電型埋め込み層２間での容量を低減させることが可能である。   Next, as shown in FIG. 2B, patterning is performed with a mask 5 for trench etching. The mask 5 can be, for example, a thermal oxide film having a film thickness of several tens of nm to several hundreds nm, or a deposited oxide film having a film thickness of several hundred nm to 1 μm. A laminated structure is also possible. Further, there is no problem even if the mask 5 is a resist film or a nitride film. A trench 6 is formed by etching using the patterned mask 5. At this time, the trench 6 is formed in contact with the buried layer 2. Then, after removing the mask 5, as shown in FIG. 2C, a gate insulating film 7, for example, a thermal oxide film having a film thickness of several hundreds to several thousands is formed. Further, here, when the concentration of the second conductivity type buried layer 2 is about medium to high, the thermal oxide film thickness is increased on the surface of the second conductivity type buried layer 2, so that the gate insulation is automatically performed. It is possible to reduce the capacitance between the film 7 and the second conductivity type buried layer 2.

次に、図２（D）に示すように多結晶シリコンゲート膜を好ましくは膜厚を１００nm〜５００nmで堆積し、プリデポあるいはイオン注入法により不純物を導入してゲート電極８とする。ここでの導電型は例えば第１導電型でも第２導電型でも可能である。それにレジスト膜９でパターニングして、図２（E）に示すようなトレンチ６を有するトランジスタ構造が整う。引き続き、図２（E）に示すように、セルフアライン法でソース領域およびドレイン領域を形成するための不純物添加を行う。ここでのセルフアライン法は本発明の本質とは関係ない。ソース領域およびドレイン領域の不純物添加は例えば導電型がN型なら例えば砒素あるいは燐を好ましくは１×１０15atoms/cm2から１×１０16atoms/cm2のドーズ量でイオン注入する。一方で、導電型がP型ならホウ素あるいはニフッ化ホウ素を好ましくは１×１０15atoms/cm2から１×１０16atoms/cm2のドーズ量でイオン注入する。さらに、ここでのソース領域およびドレイン領域への不純物添加は、トレンチ６を有しない同一チップ内のＭＯＳトランジスタと同一条件で同時におこなうことが可能である。その後、図２（F）に示すように、８００℃〜１０００℃で数時間熱処理することで、ソース高濃度拡散層９およびドレイン高濃度拡散層１０を形成させる。以上で第２導電型埋め込み層２とトレンチ６を有するＭＯＳトランジスタが製造される。 Next, as shown in FIG. 2D, a polycrystalline silicon gate film is preferably deposited to a thickness of 100 nm to 500 nm, and an impurity is introduced by predeposition or ion implantation to form the gate electrode 8. The conductivity type here may be, for example, the first conductivity type or the second conductivity type. Then, patterning is performed with a resist film 9 to complete a transistor structure having a trench 6 as shown in FIG. Subsequently, as shown in FIG. 2E, an impurity is added for forming a source region and a drain region by a self-alignment method. The self-alignment method here has nothing to do with the essence of the present invention. For example, if the conductivity type is N-type, for example, arsenic or phosphorus is preferably ion-implanted at a dose of 1 × 10 15 atoms / cm 2 to 1 × 10 16 atoms / cm 2 . On the other hand, if the conductivity type is P type, boron or boron difluoride is preferably ion-implanted at a dose of 1 × 10 15 atoms / cm 2 to 1 × 10 16 atoms / cm 2 . Further, the addition of impurities to the source region and the drain region here can be performed simultaneously under the same conditions as those of the MOS transistor in the same chip that does not have the trench 6. Thereafter, as shown in FIG. 2 (F), a high-concentration source diffusion layer 9 and a high-concentration drain diffusion layer 10 are formed by heat treatment at 800 ° C. to 1000 ° C. for several hours. Thus, the MOS transistor having the second conductivity type buried layer 2 and the trench 6 is manufactured.

図３（Ａ）は第２の実施例の半導体装置を示す模式図である。実施例１でも説明したように、トレンチ６と第２導電型埋め込み層２との位置関係は、トレンチ６側面の端部Ｇが第２導電型埋め込み層２の側面の端部Ｆより内側であることが望ましいが、ソース高濃度拡散層下端およびドレイン高濃度拡散層下端から第２導電型埋め込み層２までの距離Ｈがゲート長Ｌ'と同等以下の長さであれば、トレンチ６の底部の電流経路を優先的に電流が流れることになる。よって、トレンチ６側面の端部Ｇが第２導電型埋め込み層２の側面の端部Ｆより外側であっても、ソース高濃度拡散層下端およびドレイン高濃度拡散層下端から第２導電型埋め込み層２の側面の端部Ｆまでの距離Ｈがゲート長Ｌ'と同じかそれより短いという条件を満たせば、トレンチ６の底部にも電流が流れ、駆動能力が向上する。   FIG. 3A is a schematic diagram showing the semiconductor device of the second embodiment. As described in the first embodiment, the positional relationship between the trench 6 and the second conductivity type buried layer 2 is such that the end portion G on the side surface of the trench 6 is inside the end portion F on the side surface of the second conductivity type buried layer 2. However, if the distance H from the lower end of the source high concentration diffusion layer and the lower end of the drain high concentration diffusion layer to the second conductivity type buried layer 2 is equal to or shorter than the gate length L ′, Current flows preferentially through the current path. Therefore, even if the end portion G on the side surface of the trench 6 is outside the end portion F on the side surface of the second conductivity type buried layer 2, the second conductivity type buried layer is formed from the lower end of the source high concentration diffusion layer and the lower end of the drain high concentration diffusion layer. If the condition that the distance H to the end F of the side surface 2 is equal to or shorter than the gate length L ′ is satisfied, a current flows also to the bottom of the trench 6 and the driving capability is improved.

図３（Ｂ）はトレンチ６の長さと第２導電型埋め込み層２の長さが同じに形成されており、トレンチ６側面の端部Ｇが第２導電型埋め込み層２の側面の端部Ｆが同一直線状に揃っている態様を示している。この場合でもソース高濃度拡散層下端およびドレイン高濃度拡散層下端から第２導電型埋め込み層２までの距離Ｈがゲート長Ｌ'と同じかそれよりも短いという条件を満たせば、トレンチ６の底部にも電流が流れ、駆動能力が向上する。   3B, the length of the trench 6 and the length of the second conductive type buried layer 2 are formed to be the same, and the end G of the side surface of the trench 6 is the end F of the side surface of the second conductive type buried layer 2. Are shown in the same straight line. Even in this case, if the condition that the distance H from the lower end of the source high concentration diffusion layer and the lower end of the drain high concentration diffusion layer to the second conductivity type buried layer 2 is equal to or shorter than the gate length L ′ is satisfied, Current also flows, and the driving ability is improved.

以上説明したように、トレンチの底部に埋め込み層を設け、ソース高濃度拡散層およびドレイン高濃度拡散層と埋め込み層との距離を、ゲート長と同じかそれより短くすれば、トレンチ底部にも電流が流れ、半導体装置の駆動能力が向上する。   As described above, if a buried layer is provided at the bottom of the trench and the distances between the source high-concentration diffusion layer and the drain high-concentration diffusion layer and the buried layer are equal to or shorter than the gate length, the current also flows in the trench bottom. This improves the driving capability of the semiconductor device.

本発明の第1の実施例の半導体装置を示す模式的平面図および模式的断面図1 is a schematic plan view and a schematic cross-sectional view showing a semiconductor device according to a first embodiment of the present invention; 本発明の第１の実施例の半導体装置を製造するための工程フロー図Process flow chart for manufacturing the semiconductor device of the first embodiment of the present invention 本発明の第２の実施例の半導体装置を示す模式的断面図Schematic sectional view showing a semiconductor device according to a second embodiment of the present invention. 従来の半導体装置を示す模式図Schematic diagram showing a conventional semiconductor device

符号の説明Explanation of symbols

１、１１ 第１導電型半導体基板
２ 第２導電型埋め込み層
３ 第１導電型エピタキシャル成長層
４、１２ LOCOS酸化膜
５ マスク
６、１３ トレンチ
７、１４ ゲート絶縁膜
８、１５ ゲート電極
９、１６ ソース高濃度拡散層
１０、１７ ドレイン高濃度拡散層
Ｆ 第２導電型埋め込み層の側面の端部
Ｇ トレンチ側面の端部
Ｌ、Ｌ' ゲート長 DESCRIPTION OF SYMBOLS 1, 11 1st conductivity type semiconductor substrate 2 2nd conductivity type buried layer 3 1st conductivity type epitaxial growth layer 4, 12 LOCOS oxide film 5 Mask 6, 13 Trench 7, 14 Gate insulating film 8, 15 Gate electrode 9, 16 Source High-concentration diffusion layers 10 and 17 Drain high-concentration diffusion layer F End portion G on the side surface of the second conductivity type buried layer End portion L and L 'on the side surface of the trench

Claims (7)

第１導電型半導体基板と、
前記第１導電型半導体基板上の所定の領域に形成された第２導電型埋め込み層と、
前記第２導電型埋め込み層および前記第１導電型半導体基板の上に形成された第１導電型エピタキシャル成長層と、
前記第１導電型エピタキシャル成長層に形成された、形成されるトランジスタのゲート幅方向に並んで配置された、その底部は前記第２導電型埋め込み層に達するトレンチと、
ゲート絶縁膜を介して前記トレンチの内部及び上面と前記トレンチに隣接する第１導電型エピタキシャル成長層の表面部分に形成されたゲート電極と、
前記ゲート電極の一方の側に形成された第２導電型のソース高濃度拡散層と、
前記ゲート電極の他方の側に形成された第２導電型のドレイン高濃度拡散層と、
を有する半導体装置。 A first conductivity type semiconductor substrate;
A second conductivity type buried layer formed in a predetermined region on the first conductivity type semiconductor substrate;
A first conductivity type epitaxial growth layer formed on the second conductivity type buried layer and the first conductivity type semiconductor substrate;
A trench formed in the first conductivity type epitaxial growth layer, arranged side by side in the gate width direction of the transistor to be formed, and a bottom portion of the trench reaching the second conductivity type buried layer;
A gate electrode formed on the inside and upper surface of the trench and a surface portion of the first conductivity type epitaxial growth layer adjacent to the trench via a gate insulating film;
A second conductivity type source high-concentration diffusion layer formed on one side of the gate electrode;
A second conductivity type drain high concentration diffusion layer formed on the other side of the gate electrode;
A semiconductor device. 前記トレンチの深さは形成されるトランジスタのゲート長より短いか同じである請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a depth of the trench is shorter than or equal to a gate length of a transistor to be formed. 前記トレンチの位置は、前記第２導電型埋め込み層の側面の端部より内側である請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein a position of the trench is on an inner side than an end of a side surface of the second conductivity type buried layer. 前記トレンチの位置は、前記第２導電型埋め込み層の側面の端部と同一面である請求項２記載の半導体装置。   The semiconductor device according to claim 2, wherein a position of the trench is flush with an end of a side surface of the second conductivity type buried layer. 前記トレンチの位置は、前記第２導電型ソース高濃度拡散層下端あるいはドレイン高濃度拡散層下端から前記第２導電型埋め込み層までの距離がトランジスタのゲート長よりも短い場合、前記第２導電型埋め込み層の側面の端部より外側に形成される請求項２に記載の半導体装置の製造方法   When the distance from the lower end of the second conductivity type source high-concentration diffusion layer or the lower end of drain high-concentration diffusion layer to the second conductivity type buried layer is shorter than the gate length of the transistor, the trench is located at the second conductivity type. The method for manufacturing a semiconductor device according to claim 2, wherein the semiconductor device is formed outside an end of a side surface of the buried layer. 前記第２導電型埋め込み層の濃度は１×１０18atoms/cm3から１×１０21atoms/cm3程度である請求項１ないし５のいずれか１項に記載の半導体装置。 6. The semiconductor device according to claim 1, wherein the concentration of the second conductivity type buried layer is about 1 × 10 18 atoms / cm 3 to 1 × 10 21 atoms / cm 3 . 第１導電型半導体基板の所定の領域に第２導電型埋め込み層を形成する工程と、
前記第２導電型埋め込み層および前記第１導電型半導体基板の上に第１導電型エピタキシャル成長層を形成する工程と、
前記第１導電型エピタキシャル成長層に、形成されるトランジスタのゲート幅方向に並んで、その底部が前記第２導電型埋め込み層に達するようにトレンチを形成する工程と、
ゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜を介して前記トレンチの内部及び上面と前記トレンチに隣接する第１導電型エピタキシャル成長層の表面部分にゲート電極を形成する工程と、
前記ゲート電極の一方の側に第２導電型のソース高濃度拡散層、他方の側に第２導電型のドレイン高濃度拡散層とを形成する工程と、
を含む半導体装置の製造方法。 Forming a second conductivity type buried layer in a predetermined region of the first conductivity type semiconductor substrate;
Forming a first conductivity type epitaxial growth layer on the second conductivity type buried layer and the first conductivity type semiconductor substrate;
Forming a trench in the first conductivity type epitaxial growth layer so that the bottom of the first conductivity type epitaxial growth layer reaches the second conductivity type buried layer in the gate width direction of the transistor to be formed;
Forming a gate insulating film;
Forming a gate electrode on the inside and upper surface of the trench and the surface portion of the first conductivity type epitaxial growth layer adjacent to the trench through the gate insulating film;
Forming a second conductivity type source high-concentration diffusion layer on one side of the gate electrode and a second conductivity type drain high-concentration diffusion layer on the other side;
A method of manufacturing a semiconductor device including:
JP2008044392A 2008-02-26 2008-02-26 Semiconductor device and manufacturing method thereof Expired - Fee Related JP5159365B2 (en)

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