JP3550019B2 - Semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device using polycrystalline silicon, and more particularly to a semiconductor device having a flat channel region.
[0002]
[Prior art]
In recent years, with the development of integration technology, various portable devices such as mobile phones and electronic organizers have been used.
[0003]
In this type of portable device, a power MOSFET is used as a low withstand voltage and low resistance switching element from the viewpoint of using a battery as a power supply and reducing switching loss.
[0004]
In this type of portable equipment, the power supply voltage tends to decrease from the viewpoint of low power consumption and long life, and a low on-resistance is also required for a power MOSFET serving as a switching element.
[0005]
As described above, the semiconductor device for switching is required to have a low on-resistance so that it can be used for portable equipment and the like.
[0006]
On the other hand, a lateral MOSFET is known as a semiconductor device for switching at a low withstand voltage of about 8 V to 60 V.
[0007]
FIG. 69 is a plan view showing the structure of this type of lateral MOSFET, and FIG. 70 is a sectional view taken along line 70-70 of FIG. In this lateral MOSFET, a p-type well layer 2 is selectively formed on the surface of a p-type semiconductor substrate 1, and an n-type drain layer 3 is selectively formed on the p-type well layer 2. An n-type source layer 4 is formed on the p-type well layer 2 at a position away from the n-type drain layer 3.
[0008]
On the p-type well layer 2 between the n-type drain layer 3 and the n-type source layer 4, a gate insulating film 5 is formed. A gate electrode 6 is formed on the gate insulating film 5. On the n-type drain layer 3, a drain electrode 7 is formed. A source electrode 8 is formed on the p-type well layer 2 and the n-type source layer 4.
[0009]
This lateral MOSFET operates as follows.
[0010]
When a positive voltage that is more positive than the source is applied to the gate electrode 6 when a positive voltage is applied to the drain electrode 7 and a negative voltage is applied to the source electrode 8, the surface of the p-type well layer 2 in contact with the gate insulating film 5 Is inverted to n-type, and electrons flow from the n-type source layer 4 to the n-type drain layer 3 via the inversion layer. That is, the element becomes conductive.
[0011]
When such a lateral MOSFET is used for switching a large current, it is important to reduce the resistance in the ON state (ON resistance) in order to suppress the loss. Here, the resistance of the channel portion 109 occupies most of the on-resistance of the lateral MOSFET. Therefore, in order to reduce the on-resistance of the lateral MOSFET, the channel width may be increased. However, when the channel width is increased, the area of the lateral MOSFET is increased.
[0012]
For example, in a lateral M0SFET having a low withstand voltage of 30 V, the on-resistance is 40 mΩ · mm.²And there is a limit in further reducing the on-resistance.
[0013]
As described above, in the lateral MOSFET, there is a problem that increasing the channel width increases the element area. Further, in the lateral type MOSFET, current flows only on the surface, and there is a limit in reducing the on-resistance.
[0014]
Further, a semiconductor device having a vertical trench structure will be described. FIG. 71 is a cross-sectional view showing a configuration of a semiconductor device having a vertical trench structure. In this semiconductor device, an n − -type base layer 12 is formed on an n + -type substrate 11 of single crystal silicon, and a p-type base layer (well) 13 is formed on the surface of the n − -type base layer 12. An n + -type source layer 14 is selectively formed on the surface of the p-type base layer 13. A trench 15 is selectively formed on the surface of the n + -type source layer 14 to a depth reaching the n-type substrate 11. A gate electrode 17 is buried in the trench 15 via an insulating film 16. On such a semiconductor layer surface, an insulating layer 18 is selectively formed so as to expose the p-type base layer 13 and the n + -type source layer 14 in the vicinity thereof.
[0015]
A source electrode 19 is formed so as to contact the surfaces of the p-type base layer 13 and the n + -type source layer 14 between the insulating layers. In addition, a drain electrode 20 is formed on the n + type substrate 11 opposite to the source electrode 19.
[0016]
In such a MOSFET having the vertical trench structure, the interval W between the trenches 15 is at least about 2 μm. Such a MOSFET is formed such that a source electrode 19 contacts both layers of the n + -type source layer 14 and the p-type base layer 13 to electrically short-circuit both layers in order to prevent the operation of a parasitic npn transistor. I have.
[0017]
In addition, in the structure shown in FIG.⁺n⁻n⁺A structure has been proposed as shown in FIG. But n⁺n⁻n⁺Since the structure requires a wide interval W between trenches, there is a problem that the breakdown voltage is reduced.
[0018]
For example, n⁺n⁻n⁺When a MOSFET having a structure is formed of single crystal silicon, even if a narrow trench interval W of 0.5 μm or less is formed, holes generated in the depletion layer are n⁻Since it is accumulated in the mold base layer 12 and causes a parasitic bipolar operation, there is a problem that the breakdown voltage is deteriorated. For this reason, the breakdown voltage is lower than in the case of being formed from polycrystalline silicon.
[0019]
[Problems to be solved by the invention]
As described above, the semiconductor device has a problem that there is a limit in reducing the on-resistance without increasing the element area.
[0020]
The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device that can be used as a switching element of a portable device and that can realize low withstand voltage and low on-resistance.
[0021]
Another object of the present invention is to provide a semiconductor device capable of greatly reducing the on-resistance without increasing the area of the element.
[0022]
[Means for Solving the Problems]
The gist of the present invention isIn a semiconductor device having a vertical trench structure, a channel region between trenches and a contact region with a source electrode are formed separately, so that a trench interval can be reduced, and by being formed of polycrystalline silicon, The structure eliminates the parasitic bipolar transistor operation. As a result, in a semiconductor device having a structure with a narrow trench interval, a high switching speed and a cutoff of a large current can be simultaneously realized.
[0026]
The present invention as described aboveBone ofBased on the child, concrete measures such as the following are taken.
[0038]
Claim1And a second conductive type substrate formed on the drain electrode, a second conductive type high-resistance layer formed on the second conductive type substrate, and a second conductive type high resistance layer formed on the second conductive type substrate. A second conductivity type buried layer having a lower resistance than the high resistance layer and formed in the second conductivity type high resistance layer; and a second conductivity type drain formed on the surface of the second conductivity type high resistance layer. A first conductive type base layer formed on the surface of the second conductive type high resistance layer in a region different from the second conductive type drain layer; and a second conductive layer formed on the surface of the first conductive type base layer. A conductive type source layer; a source electrode formed on the second conductive type source layer; and a middle of the second conductive type high resistance layer between the second conductive type source layer and the second conductive type drain layer. Buried via a gate insulating film in a plurality of trenches formed to a depth of A semiconductor device provided with and.
[0039]
Claims2The invention corresponding to the first aspect includes a drain electrode, a second conductivity type drain layer formed on the drain electrode, a second conductivity type high resistance layer formed on the second conductivity type drain layer, and a second conductivity type high resistance layer. A first conductive type base layer formed on the resistance layer, a linear first conductive type contact layer formed on the first conductive type base layer, and a first conductive type contact layer in a region different from the first conductive type contact layer; A second conductive type source layer formed on the surface of the conductive type base layer; and a plurality of second conductive type source layers formed on the surface of the second conductive type source layer having a depth reaching the drain electrode from the surface of the second conductive type source layer. A gate electrode buried in the trench via an insulating film, and a source electrode formed in contact with the first conductive type contact layer and the second conductive type source layer near the first conductive type contact layer; Drain layer, second conductive type high resistance layer, first conductive type Type base layer, a first conductive-type contact layer and the second conductive type source layer is a semiconductor device which is formed of polycrystalline silicon.
[0040]
Claims3The invention corresponding to the claim2Is a semiconductor device in which the longitudinal direction of the first conductivity type contact layer and the longitudinal direction of each trench are substantially orthogonal to each other.
[0041]
Therefore, the claims1~ Claim3According to the invention corresponding to any one of the above, the need for the two-layer wiring on the upper surface is unnecessary, and thus the wiring resistance which normally becomes a problem in the case of Al wiring or the like can be reduced.
[0042]
Claims1According to the invention, the channel width can be increased in accordance with the trench depth and the installation density while keeping the element area the same, so that the resistance of the channel portion of the element is reduced, that is, the resistance of the element itself is reduced. Therefore, the on-resistance can be reduced.
[0043]
Claims1According to the invention corresponding to (1), the provision of the low resistance second conductivity type buried layer allows the current to expand and flow over the entire channel width, so that the on-resistance can be easily and reliably reduced.
[0044]
Claims2According to the invention corresponding to (1), since the gate electrode having the trench structure and the contact region to the source electrode are formed apart from each other, a narrow trench interval can be realized. Since each semiconductor layer is formed of polycrystalline silicon, the operation of a parasitic transistor is eliminated, so that a high switching speed and a high current interruption can be realized at the same time.
[0045]
Claims3Since the longitudinal direction of the first conductivity type contact layer and the longitudinal direction of each trench are substantially orthogonal to each other,2And the electrons injected from the source electrode can smoothly flow through the channel region between the trenches.
[0046]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this description, polycrystalline silicon is used in the first to sixth and eighteenth embodiments, and single crystal silicon is used in the seventh to seventeenth and nineteenth to twenty-sixth embodiments. However, polycrystalline silicon may be used as appropriate in the fifteenth to seventeenth embodiments.
[0047]
(1st Embodiment)
FIG. 1 is a plan view showing the configuration of the semiconductor device according to the first embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. 1, and FIG. FIG. In this semiconductor device, an oxide film 22 is formed on a substrate 21, and a source electrode 23 and a drain electrode 24 are formed on the oxide film 22 in stripes.
[0048]
A high-resistance channel layer 25 made of polycrystalline silicon is formed between the source electrode 23 and the drain electrode 24. It is preferable that the channel layer 25 be formed as thin as about 500 nm from the viewpoint of improving the channel mobility. In the channel layer 25, a source layer 26 having a high impurity concentration is formed at one end contacting the source electrode 23, and a drain layer 27 having a high impurity concentration is formed at the other end contacting the drain electrode 24.
[0049]
On these source layer 26, channel layer 25, and drain layer 27, a gate electrode 29 having a buried structure surrounded by an oxide film 28 is arranged.
[0050]
Similarly, between the source electrode 23 and the drain electrode 24, a polycrystalline semiconductor layer 30 including a source layer 26, a channel layer 25 and a drain layer 27, and a buried gate electrode surrounded by an oxide film 28. 29 are alternately arranged.
[0051]
In a part of the region between the source electrode 23 and the drain electrode 24, the gate wiring layer 31 is formed to a depth reaching the oxide film 22 from the uppermost gate electrode 29.
[0052]
The gate wiring layer 31 is electrically connected to the gate electrode 29 as shown in FIG. 3, but is electrically insulated from the channel layer 25 via the oxide film 28.
[0053]
With the configuration as described above, the semiconductor device according to the present embodiment has the thin film of the channel layer 25 made of polycrystalline silicon interposed between the gate electrodes 29 of the buried structure, so that the channel layer 25 as a whole is turned on when in the ON state. Since high mobility can be realized, it can be used also as a switching element of a portable device, and low withstand voltage and low on-resistance can be realized.
[0054]
In addition, since the single-crystal MOSFET has a structure in which a plurality of channel layers 25 that can be expected to have the same high mobility as the single-crystal MOSFET are also arranged in parallel with each other, the on-resistance of the single-crystal MOSFET is higher than that of the single-crystal MOSFET. Low on-resistance can be realized.
[0055]
Further, since the thickness of the channel layer 25 is as thin as 0.8 μm or less, the entire thickness direction of the polycrystalline semiconductor layer becomes a channel, and channel mobility equivalent to that of a single-crystal silicon MOSFET is easily provided for each channel layer 25. In addition, since it can be reliably achieved, the on-resistance can be further reduced.
[0056]
(Second embodiment)
FIG. 4 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention. The same parts as those in FIGS. 1 to 3 are denoted by the same reference numerals, and detailed description thereof will be omitted. , The same symbols indicate the same kind of elements.
[0057]
That is, this semiconductor device is an n-channel MOSFET composed of a single-layer polycrystalline silicon channel sandwiched between upper and lower gates, unlike the multilayer channel structure shown in FIGS.
[0058]
Specifically, in this semiconductor device, an oxide film 22 and a first p + type gate electrode 29p are formed on a substrate 21. A gate wiring layer 31 and an oxide film 22a are selectively formed on the first p + type gate electrode 29p. On the oxide film 22a, an n + type source layer 26, an n− type channel layer 25n, and an n + type drain layer 27 are sequentially arranged in the lateral direction. A source electrode 23 is formed on the n + type source layer 26. On the n + type drain layer 27, a drain electrode 24 is formed.
[0059]
A second p + type gate electrode 32p is formed on a part of the n + type source layer 26, on the n− type channel layer 25n, and on a part of the n + type drain layer 27 via a gate oxide film 28. The first and second p + gate electrodes 29p and 32p are connected to each other via a gate wiring layer 31.
[0060]
With the above configuration, the same effects as those of the first embodiment can be obtained. In the present embodiment, the n + -type source layer 26 and the n + -type drain layer 27 are replaced with p + -type layers, respectively, and are replaced with p + -type source layers 26p and p + -type drain layers 27p. Needless to say.
[0061]
(Third embodiment)
FIG. 5 is a sectional view showing the configuration of the semiconductor device according to the third embodiment of the present invention, and FIG. 6 is a sectional view taken along line 6-6 of FIG.
[0062]
That is, this semiconductor device is a CMOS in which an n-channel MOSFET and a p-channel MOSFET are arranged in parallel.
[0063]
Specifically, oxide film 22 is formed on substrate 21, and n − -type high resistance layer 33 is formed on oxide film 22. In the n− type high resistance layer 33, a plurality of first p + type gate electrodes are selectively formed. Here, the n− type high resistance layer 33 is formed by controlling the addition of impurities so as to be n− type, and thereafter, each first p + is doped by impurity diffusion so as to be selectively p + type. A mold gate electrode 29p is formed. Since the n− type high resistance layer 33 is provided between each first p + type gate electrode 29p, it is electrically separated from the other first p + type gate electrode 29p.
[0064]
An oxide film 22a is formed on the n− type high resistance layer 33 and the first p + type gate electrode 29p, and an n-channel MOSFET and a p-channel MOSFET are formed on the oxide film 22a as described above. ing. The n-channel MOSFET and the p-channel MOSFET are provided such that the n- type channel layer 25n is located on the first p + type gate electrode 29p via the oxide film 22a.
[0065]
With the above configuration, the same effects as those of the first embodiment can be obtained. Further, in the present embodiment, as shown in FIG. 7, the same effect can be obtained even if the first p + type gate electrode 29p is modified to a configuration in which the first p + type gate electrode 29p is separated from each other by an oxide film 22a by LOCOS.
[0066]
(Fourth embodiment)
FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along line 9-9 of FIG. 3 shows a modified configuration.
[0067]
That is, in the present embodiment, the structure of the first embodiment is easily realized. Specifically, as shown in FIGS. 8 and 9, the source electrode is replaced with the gate electrode 29 having the buried structure. A p + type gate electrode 41p having an n− type high resistance layer 40 and insulated from both electrodes 23 and 24 is provided at a portion in contact with the drain electrode 23 and the drain electrode 24.
[0068]
Here, the p + -type gate electrode 41 p is made of polycrystalline silicon to which B (boron) is added, and B is not added to a portion in contact with the source electrode 23 and the drain electrode 24 without adding B. It is formed.
[0069]
The n + -type source layer 26 and the n + -type drain layer 27 at both ends of the n − -type channel layer 25n are formed by high-concentration P (phosphorus) ion implantation and annealing.
[0070]
According to the above configuration, the p + type gate electrode 41p is electrically insulated from the source electrode 23 and the drain electrode 24 by the n− type high resistance layer 40, and the n + type source layer 26 and the n + type Since the drain layer 27 is connected to the source electrode 23 and the drain electrode 24, respectively, in addition to the effects of the first embodiment, the steps relating to the buried structure can be omitted, and the manufacturing steps can be simplified.
[0071]
(Fifth embodiment)
FIG. 10 is a plan view showing the configuration of a semiconductor device according to the fifth embodiment of the present invention, FIG. 11 is a cross-sectional view taken along line 11-11 of FIG. 10, and FIG. 12 is 12-12 of FIG. FIG.
[0072]
This semiconductor device is a vertical polycrystalline silicon MOSFET in which polycrystalline silicon is deposited on a drain electrode 24 serving as a base material, a trench is dug, a trench surface is oxidized, and polycrystalline silicon serving as a gate is embedded. is there.
[0073]
Specifically, a first n + type polysilicon layer 51, an n− type polysilicon layer 52, and a second n + type polysilicon layer 53 are sequentially formed on the drain electrode 24. In the region of the second polycrystalline silicon layer 53 where the gate electrode is buried, the region selectively reaches the depth reaching the drain electrode 24 via the n − type polycrystalline silicon layer 52 and the first polycrystalline silicon layer 51. A trench is formed in the trench. An oxide film 54 is formed on the trench surface. After the oxide film 54 is formed, ap + -type gate electrode 55p is buried in the trench. Thereafter, as shown in FIG. 11, an oxide film 56 is selectively formed on the gate electrode 55p in a region where the source electrode 23 is formed. As shown in FIG. 12, an oxide film 57 is selectively formed on the second n + -type polycrystalline silicon layer 53 between the trenches in the region where the gate wiring layer 31 is formed.
[0074]
With the above configuration, the same effects as those of the first embodiment can be obtained. Further, the vertical element structure can omit the step of laminating many polycrystalline silicon layers. Thus, the manufacturing process can be simplified.
[0075]
(Sixth embodiment)
13 to 17 are cross-sectional views showing modified configurations of the semiconductor devices according to the first to fourth embodiments. CMOS circuits are formed on oxide films 22 and 22a in parallel with the semiconductor devices according to the respective embodiments. Is formed.
[0076]
Here, in the nMOS and each semiconductor device in the CMOS circuit, an n + type source layer 26 and an n + type drain layer 27 are simultaneously formed, respectively.
[0077]
In the CMOS circuit and each semiconductor device, an n-type channel layer 25n is simultaneously formed. Further, in the pMOS of the CMOS circuit and each semiconductor device, the p + source layer 26p, the p + drain layer 27p, and the p + gate electrode 32p are simultaneously formed, respectively.
[0078]
Therefore, according to the present embodiment, in addition to the effects of the first to fourth embodiments, an intelligent semiconductor device including a control circuit made of CMOS and a power element can be realized while making the manufacturing process common. . Since the semiconductor device according to the fifth embodiment has a configuration as shown in FIG. 18, the manufacturing process for the CMOS and the power element cannot be shared. An intelligent semiconductor device including a circuit and a power element can be realized.
[0079]
(Seventh embodiment)
FIG. 19 is a plan view showing the configuration of the lateral trench MOSFET according to the seventh embodiment of the present invention. FIG. 20A is a cross-sectional view taken along line 20A-20A of FIG. 20) is a sectional view taken along line 20B-20B in FIG. In this horizontal trench MOSFET, an n-type high resistance layer 112 is formed on a p-type substrate 111. A p-type well layer 113 is selectively formed on the n-type high resistance layer 112 in a stripe shape. On the surface of the p-type well layer 113, an n-type source layer 114 is selectively formed in a stripe shape. On the other hand, a striped n-type drain layer 115 is formed on the surface of the n-type high-resistance layer 112 at a position away from the n-type source layer 114 so as to be parallel to the n-type source layer 114.
[0080]
In an intermediate region extending from the end of the n-type drain layer 115 to the ends of the n-type high resistance layer 112, the p-type well layer 113, and the ends of the n-type source layer 114, the n-type high resistance A plurality of trenches (grooves) 116 are formed to a depth in the middle of the layer 112. Each of the trenches 116 has a stripe-shaped planar shape in a direction orthogonal to the n-type source layer 114 and the n-type drain layer 115, and is arranged substantially parallel to each other. The surface orientation of the surface of the trench 116 may be, for example, a (100) plane.
[0081]
A gate electrode 118 made of polysilicon is formed in the intermediate region between the drain and the source and in each trench 16 via a gate insulating film 117. On the n-type source layer 114, a source electrode 119 is formed. On the n-type drain layer 115, a drain electrode 120 is formed.
[0082]
Next, the operation of such a lateral trench MOSFET will be described.
[0083]
As described above, when a positive voltage that is more positive than the source is applied to the gate electrode 118 when a positive voltage is applied to the drain electrode 120 and a negative voltage is applied to the source electrode 119, the gate electrode 118 of the p-type well layer 113 is applied to the gate electrode 118. The contacted surface is inverted to n-type, and electrons are injected from the n-type source layer 114 to the n-type high-resistance layer 112 via the inversion layer, and flow through the n-type high-resistance layer 112 toward the n-type drain layer 115. , Reaches the n-type drain layer 115. That is, the element becomes conductive.
[0084]
At this time, a channel is also formed inside the n-type high resistance layer 112 along the trench 116, and the electrons e spread inside and flow, as shown in FIG. Therefore, the on-resistance can be reduced according to the width of the internal channel. The degree of reduction in the on-resistance depends on the element design, but can be expected to be 1/10 or less as compared with the conventional planar structure.
[0085]
For example, FIG. 21 is a diagram showing, on a logarithmic scale, the dependency of the trench interval on the on-resistance of a lateral trench MOSFET formed in single-crystal silicon. As shown in the figure, as the trench interval W2 becomes narrower, the channel width per unit area increases, so that the on-resistance can be reduced. In particular, when the trench interval W2 is in the range of 0.8 to 0.01 μm, it is preferable because the on-resistance is practically sufficiently low. However, a trench interval of 0.01 μm or less is not preferable because it lowers channel mobility under the influence of surface scattering and increases on-resistance.
[0086]
The on-resistance of the conventional 30 V withstand voltage horizontal planar MOSFET is 40 mΩ · mm.²And the on-resistance of the conventional vertical trench MOSFET is 30 mΩ · mm²It is.
[0087]
On the other hand, the on-resistance of the lateral trench MOSFET according to the present invention is actually 1 mΩ · mm if both the trench interval W2 and the trench width W1 are 0.1 μm.²The following can be expected. This value is 1/10 or less of the conventional vertical trench MOSFET. When both the trench interval W2 and the trench width W1 are 0.05 μm, the on-resistance of the lateral trench MOSFET according to the present invention is 0.3 mΩ · mm.²And it is reduced to 1/100 of the conventional vertical trench MOSFET.
[0088]
Thus, it can be seen that the lateral trench MOSFET according to the present invention is overwhelmingly superior to the vertical MOSFET using trenches of the same dimensions. Further, in general, since the characteristics of the horizontal element are lower than those of the vertical element, it can be seen that the effect of reducing the on-resistance according to the present invention is extremely remarkable.
[0089]
It should be noted that the horizontal trench MOSFET according to the present invention can have a lower on-resistance than a vertical element when a general vertical trench MOSFET has a withstand voltage lower than about 60 V. The reason is that in the lateral trench MOSFET according to the present invention, the interval between the trenches can be reduced as much as possible.
[0090]
For example, in a vertical trench MOSFET, as shown in FIG. 22, the n-type source layer 121 and the p-type contact layer 122 need to be in contact with the source electrode 123 at the top. Here, since the vertical trench MOSFET requires the contact hole 124 for contact, the trench interval W2 cannot be narrowed to 3 μm or less at present.
[0091]
On the other hand, in the lateral trench MOSFET, since there is no such restriction, the trench interval W2 can be reduced to about 0.1 μm, and the channel width per unit area is at least five times larger than that of the vertical trench MOSFET. As a result, the lateral trench MOSFET can reduce the on-resistance as described above.
[0092]
As described above, according to the present embodiment, the on-resistance can be reduced without increasing the element area.
[0093]
(Eighth embodiment)
FIG. 23 is a plan view showing the configuration of the lateral trench MOSFET according to the eighth embodiment of the present invention. FIG. 24A is a cross-sectional view taken along line 24A-24A of FIG. 24) is a sectional view taken along line 24B-24B in FIG. 23, 24 (A) and 24 (B), the same parts as those in FIG. 19 are denoted by the same reference numerals, detailed description thereof will be omitted, and only different parts will be described here. The following embodiments will be described so as to avoid duplication of the same contents.
[0094]
This embodiment is a modification of the seventh embodiment. As shown, the depth d of the trench 116 is made shallower than the p-type well layer 113, and the trench interval W2 and the trench width W1 are further reduced. The configuration is as follows.
[0095]
According to such a configuration, in addition to the effect of the seventh embodiment, when the trench interval W2 is 0.1 μm or less, the entire n-type high resistance layer 112 sandwiched between the trenches 116 becomes a channel. As a result, the on-resistance can be significantly reduced. This is an effect that can be achieved only by using the horizontal type.
[0096]
(Ninth embodiment)
FIG. 25 is a plan view showing the configuration of the lateral trench MOSFET according to the ninth embodiment of the present invention. FIG. 26A is a sectional view taken along line 26A-26A of FIG. ) Is a sectional view taken along line 26B-26B in FIG.
[0097]
This embodiment is a modification of the seventh embodiment. As shown, a p-type high resistance layer 131 is formed instead of the n-type high resistance layer 112. On the surface of the p-type high resistance layer 131 between the p-type well layer 113 and the n-type drain layer 114, an n-type RESURF diffusion layer 132 is formed.
[0098]
According to such a configuration, in addition to the effects of the seventh embodiment, a high withstand voltage can be achieved by electric field relaxation by the n-type RESURF diffusion layer 132.
[0099]
(Tenth embodiment)
FIG. 27 is a plan view showing the configuration of the lateral trench MOSFET according to the tenth embodiment of the present invention. FIG. 28A is a sectional view taken along line 28A-28A of FIG. 28) is a sectional view taken along line 28B-28B of FIG.
[0100]
This embodiment is a modification of the seventh embodiment. An n-type RESURF diffusion layer 132 is formed on the surface of an n-type high resistance layer 112 between a p-type well layer 113 and an n-type drain layer 115. I have.
[0101]
According to such a configuration, in addition to the effects of the seventh embodiment, a high withstand voltage can be achieved by electric field relaxation by the n-type RESURF diffusion layer 132.
[0102]
This embodiment is also applicable as a modified configuration of the eighth embodiment.
[0103]
(Eleventh embodiment)
FIG. 29 is a plan view showing the configuration of the lateral trench MOSFET according to the eleventh embodiment of the present invention. FIG. 30 (a) is a sectional view taken along line 30A-30A of FIG. ) Is a sectional view taken along line 30B-30B in FIG.
[0104]
This embodiment is a modification of the seventh embodiment. An n-type offset layer 133 having higher resistance than the n-type high resistance layer 112 is provided between the n-type drain layer 115 and the n-type high resistance layer 112. Is formed.
[0105]
According to such a configuration, in addition to the effects of the seventh embodiment, the withstand voltage of the element can be increased by the resistance of the n-type offset layer 133. This embodiment is applicable to any of the seventh to tenth embodiments.
[0106]
In this embodiment, a supplementary description will be given of the case where the p-type well layer 113 is formed by diffusion without using the diffusion self-alignment (DSA), and then the n-type source layer 114 is formed by diffusion. In this case, the p-type well layer 113 near the junction with the n-type source layer 114 has a lower concentration at the portion 113B on the lower surface of the n-type source layer 114 than at the portion 113A on the side surface of the n-type source layer 114. . For this reason, as shown in FIG. 31, the electrons e are injected into the channel from a portion 113B having a low threshold voltage. Therefore, by forming a large portion 113B between the trenches 116, electrons can be easily injected and the element resistance can be reduced.
[0107]
(Twelfth embodiment)
FIG. 32 is a plan view showing a configuration of a lateral trench MOSFET according to a twelfth embodiment of the present invention. FIG. 33 (a) is a cross-sectional view taken along line 33A-33A of FIG. 32) is a sectional view taken along line 33B-33B in FIG.
[0108]
This embodiment is a modified configuration of the eleventh embodiment, and an n-type buried layer 134 having a lower resistance than the n-type high-resistance layer 112 is formed immediately below the n-type offset layer 133. The n-type buried layer 134 is formed such that its source-side end is substantially at the same position as the source-side end of the n-type offset layer 133 in the vertical direction.
[0109]
According to such a configuration, in the conductive state, the electrons e injected into the n-type high resistance layer 112 pass through the side surface of the trench 116 to reach the n-type buried layer 134, and from the n-type buried layer 134 to the n-type offset layer 133 And flows to the n-type drain layer 115.
[0110]
That is, by providing the n-type buried layer 134 immediately below the n-type offset layer 133, electrons spread sufficiently within the channel width on the side surface of the trench 116 and flow into the n-type buried layer 134, so that the on-resistance is further reduced. be able to.
[0111]
Note that in this embodiment, the position of the n-type drain layer 115 is set higher than the position of the n-type source layer as shown in FIGS. Although formed lower, this is a modified example, and it goes without saying that the position of the n-type drain layer 115 may be on the same plane as the position of the n-type source layer.
[0112]
(Thirteenth embodiment)
FIG. 34 is a plan view showing the configuration of the lateral trench MOSFET according to the thirteenth embodiment of the present invention. FIG. 35 (a) is a sectional view taken along line 35A-35A of FIG. 34) is a sectional view taken along line 35B-35B in FIG.
[0113]
This embodiment is a modified configuration of the twelfth embodiment, in which a low-resistance n-type buried layer 135 formed immediately below an n-type offset layer 133 is provided to extend to near the center between the drain and the source. .
[0114]
According to such a configuration, as in the twelfth embodiment, the electrons e sufficiently spread within the channel width on the side surface of the trench and flow into the n-type buried layer 135, so that the on-resistance can be further reduced. . Further, in the present embodiment, since the n-type buried layer 135 is provided up to the vicinity of the center between the drain and the source, as shown in FIG. And the on-resistance can be further reduced.
[0115]
In the twelfth and thirteenth embodiments, the on-resistance can be reduced as the n-type buried layers 134 and 135 are extended toward the source, but the n-type offset layer 133 is formed deeper. To improve the breakdown voltage.
[0116]
(14th embodiment)
FIG. 36 is a plan view showing a configuration of a lateral trench MOSFET according to a fourteenth embodiment of the present invention. FIG. 37 (a) is a sectional view taken along line 37A-37A of FIG. 37) is a sectional view taken along line 37B-37B in FIG.
[0117]
The present embodiment is a modified configuration of the seventh embodiment, specifically, a combination configuration of the tenth and eleventh embodiments, in which the n-type drain layer 115 and the n-type high resistance layer 112 An n-type offset layer 133 having a higher resistance than the n-type high resistance layer 112 is formed, and an n-type RESURF diffusion is formed on the surface of the n-type high resistance layer 112 between the p-type well layer and the n-type offset layer 133. A layer 132 is formed.
[0118]
According to such a configuration, the effects of the seventh, tenth, and eleventh embodiments can be simultaneously obtained. That is, the on-resistance can be reduced without increasing the element area, and the withstand voltage of the element can be increased.
[0119]
(Fifteenth embodiment)
FIG. 38 is a sectional view showing the configuration of the vertical trench MOSFET according to the fifteenth embodiment of the present invention. This vertical trench MOSFET is a modification of the eleventh embodiment. Specifically, a p-type diffusion layer 136 is formed on the surface of a p-type well layer 113 to a depth that selectively reaches the p-type substrate 111. In addition, the source electrode 119 is covered with an insulating layer 137 so as not to be connected to an electric circuit (not shown), and is replaced with a simple metal layer 119x, while a new source electrode 38 is formed on the back surface of the p-type substrate 111. I have. Further, the drain electrode 120 a is formed on the entire surface of the insulating layer 137 while being in contact with the drain layer 115.
[0120]
That is, the source electrode 138 is formed on the back surface of the p-type substrate 111 by electrically connecting the p-type well layer 113 and the p-type substrate 111 via the p-type diffusion layer 136. This configuration is suitable for a large-current element because the wiring resistance, which normally becomes a problem in Al wiring and the like, can be reduced by eliminating the need for a two-layer wiring on the upper surface.
[0121]
As described above, when a predetermined voltage is applied to each of the electrodes 120a, 138, and 118, a current i flows from the drain electrode 120a through the drain layer 115 and the n-type offset layer 133 as shown in FIG. Through the channel on the side surface of the trench 116 to reach the p-type well layer 113, and from the p-type well layer 113 through the p-type well layer 113 and the p-type diffusion layer 136 via the n-type source layer 114 and the metal layer 119 x. It goes to the p-type substrate 111 and flows to the source electrode 138.
[0122]
As described above, according to the present embodiment, in addition to the effects of the eleventh embodiment, a configuration suitable for a large current element can be realized. Further, the drain layer 115 can be replaced with a p-type layer for forming an IGBT. That is, this embodiment can be applied to an IGBT by providing a p-type layer instead of the drain layer 115.
[0123]
(Sixteenth embodiment)
FIG. 40 is a plan view showing a configuration of a vertical trench MOSFET according to a sixteenth embodiment of the present invention, and FIG. 41 is a cross-sectional view taken along line 41-41 of FIG.
[0124]
This vertical trench MOSFET has a stripe-shaped p-type well in which an n-type buffer layer 112b and an n-type epitaxial layer 112c are sequentially formed on an n-type substrate 111n, and selectively substantially parallel to each other on the surface of the n-type epitaxial layer 112c. A layer 113 is formed. On the surface of the p-type well layer 113, an n-type source layer 114 having a stripe shape substantially parallel to each other is selectively formed.
[0125]
Here, an intermediate region extending from the end of one n-type source layer 114 to the end of the other p-type well layer 113 and the end of the n-type source layer 114 via the p-type well layer 113 and the n-type epitaxial layer 112c has a p-type. A trench 116a is formed through the n-type well layer 113 and the n-type epitaxial layer 112c to a depth in the middle of the n-type buffer layer 112b. The planar shape of the trench 116a is a continuous substantially cross shape. Specifically, the middle of each of the n-type source layers 114 is set in the middle of a stripe-shaped planar shape substantially perpendicular to the n-type source layers 114. A stripe-shaped planar shape extends substantially parallel to the layer 114.
[0126]
In the trench 116a, SiO₂A gate electrode 118 made of polysilicon is formed via a gate insulating film 117 made of polysilicon. Further, on the intermediate region between the respective sources, SiO 2 including the gate electrode 118 is formed.₂An insulating layer 137 is formed. The source electrode 138b is formed on the entire surface of the insulating layer 137 while being in contact with the n-type source layer 114. On the other hand, a drain electrode 120b is formed on the surface of the n-type substrate 111n opposite to the source electrode 138b.
[0127]
With the above-described configuration, in the conductive state, as shown in FIG. 41, electrons e supplied from source electrode 138b pass through the inversion layer at the interface of trench 116a in p-type well layer 113 via n-type source layer 114. It is injected into the n-type epitaxial layer 112c, reaches the n-type buffer layer 112b along the channel on the side surface of the trench 116a, and flows to the drain electrode 120b through the n-type substrate 111n.
[0128]
Therefore, according to the present embodiment, the same effect as that of the fifteenth embodiment can be obtained.
[0129]
In addition, in the present embodiment, as shown in a plan view shown in FIG. 42, a sectional view taken along line 43-43 of FIG. 43 shown in FIG. 43, and a sectional view taken along line 44-44 of FIG. 42 shown in FIG. The structure may be modified to omit the trench that passes through the middle of each trench at substantially right angles. Even with such a structure, the same effect as in the present embodiment can be obtained. In addition, the present embodiment and its modifications are modified to an IGBT (Insulated Gate Bipolar Transistor) using a p + type substrate 111p instead of the n + type substrate 111n, as shown in the cross-sectional views shown in FIG. 45 or FIG. Is also good.
[0130]
(Seventeenth embodiment)
FIG. 47 is a sectional view showing a configuration of a vertical trench MOSFET according to a seventeenth embodiment of the present invention. In this vertical trench MOSFET, an n-type epitaxial layer 112c is formed on an n-type substrate 111n, and the interface between the n-type epitaxial layer 112c and the n-type substrate 111n has a lower resistance than the n-type epitaxial layer 112c. Striped n-type buried layer 135a is selectively formed. On the surface of the n-type epitaxial layer 112c, a striped n-type offset layer 133a is formed substantially parallel to the n-type buried layer 135a and selectively to a depth reaching the n-type buried layer 135a. On the surface of the n-type offset layer 133a, a stripe-shaped n-type low-resistance layer 115a is selectively formed so as to be substantially parallel to the n-type offset layer 133a.
[0131]
On the other hand, in a region different from the n-type offset layer 133a on the surface of the n-type epitaxial layer 112c, a p-type well layer 113 having a stripe shape is formed selectively so as to be substantially parallel to the n-type offset layer 133a. . The end of the p-type well layer 113 overlaps the end of the n-type buried layer 135a in the vertical direction via the n-type epitaxial layer 112c. On the surface of the p-type well layer 113, a striped n-type source layer 114 is formed selectively so as to be substantially parallel to the p-type well layer 113.
[0132]
Here, the p-type well layer 113 and the n-type epitaxial layer 112c pass through the intermediate region from the end of the n-type source layer 114 to the n-type offset layer 133a via the p-type well layer 113 and the n-type epitaxial layer 112c. Then, a plurality of trenches 116 are formed to a depth reaching n-type buried layer 135a. As described above, each of the trenches 116 has a stripe-shaped planar shape in a direction substantially orthogonal to the n-type source layer 114 and the n-type low resistance layer 115a, and is arranged substantially parallel to each other.
[0133]
A gate electrode 118 is formed in each trench 116 with a gate insulating film 117 interposed therebetween. In addition, an insulating layer 137 is formed on the intermediate region between the n-type source layer 114 and the n-type low-resistance layer 115a, including the gate electrode 118. The source electrode 138b is formed on the entire surface of the insulating layer 137 while being in contact with the n-type source layer 114. On the other hand, a drain electrode 120b is formed on the surface of the n-type substrate 111n opposite to the source electrode 138b.
[0134]
With the above configuration, in the conductive state, as shown in FIG. 48, electrons e supplied from the source electrode 138b pass through the n-type source layer 114, pass through the inversion layer on the surface of the p-type well layer 113, and pass through the n-type epitaxial layer. The n-type offset layer 133a is injected into the layer 112c and reaches the n-type low-resistance layer 115a from the n-type offset layer 133a with or without the n-type buried layer 135a along the channel on the side surface of the trench 116. The electrons e reach the n-type substrate 111n from the n-type low resistance layer 115a through the n-type offset layer 133a and the n-type buried layer 135a, and flow from the n-type substrate 111n to the drain electrode 120b.
[0135]
Therefore, according to the present embodiment, the same effect as that of the fifteenth embodiment can be obtained. In addition, the provision of the n-type buried layer 135a allows the electrons e to sufficiently spread within the channel width on the side surface of the trench and flow into the n-type low-resistance layer 115a, so that the on-resistance can be further reduced. it can.
[0136]
The structures shown in FIGS. 38 to 48 can be realized with either single crystal silicon or polycrystalline silicon. However, it is easier to manufacture using single crystal silicon.
[0137]
(Eighteenth Embodiment)
FIG. 49 is a plan view showing the surface configuration of the semiconductor layer of the vertical trench MOSFET according to the eighteenth embodiment of the present invention, and FIG. 50 is a sectional view taken along line 50-50 of FIG. FIG. 51 is a sectional view taken along line 51-51 of FIG.
[0138]
This semiconductor device has a structure capable of reducing a trench interval, and a semiconductor layer is formed of polycrystalline silicon from the viewpoint of eliminating a parasitic npn transistor operation.
[0139]
Specifically, as shown in FIGS. 50 and 51, a 0.2 μm thick n + type drain layer 115x, a 0.5 μm thick n− type base layer 112x, a 0.3 μm A thick p-type base layer 113x, a p + -type contact layer 100, and a 0.2 μm-thick n + -type source layer 114x are sequentially formed. Here, the p + -type contact layer 100 has a linear planar shape and is selectively formed on the surface of the p-type base layer 113x. Further, the n + -type source layer 114x is selectively formed on the surface of the p-type base layer 113x in a region different from the p + -type contact layer 100.
[0140]
A plurality of trenches 116x having a longitudinal direction substantially perpendicular to the longitudinal direction of the p + type contact layer 100 and having a depth reaching the drain electrode 120b are formed in the n + type source layer 114x. Each trench 116x has a width of 0.4 μm and a length of 10 μm, has an interval W of 0.4 μm in the lateral direction, and is arranged at an interval of 2 μm in the longitudinal direction. Note that, within the interval of 2 μm, a linear p + -type contact layer 100 is formed along a direction substantially perpendicular to the longitudinal direction of the trench 116x.
[0141]
Note that these dimensions are merely examples, and for example, the interval W between the trenches 116x can be arbitrarily set between 0.03 and 0.8 μm. A gate electrode 118 is buried in each trench 116x via an insulating film 117.
[0142]
Also, p⁺A source electrode 138b is formed so as to make contact with type contact layer 100 and n + type source layer 114x in the vicinity thereof.
[0143]
Next, a method for manufacturing such a semiconductor device will be described.
[0144]
On the metal layer as the drain electrode 120b, a 0.2 μm thick n⁺Type amorphous silicon layer and 1 μm thick n⁻Type high resistance layers are sequentially deposited.
[0145]
Subsequently, by annealing at 600 ° C. for 20 hours, amorphous silicon is transformed into polycrystalline silicon and formed on the n + -type drain layer 115x. Subsequently, boron is ion-implanted at 100 keV, and As and boron are ion-implanted at 15 keV, thereby forming a 1 μm thick n.⁻N-type base layer 112x having a thickness of 0.5 μm, p-type base layer 113x having a thickness of 0.3 μm, and n having a thickness of 0.2 μm.⁺The source layer 114x is formed in a stacked structure of a 0.3 μm thick p + type contact layer 100.
[0146]
Hereinafter, a MOSFET having a trench structure is formed by a well-known manufacturing method for single crystal silicon. For example, a plurality of trenches 116x having a depth reaching the drain electrode 120b from the surface of the n + type source layer 114x are selectively formed by RIE. Subsequently, after an insulating film 117 is formed on the entire surface of the substrate, polycrystalline silicon as a gate electrode 118 is buried on the insulating film 117 in each trench 116x.
[0147]
This polycrystalline silicon is removed except for a portion connecting each gate. Next, the resistance is reduced by diffusing phosphorus into the polycrystalline silicon.
[0148]
In addition, an interlayer insulating layer 102 is selectively formed on the substrate with a contact hole 101 for exposing the p + type contact layer 100 and a region in the vicinity thereof. Thereafter, a source electrode 138b is formed in contact with the p + type contact layer 100 and the n + type source layer 114x in the vicinity thereof.
[0149]
As described above, according to the present embodiment, since the gate electrode 118 having the trench structure and the contact region of the source electrode 138b are formed apart from each other, a narrow trench interval W of 0.5 μm or less can be realized, and the semiconductor layer can be formed. Since it is made of polycrystalline silicon, a high switching speed and a high current interruption can be realized at the same time.
[0150]
That is, since the amplification factor of the parasitic npn transistor becomes substantially zero by manufacturing the vertical MOSFET with polycrystalline silicon, the MOSFET can cut off a large current and improve the switching speed.
[0151]
Supplementally, in the structure of the present embodiment, when single crystal silicon is used, a parasitic npn transistor operates in a portion apart from a portion where the p-type base layer 113x and the n + -type source layer 114x are short-circuited. There is a problem that the speed is slow and a large current cannot be cut off.
[0152]
For example, when the MOSFET having the structure according to the present embodiment is formed of single crystal silicon, the cutoff current is 1 A. On the other hand, when the MOSFET having the structure according to the present embodiment is formed of polycrystalline silicon, the current that can be cut off is 20 A, and the current that can be cut off is 20 times larger than that of single crystal silicon.
[0153]
In addition, since the MOSFET made of polycrystalline silicon does not operate the parasitic npn transistor, the switching speed at the time of turn-off can be higher than that of the MOSFET made of single crystal silicon.
[0154]
Further, since the longitudinal direction of the p + -type contact layer 100 and the longitudinal direction of each trench 116x are substantially orthogonal to each other, electrons injected from the source electrode 138b can flow smoothly through the channel region between the trenches.
[0155]
(Nineteenth Embodiment)
The seventh to eighteenth embodiments described above are the basic configuration of the present invention relating to the trench structure. Next, among the embodiments related to the trench structure, those having a source layer and a drain layer in a well layer will be described using single crystal silicon as an example.
[0156]
FIG. 52 is a plan view showing a configuration of a lateral trench MOSFET according to a nineteenth embodiment of the present invention. FIG. 53 (a) is a cross-sectional view taken along line 53A-53A of FIG. 52) is a sectional view taken along line 53B-53B in FIG. 52.
[0157]
In this lateral trench MOSFET, a p-type well layer 142p is selectively formed on a p-type substrate 141p. On the surface of the p-type well layer 141p, an n-type source layer 143n is selectively formed in a stripe shape, and the n-type source layer 143n is spaced apart from the n-type source layer 143n so as to be parallel to the n-type source layer 143n. Type drain layer 144n is selectively formed.
[0158]
In an intermediate region from the end of the n-type drain layer 144n to the end of the p-type well layer 142p and the end of the n-type source layer 143n, a plurality of trenches 145 are formed to a depth in the middle of the p-type well layer 142p. Each trench 145 has a stripe-shaped planar shape in a direction orthogonal to the n-type source layer 143n and the n-type drain layer 144n, and is arranged substantially in parallel with each other.
[0159]
In an intermediate region between the drain and the source and in each trench 145, a gate electrode 147 is formed with a gate insulating film 146 interposed therebetween. A source electrode 148 is formed on the n-type source layer 143n. A drain electrode 149 is formed on the n-type drain layer 144n.
[0160]
According to such a configuration, as described above, when a positive voltage that is more positive than the source is applied to the gate electrode 147 when a positive voltage is applied to the drain electrode 149 and a negative voltage is applied to the source electrode 148, the p-type The surface of the well layer 142p in contact with the gate electrode 147 is inverted to n-type, and electrons flow from the n-type source layer 143n to the n-type drain layer 144n via the inversion layer. That is, the element becomes conductive.
[0161]
At this time, a channel is formed inside the p-type well layer 142p along the trench 145, and the current spreads and flows inside as described above. Therefore, the on-resistance can be reduced according to the width of the internal channel.
[0162]
Here, assuming that the width of the trench 145 is W1, the interval between the trenches 145 is W2, and the depth of the trench 145 is d, the channel width per unit area is increased by (W1 + W2 + 2d) / (W1 + W2) times as compared with the conventional example. Can be done.
[0163]
For example, when W1 = W2 = W and the depth d = 1 μm, the relationship between the on-resistance and W is shown in FIG. When W becomes narrow in this way, the channel width per unit area increases, so that the on-resistance is reduced. In the case of W2 of 0.6 μm or less, the portion sandwiched between the trenches 145 is completely depleted when the gate is turned on, so that the electric field in the direction perpendicular to the channel is eliminated, and the on-resistance is significantly reduced. However, for W2 of 0.03 μm or less, the scattering effect due to surface irregularities increases, and the on-resistance does not decrease. Further, W2 smaller than 0.01 μm increases the on-resistance. Therefore, as described above, W2 is preferably within the range of 0.01 to 0.8 μm.
[0164]
As described above, according to the present embodiment, the same effect as in the seventh embodiment can be obtained even when the n-type source layer 143n and the n-type drain layer 144n are provided in the p-well layer 142p.
[0165]
(Twentieth embodiment)
FIG. 55 is a plan view showing the configuration of the lateral trench MOSFET according to the twentieth embodiment of the present invention. FIG. 56 (a) is a cross-sectional view taken along line 56A-56A of FIG. 55) is a sectional view taken along line 56B-56B in FIG.
[0166]
This embodiment is a modified configuration of the nineteenth embodiment, in which the conductivity types of the p-type well layer 142p, the n-type source layer 143n, and the n-type drain layer 144n are inverted. An n-type well layer 142n, a p-type source layer 143p, and a p-type drain layer 144p are provided instead of the type well layer 142p, the n-type source layer 143n, and the n-type drain layer 144n.
[0167]
Even with the above configuration, the same effects as in the nineteenth embodiment can be obtained. This embodiment can form a bridge circuit or a push-pull circuit by being combined with the nineteenth embodiment.
[0168]
(Twenty-first embodiment)
FIG. 57 is a plan view showing the configuration of the lateral trench MOSFET according to the twenty-first embodiment of the present invention. FIG. 58 (a) is a sectional view taken along the line 58A-58A in FIG. 57) is a sectional view taken along line 58B-58B in FIG. 57.
[0169]
This embodiment is a modification of the nineteenth embodiment, and is a modification of the peripheral structure of the p-type well layer. Specifically, the p-type substrate 141p has a selectively low resistance p-type buried surface. Embedded layer 151p is formed, n-type epitaxial layer 152n is formed on p-type buried layer 151p, and p-type well layer 142p is formed on the surface of n-type epitaxial layer 152n so as to reach p-type buried layer 151p. Is formed. The structure in the p-type well layer 142p is the same as in the twelfth embodiment.
[0170]
Even with such a configuration, the same effect as in the nineteenth embodiment can be obtained.
[0171]
(Twenty-second embodiment)
FIG. 59 is a plan view showing the configuration of the lateral trench MOSFET according to the twenty-second embodiment of the present invention. FIG. 60 (a) is a cross-sectional view taken along line 60A-60A of FIG. 60) is a sectional view taken along line 60B-60B in FIG.
[0172]
This embodiment is a modification of the twenty-first embodiment, in which the conductivity types of the p-type buried layer 151p, the p-type well layer 142p, the n-type source layer 143n, and the n-type drain layer 144n are inverted. Specifically, instead of the p-type buried layer 151p, the p-type well layer 142p, the n-type source layer 144n, and the n-type drain layer 144n, the n-type buried layer 151n, the n-type well layer 142n, the p-type source layer 143p and The p-type drain layer 144p is provided.
[0173]
With the above configuration, the same effect as that of the twenty-first embodiment can be obtained. This embodiment can be combined with the twenty-first embodiment to form a bridge circuit or a push-pull circuit.
[0174]
(Twenty-third embodiment)
FIG. 61 is a plan view showing the configuration of the lateral trench MOSFET according to the twenty-third embodiment of the present invention. FIG. 62 (a) is a sectional view taken along line 62A-62A of FIG. 62) is a sectional view taken along line 62B-62B in FIG.
[0175]
This embodiment is a modification of the nineteenth embodiment. Specifically, an n-type offset having a higher resistance than the n-type drain layer 144n is provided between the n-type drain layer 144n and the p-type well layer 142p. It has a layer 161n.
[0176]
Here, the n-type offset layer 161n can be formed in a self-aligned manner using, for example, the gate electrode 147 as a mask. The n-type drain layer 144n is formed, for example, by forming an oxide film on at least the gate electrode 147 and the n-type offset layer 161n after the formation of the n-type offset layer 161n, and removing the oxide film by RIE to remove the gate electrode 147. A sidewall 162 made of an oxide film is formed on the gate electrode 147. Further, the gate electrode 147 and the sidewall 162 can be used as a mask to be formed by diffusion in a self-aligned manner.
[0177]
Even with such a configuration, the effects of the nineteenth embodiment can be obtained. Also, as compared with the nineteenth embodiment, even if the gate insulating film 146 becomes thinner and the concentration of the p-type well layer 142p becomes higher, the electric field at the drain end under the gate can be reduced, so that the breakdown voltage can be maintained. .
[0178]
(24th embodiment)
FIG. 63 is a plan view showing the configuration of the lateral trench MOSFET according to the twenty-fourth embodiment of the present invention. FIG. 64 (a) is a cross-sectional view taken along line 64A-64A of FIG. 64) is a sectional view taken along line 64B-64B in FIG.
[0179]
This embodiment is a modification of the twenty-third embodiment, in which the conductivity types of the p-type well layer 142p, the n-type source layer 143n, the n-type offset layer 161n, and the n-type drain layer 144n are inverted. Specifically, instead of the p-type well layer 142p, the n-type source layer 143n, the n-type offset layer 161n, and the n-type drain layer 144n, the n-type well layer 142n, the p-type source layer 143p, the p-type offset layer 161p, The p-type drain layer 144p is provided.
[0180]
Even with the above configuration, the same effects as in the twenty-third embodiment can be obtained. This embodiment can be combined with the twenty-third embodiment to form a bridge circuit or a push-pull circuit.
[0181]
(25th embodiment)
FIG. 65 is a plan view showing the configuration of the lateral trench MOSFET according to the twenty-fifth embodiment of the present invention. FIG. 66 (a) is a sectional view taken along line 66A-66A of FIG. 65) is a sectional view taken along line 66B-66B in FIG.
[0182]
This embodiment is a modification of the twenty-third embodiment. Specifically, an n-type low resistance having a higher resistance than the n-type source layer 143n is provided between the n-type source layer 143n and the p-type well layer 142p. It has a concentration layer 171n.
[0183]
Here, the n-type low-concentration layer 171n is formed simultaneously with the n-type offset layer 161n by the same forming process as that of the n-type offset layer 161n described above. Similarly, the n-type source layer 143n is formed simultaneously with the n-type drain layer 144n by the same forming process as that of the above-described n-type drain layer 144n.
[0184]
Even with such a configuration, the effects of the twenty-third embodiment can be obtained. Also, in the present embodiment, the number of steps can be reduced because the n-type source layer 143n and the n-type drain layer 144n can be formed at the same time as compared with the twenty-third embodiment.
[0185]
(Twenty-sixth embodiment)
FIG. 67 is a plan view showing a configuration of a lateral trench MOSFET according to a twenty-sixth embodiment of the present invention. FIG. 68 (a) is a sectional view taken along line 68A-68A of FIG. FIG. 67) is a sectional view taken along line 68B-68B in FIG. 67.
[0186]
This embodiment is a modification of the twenty-fifth embodiment. The conductivity type of the p-type well layer 142p, the n-type source layer 143n, the n-type low concentration layer 171n, the n-type offset layer 161n, and the n-type drain layer 144n is changed. Specifically, instead of the p-type well layer 142p, the n-type source layer 143n, the n-type low concentration layer 171n, the n-type offset layer 161n, and the n-type drain layer 144n, an n-type well layer is used. 142n, a p-type source layer 143p, a p-type low concentration layer 171p, a p-type offset layer 161p, and a p-type drain layer 144p.
[0187]
Even with the above configuration, the same effects as in the twenty-fifth embodiment can be obtained. This embodiment can be combined with the twenty-fifth embodiment to form a bridge circuit or a push-pull circuit.
[0188]
The embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments. For example, in the above embodiment, the p-type is the first conductivity type and the n-type is the second conductivity type, but the conductivity types may be all reversed.
[0189]
In addition, the present invention can be variously modified and implemented without departing from the gist thereof.
[0190]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a semiconductor device that can be used as a switching element of a portable device and that can realize low withstand voltage and low on-resistance.
[0191]
Further, it is possible to provide a semiconductor device capable of greatly reducing the on-resistance without increasing the element area.
[Brief description of the drawings]
FIG. 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a sectional view taken along line 2-2 of FIG.
FIG. 3 is a sectional view taken along line 3-3 of FIG. 1;
FIG. 4 is a sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention;
FIG. 5 is a sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention.
FIG. 6 is a sectional view taken along line 6-6 of FIG. 5;
FIG. 7
Sectional view showing a modified configuration in the same embodiment.
FIG. 8 is a sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention.
9 is a cross-sectional view taken along line 9-9 of FIG.
FIG. 10 is a plan view showing a configuration of a semiconductor device according to a fifth embodiment of the present invention.
11 is a sectional view taken along line 11-11 of FIG. 10;
FIG. 12 is a sectional view taken along line 12-12 of FIG. 10;
FIG. 13 is a cross-sectional view showing a modified configuration of the first embodiment according to the sixth embodiment of the present invention.
FIG. 14 is a sectional view showing a modified configuration of the second embodiment in the same embodiment;
FIG. 15 is a sectional view showing a modified configuration of the third embodiment in the third embodiment;
FIG. 16 is a sectional view showing a modified configuration of the third embodiment in the modified configuration of the third embodiment;
FIG. 17 is a sectional view showing a modified configuration of the fourth embodiment in the fourth embodiment;
FIG. 18 is a sectional view showing a modified configuration of the fifth embodiment according to the fifth embodiment;
FIG. 19 is a plan view showing the configuration of a lateral trench MOSFET according to a seventh embodiment of the present invention.
20 is a cross-sectional view taken along line 20A-20A and line 20B-20B in FIG. 19;
FIG. 21 is a diagram showing, on a logarithmic scale, the dependency of the trench interval on the on-resistance of the lateral trench MOSFET in the same embodiment.
FIG. 22 is a cross-sectional view of a conventional element for describing the effect of the embodiment.
FIG. 23 is a plan view showing a configuration of a lateral trench MOSFET according to an eighth embodiment of the present invention.
24 is a sectional view taken along line 24A-24A and line 24B-24B in FIG.
FIG. 25 is a plan view showing a configuration of a lateral trench MOSFET according to a ninth embodiment of the present invention.
26 is a sectional view taken along line 26A-26A and line 26B-26B in FIG. 25;
FIG. 27 is a plan view showing a configuration of a lateral trench MOSFET according to a tenth embodiment of the present invention.
28 is a sectional view taken along line 28A-28A and line 28B-28B in FIG. 27;
FIG. 29 is a plan view showing a configuration of a lateral trench MOSFET according to an eleventh embodiment of the present invention.
30 is a sectional view taken along line 30A-30A and line 30B-30B in FIG. 29;
FIG. 31 is a schematic view for explaining an optimal mode in the embodiment.
FIG. 32 is a plan view showing a configuration of a lateral trench MOSFET according to a twelfth embodiment of the present invention.
33 is a sectional view taken along line 33A-33A and line 33B-33B in FIG. 32;
FIG. 34 is a plan view showing a configuration of a lateral trench MOSFET according to a thirteenth embodiment of the present invention.
35 is a sectional view taken along line 35A-35A and line 35B-35B in FIG. 34;
FIG. 36 is a plan view showing a configuration of a lateral trench MOSFET according to a fourteenth embodiment of the present invention.
FIG. 37 is a sectional view taken along line 37A-37A and line 37B-37B in FIG. 36;
FIG. 38 is a sectional view showing a configuration of a vertical trench MOSFET according to a fifteenth embodiment of the present invention;
FIG. 39 is a schematic view for explaining a current path in the embodiment.
FIG. 40 is a plan view showing a configuration of a vertical trench MOSFET according to a sixteenth embodiment of the present invention.
FIG. 41 is a sectional view taken along line 41-41 of FIG. 40;
FIG. 42 is a plan view showing a modified configuration of the embodiment.
FIG. 43 is a sectional view taken along line 43-43 of FIG. 42;
FIG. 44 is a sectional view taken along line 44-44 of FIG. 42;
FIG. 45 is a sectional view showing a modified configuration of the embodiment.
FIG. 46 is a sectional view showing a modified configuration of the modified configuration of the embodiment.
FIG. 47 is a plan view showing a configuration of a vertical trench MOSFET according to a seventeenth embodiment of the present invention;
FIG. 48 is a schematic view for explaining a current path in the embodiment.
FIG. 49 is a plan view showing a surface configuration of a semiconductor layer of a vertical trench MOSFET according to an eighteenth embodiment of the present invention;
50 is a sectional view taken along line 50-50 of FIG. 49.
FIG. 51 is a sectional view taken along line 51-51 of FIG. 49;
FIG. 52 is a plan view showing the configuration of a lateral trench MOSFET according to a nineteenth embodiment of the present invention.
FIG. 53 is a sectional view taken along line 53A-53A and line 53B-53B in FIG. 52;
FIG. 54 is a view showing the relationship between on-resistance and trench dimensions in the embodiment.
FIG. 55 is a plan view showing a configuration of a lateral trench MOSFET according to a twentieth embodiment of the present invention;
FIG. 56 is a sectional view taken along lines 56A-56A and 56B-56B of FIG. 55;
FIG. 57 is a plan view showing a configuration of a lateral trench MOSFET according to a twenty-first embodiment of the present invention.
58 is a sectional view taken along line 58A-58A and line 58B-58B in FIG. 57;
FIG. 59 is a plan view showing the configuration of a lateral trench MOSFET according to a twenty-second embodiment of the present invention.
60 is a sectional view taken along line 60A-60A and line 60B-60B in FIG. 59.
FIG. 61 is a plan view showing a configuration of a lateral trench MOSFET according to a twenty-third embodiment of the present invention.
FIG. 62 is a sectional view taken along line 62A-62A and line 62B-62B of FIG. 61;
FIG. 63 is a plan view showing a configuration of a lateral trench MOSFET according to a twenty-fourth embodiment of the present invention;
64 is a sectional view taken along line 64A-64A and line 64B-64B in FIG. 63;
FIG. 65 is a plan view showing a configuration of a lateral trench MOSFET according to a twenty-fifth embodiment of the present invention.
FIG. 66 is a sectional view taken along line 66A-66A and line 66B-66B in FIG. 65;
FIG. 67 is a plan view showing a configuration of a lateral trench MOSFET according to a twenty-sixth embodiment of the present invention.
FIG. 68 is a sectional view taken along line 68A-68A and line 68B-68B in FIG. 67;
FIG. 69 is a plan view showing a configuration of a conventional lateral MOSFET.
70 is a sectional view taken along line 70-70 of FIG. 69;
FIG. 71 is a sectional view showing the configuration of a conventional vertical MOSFET.
FIG. 72 is a sectional view showing a configuration of a conventional vertical MOSFET.
[Explanation of symbols]
21 ... Substrate
22, 22a, 54, 56, 57 ... oxide film
23 ... Source electrode
24 ... Drain electrode
25 ... Channel layer
25n ... n- type channel layer
26 ... Source layer
26p ... p + type source layer
27 ... Drain layer
27p ... p + type drain layer
28 ... Oxide film
29 ... Gate electrode
29p, 32p, 41p, 55p ... p + type gate electrode
30 ... polycrystalline semiconductor layer
31 ... Gate wiring layer
33, 40 ... n- type high resistance layer
51, 53... N + type polycrystalline silicon layers
52... N-type polycrystalline silicon layer
100 ... p + type contact layer
111, 141p ... p-type substrate
111n ... n-type substrate
112 ... n-type high resistance layer
112b ... n-type buffer layer
112c, 152n ... n-type epitaxial layer
112x ... n- type base layer
113, 142p ... p-type well layer
113x ... p-type base layer
114, 114x, 143n... N-type source layer
115, 115x, 144n... N-type drain layer
115a ... n-type low resistance layer
116, 116a, 116x, 145 ... trench
117,146 ... gate insulating film
118, 147 gate electrode
119, 138, 138b, 148 ... source electrode
119x ... metal layer
120, 120a, 120b, 149 ... Drain electrode
131 ... p-type high resistance layer
132 ... n-type RESURF diffusion layer
133, 133a... N-type offset layer
134, 135, 135a, 151n ... n-type buried layer
136 ... p-type diffusion layer
137 ... Insulating layer
142n ... n-type well layer
143p ... p-type source layer
144p ... p-type drain layer
151p ... p-type buried layer
161n ... n-type offset layer
161p ... p-type offset layer
162 ... side wall
171n ... n-type low concentration layer
171p ... p-type low concentration layer

Claims (3)

A drain electrode;
A second conductivity type substrate formed on the drain electrode;
A second conductive type high resistance layer formed on the second conductive type substrate;
A second conductivity type buried layer having a lower resistance than the second conductivity type high resistance layer and formed in the second conductivity type high resistance layer;
A second conductivity type drain layer formed on the surface of the second conductivity type high resistance layer;
A first conductivity type base layer formed on a surface of the second conductivity type high resistance layer in a region different from the second conductivity type drain layer;
A second conductivity type source layer formed on the surface of the first conductivity type base layer;
A source electrode formed on the second conductivity type source layer;
A plurality of trenches formed between the second conductivity type source layer and the second conductivity type drain layer to a depth in the middle of the second conductivity type high resistance layer are buried via a gate insulating film. A semiconductor device comprising: a gate electrode; A drain electrode;
A second conductivity type drain layer formed on the drain electrode;
A second conductivity type high resistance layer formed on the second conductivity type drain layer;
A first conductivity type base layer formed on the second conductivity type high resistance layer;
A linear first conductivity type contact layer formed on the first conductivity type base layer;
A second conductivity type source layer formed on a surface of the first conductivity type base layer in a region different from the first conductivity type contact layer;
A gate electrode having a depth reaching the drain electrode from the surface of the second conductivity type source layer and buried through a plurality of trenches formed on the surface of the second conductivity type source layer via an insulating film; When,
A source electrode formed in contact with the first conductivity type contact layer and the second conductivity type source layer in the vicinity thereof;
The second conductive type drain layer, the second conductive type high resistance layer, the first conductive type base layer, the first conductive type contact layer, and the second conductive type source layer are formed of polycrystalline silicon. A semiconductor device characterized by the above-mentioned. The semiconductor device according to claim 2 ,
A semiconductor device, wherein a longitudinal direction of the first conductivity type contact layer and a longitudinal direction of each of the trenches are substantially orthogonal to each other.

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