JP2010103565A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To store minority carriers in a body region to increase minority carrier concentration in the body region, and to further lower an on-voltage of a semiconductor device. <P>SOLUTION: The semiconductor device includes: n+ type emitter regions 34 connected to an emitter electrode E; p- type body regions 28 surrounding the emitter regions 34 and connected to the emitter electrode E; an n- type drift region 26 contacting the body regions 28 and isolated from the emitter regions 34 by the body regions 28; and trench gate electrodes 32 each facing, through an gate insulating film 33, the body region 28 isolating the emitter region 34 and the drift region 26 from each other. In the semiconductor device, a part of the trench gate electrode 32 different in trench width is formed in the longitudinal direction of the trench gate electrode 32. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device that controls on / off of a current flowing between a pair of main electrodes by a trench-type gate electrode, and more particularly to a technique for reducing on-voltage or on-resistance.

There is known an IGBT (Insulated Gate Bipolar Transistor) in which a MOS structure is formed on the surface of a bipolar transistor. FIG. 7 shows an example of the IGBT 6 in which the current flowing between the collector electrode C and the emitter electrode E is on / off controlled by the trench gate electrode 132.
On the surface portion of the IGBT 6, a p ⁺ type body contact region 136 connected to the emitter electrode E, an n ⁺ type emitter region 134 connected to the emitter electrode E, the body contact region 136 and the emitter A p ⁻ type body region 128 surrounding the region 134 is formed. Since the p ⁺ -type body contact region 136 and the p ⁻ -type body region 128 are maintained at the same potential, they may be collectively referred to as a body region.
An n ⁻ type drift region 126 is formed below the p ⁻ type body region 128, an n ⁺ type buffer region 124 is formed below the p ⁻ type body region 128, and a p ⁺ type collector region 122 is formed therebelow. Is formed. The collector region 122 is connected to the collector electrode D.
A trench is formed in the body region 128 that separates the emitter region 134 and the drift region 126, and a trench gate electrode 132 that faces the body region 128 that separates the emitter region 134 and the drift region 126 via the gate insulating film 133. Is formed.

The operation of the IGBT 6 in the on state will be described. When the emitter electrode E is grounded, a positive voltage is applied to the collector electrode C, and a positive voltage is applied to the trench gate electrode 132, a portion of the body region 128 facing the trench gate electrode 132 through the gate insulating film 133 is n-type. Invert. Then, electron carriers are injected from the emitter region 134 into the drift region 126 via the channel inverted to the n-type and accumulated in the buffer region 124. When the electron carriers are accumulated in the buffer region 124, the contact potential difference between the buffer region 124 and the collector region 122 is decreased, hole carriers are injected from the collector region 122 into the buffer region 124, and further injected into the drift region 126. As a result, a conductivity modulation phenomenon occurs in the buffer region 124 and the drift region 126, and a low on-voltage is realized.
The hole carriers injected from the collector region 122 recombine with the electron carriers and disappear, or are discharged to the emitter electrode E through the body region 128 and the body contact region 136.

In order to reduce the on-voltage of this type of semiconductor device, a semiconductor device has been proposed in which the hole carrier concentration between the collector and emitter electrodes is increased.
Patent Document 1 describes a semiconductor device in which a high-concentration semiconductor region having an impurity concentration higher than that of the drift region is formed at the pn junction interface between the drift region and the body region. According to this semiconductor device, the hole carriers discharged to the emitter electrode are likely to accumulate in the drift region due to the potential barrier formed at the interface between the high concentration semiconductor region and the drift region, and the hole carrier concentration is increased. can do. As the hole carrier concentration increases, the amount of injected electron carriers also increases, so the on-voltage of the semiconductor device decreases.

JP-A-8-316479

However, in order to further reduce the on-voltage of this type of semiconductor device, it is necessary to increase the minority carrier concentration in the body region. Although the semiconductor device of Patent Document 1 can increase the minority carrier concentration in the drift region near the floating semiconductor region, it cannot accumulate minority carriers in the body region and increase the minority carrier concentration.
An object of the present invention is to accumulate minority carriers in the body region, increase the minority carrier concentration in the body region, and further reduce the on-voltage of the semiconductor device.

A semiconductor device of the present invention surrounds a pair of main electrodes, a second conductivity type semiconductor region connected to one main electrode, and the second conductivity type semiconductor region, and is connected to the one main electrode. A first conductivity type body region, a second conductivity type drift region in contact with the body region and separated from the second conductivity type semiconductor region by the body region, and the second conductivity type semiconductor region and the drift region. A trench gate electrode is provided opposite to the separated body region via a gate insulating film. In the trench gate electrode of the semiconductor device of the present invention, portions having different trench widths are formed in the longitudinal direction of the trench gate electrode.
The semiconductor device of the present invention is a MOSFET, IGBT, thyristor or the like. In the case of a MOSFET, a pair of main electrodes is a drain / source electrode, and a second conductivity type semiconductor region is called a source region. In the case of an IGBT or thyristor, a pair of main electrodes is an emitter / collector electrode, and the second conductivity type semiconductor region is called an emitter region.
The second semiconductor region only needs to be formed at least part of the position along the trench gate electrode above the body region, and the shape and the like may be adjusted as appropriate. The body region may be composed of a body contact region having a high impurity concentration and a narrow body region having a low impurity concentration. Providing a body contact region with a high impurity concentration is advantageous because it is easy to make ohmic contact with the electrode.

In the trench gate electrode of the semiconductor device, portions having different trench widths are formed in the longitudinal direction. Therefore, in terms of the relationship with the adjacent trench gate electrodes, a region where the interval between the adjacent trench gate electrodes is narrow and a region where the space is wide are formed in the longitudinal direction of the trench gate electrode. In a region where the distance between adjacent trench gate electrodes is narrow, the surface area of the body region is reduced. As the surface area of the body region decreases, the resistance to the flow of minority carriers discharged through the body region to the main electrode increases. For this reason, minority carriers that should be discharged to the main electrode are likely to accumulate in the body region, and the amount of majority carriers injected increases accordingly, and the on-voltage decreases.
In addition, it is important that portions having different trench widths of the trench gate electrode are partially formed. For example, if the trench gate electrode is formed to have a wide trench width over the entire length, the off breakdown voltage is deteriorated. There is a problem of doing. That is, if the trench width of the trench gate electrode is wide over the entire length, the area of the pn junction interface between the body region and the drift region is reduced. For this reason, when the semiconductor device is turned off, the electric field that can be held in the depletion layer extending from the pn junction interface between the body region and the drift region is reduced. As a result, the electric field tends to concentrate on the gate insulating film of the trench gate electrode, and in particular, the phenomenon that the electric field concentrates on the bent portion of the gate insulating film and the semiconductor device is easily broken. Therefore, it is important that the trench gate electrode is partially formed in the longitudinal direction with different trench widths. In other words, a region having a wide interval between adjacent trench gate electrodes is partially formed. It is important that As a result, an electric field that tends to concentrate on the gate insulating film in a region where the interval between adjacent trench gate electrodes is narrow can be dispersed to the region side where the interval between adjacent trench gate electrodes is wide. In a region where the distance between adjacent trench gate electrodes is wide, the semiconductor device can be prevented from being broken and high breakdown voltage can be maintained.

It is preferable that the phase in the longitudinal direction of the trench width of the trench gate electrode is aligned between adjacent trench gate electrodes.
When the phases in which the trench widths change in the longitudinal direction are aligned, the interval between the adjacent trench gate electrodes becomes narrow in the portion where the trench width is wide, and the interval between the adjacent trench gate electrodes becomes wide in the portion where the trench width is narrow. Become. A region where the interval between adjacent trench gate electrodes is narrow and a region where the interval is wide are alternately formed. As a result, minority carriers can be accumulated in the body region, and the on-voltage can be reduced. In addition, since the portions where the interval between adjacent trench gate electrodes is wide are alternately formed, the electric field does not concentrate on the bent portion of the gate insulating film, and the off breakdown voltage does not decrease.

When wide and narrow portions of the trench are alternately formed in the longitudinal direction of the trench gate electrode, the total length of the wide portion of the trench is formed in the range of 30 to 80% of the total length of the trench gate electrode. It is preferable that
When the trench width of the trench gate electrode is wide over the entire length, the electric field concentrates on the bent portion of the gate insulating film of the trench gate electrode, and the off breakdown voltage is reduced. On the other hand, when the trench width of the trench gate electrode is narrow over the entire length, it is the same as a conventionally known semiconductor device, and minority carriers cannot be accumulated in the body region. Therefore, if the portion having a wide trench width of the trench gate electrode is formed partially and spaced apart along the longitudinal direction of the trench gate electrode, minority carriers can be accumulated without lowering the off breakdown voltage.
In the above semiconductor device, when the total length of the wide portion of the trench is in the range of 30 to 80% of the total length of the trench gate electrode, the electric field concentrates on the gate insulating film and the off breakdown voltage is reduced. Without this, minority carriers can accumulate in the body region and the on-voltage can be lowered.

It is preferable that portions of the trench gate electrode having different trench widths are periodically repeated along the longitudinal direction of the trench gate electrode.
In this case, a narrow area and a wide area between adjacent trench gate electrodes are periodically formed along the longitudinal direction. Thereby, wide regions between adjacent trench gate electrodes are formed at equal intervals. Therefore, the electric field that tends to concentrate on the gate insulating film is easily dispersed uniformly.

As a result of detailed examination of the effect of the trench gate electrode in which the trench width varies in the longitudinal direction, the present inventors can reduce not only the on-voltage but also the turn-on time when the semiconductor device is turned on. I found.
In particular, the turn-on time is significantly shortened when a semiconductor region existing in a narrow region between adjacent trench gate electrodes is substantially completely depleted without a gate-on voltage applied to the trench gate electrode. I found out that
A depletion layer extends from the junction interface between the gate insulating film and the semiconductor region even when no gate voltage is applied to the trench gate electrode.
When the semiconductor region sandwiched between adjacent trench gate electrodes is narrow and the gate insulating film thickness is optimized, a depletion layer extending from each gate insulating film is sandwiched between adjacent trench gate electrodes. They are connected in the semiconductor region, and the semiconductor region is completely depleted.
When a gate voltage is applied to the trench gate electrode in this state, an inversion layer is immediately formed in the semiconductor region because the depletion layer cannot spread further in the semiconductor region sandwiched between the adjacent trench gate electrodes. It will be.
In the above semiconductor device, the inversion layer is formed in an extremely short time in the semiconductor region in a narrow width portion between adjacent trench gate electrodes. Turn-on time can be shortened and high-speed switching characteristics are realized.
When the semiconductor region existing in the interval between the trench gate electrodes is completely depleted in a state where no gate-on voltage is applied to the trench gate electrode, the gap between the second conductivity type semiconductor region and the second conductivity type drift region is increased. There is no need to separate the first conductivity type body layer. The semiconductor region existing between the trench gate electrodes may be a semiconductor region in which the second conductivity type semiconductor region and the second conductivity type drift region are directly connected, and the first conductivity type body layer is interposed through the first conductivity type body layer. It may be a semiconductor region in which the two conductivity type semiconductor region and the second conductivity type drift region are connected.

  According to the present invention, the minority carrier concentration in the body region can be increased, and the on-voltage of the semiconductor device can be reduced.

The principal part perspective view of the semiconductor device 1 of 1st Example is shown. 2 shows a planar pattern of the trench gate electrode of the semiconductor device 1 of the first embodiment. The principal part perspective view of the semiconductor device 2 of 2nd Example is shown. The plane pattern of the trench gate electrode of the semiconductor device 3 of 3rd Example is shown. The plane pattern of the trench gate electrode of the semiconductor device 4 of 4th Example is shown. The principal part perspective view of the semiconductor device 5 of 5th Example is shown. The principal part perspective view of the conventional semiconductor device is shown.

First, the main features of the embodiment are listed.
First Embodiment A first conductivity type (for example, p-type) body contact region connected to an emitter electrode, a second conductivity type (for example, n-type) emitter region connected to the emitter electrode, and A body region of a first conductivity type surrounding the body contact region and the emitter region; a drift region of a second conductivity type in contact with the body region and separated from the body contact region and the emitter region by the body region; and the drift region A buffer region that is in contact with the buffer region and separated from the body region by the drift region, a collector region that is in contact with the buffer region and is separated from the drain region by the buffer region, and a collector electrode that is connected to the collector region; In the body region separating the emitter region and drift region In an IGBT including gate electrodes facing each other with a gate insulating film interposed therebetween, the trench gate electrode is formed with portions having different trench widths in the longitudinal direction of the trench gate electrode.
Second Embodiment A first conductivity type (for example, p-type) body contact region connected to a source electrode, a second conductivity type (for example, n-type) source region connected to the source electrode, A body region of a first conductivity type surrounding the body contact region and the source region; a drift region of a second conductivity type in contact with the body region and separated from the body contact region and the source region by the body region; and the drift region A drain region separated from the body region by the drift region, a drain electrode connected to the drain region, and a body region separating the drift region from the source region through a gate insulating film In a MOS including a gate electrode, the trench gate electrode is a portion having a different trench width. Minutes are formed in the longitudinal direction of the trench gate electrode.
Third Embodiment The phase of the planar pattern of the trench gate electrode group is aligned in the longitudinal direction of the trench gate electrode.
(4th Embodiment) The part from which the width | variety of a trench gate electrode differs is formed with fixed periodicity (at equal intervals) along the longitudinal direction of a trench gate electrode.
Fifth Embodiment The length in the longitudinal direction of the portion of the trench gate electrode where the trench width is wide is formed to be not more than 5 times the distance to the adjacent trench gate electrode.

Embodiments will be described in detail below with reference to the drawings.
First Embodiment FIG. 1 schematically shows a perspective view of a main part of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 is a semiconductor device including a trench gate electrode 32 that controls on / off of a current flowing between a collector and an emitter electrode.
The structure of the semiconductor device 1 will be described from the back side in the film thickness direction (z direction in the drawing) of the semiconductor device. A silicon single crystal containing p ⁺ -type impurities connected to a collector electrode (not shown) made of aluminum or the like Collector region 22 is formed. A silicon single crystal buffer region 24 containing an n ⁺ type impurity is formed on the collector region 22. Its on the buffer region 24 n ^- drift region 26 of the silicon single crystal containing type impurities is formed. On the drift region 26, a silicon single crystal body region 28 containing ap ⁺ type impurity is formed.
A plurality of trench gate electrodes 32 penetrating through the body region 28 and reaching the drift region 26 and facing the body region 28 via a gate insulating film 33 are formed in parallel (parallel to the y direction in the figure). Formed). The gate insulating film 33 is made of silicon oxide, and the trench gate electrode 32 is made of polysilicon. The trench gate electrode 32 is formed by repeating a portion having a wide trench width in the longitudinal direction (x direction in the drawing) of the trench gate electrode 32 at a constant cycle. Or it can be said that the wide part of the trench width of the trench gate electrode 32 is repeated at equal intervals.
When the planar pattern of the trench gate electrode 32 is viewed, the phases of the periods of the planar patterns of the adjacent trench gate electrodes 32 are aligned. Accordingly, the interval between the wide portions of the adjacent trench gate electrodes 32 is formed narrow, and the interval between the non-wide portions of the adjacent trench gate electrodes 32 is formed wide. Narrow and wide intervals between the adjacent trench gate electrodes 32 are alternately and periodically formed in the extending direction (x direction) of the trench gate electrodes 32.

An emitter region 34 and an p ⁺ type body contact region 36 that selectively contain n ⁺ type impurities are formed on the body region 28. The emitter region 34 is formed in contact with the trench gate electrode 32 in a region where the interval between adjacent trench gate electrodes 32 is wide. The body contact region 36 is formed over the upper portion of the body region 28 including a region where the interval between adjacent trench gate electrodes 32 is narrow. The emitter region 34 and the body contact region 36 are connected to an emitter electrode (not shown). The body contact region 36 is used to keep the emitter electrode and the body region 28 at the same potential, and can be omitted if an ohmic connection is secured between the emitter electrode and the body region 28. The narrowly defined body region 28 and body contact region 34 may be collectively referred to as a broadly defined body region.
The impurity concentration of each semiconductor region is in the range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ^{−3 for} the collector region 22, and in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ^{−3 for} the buffer region 24, The drift region 26 is in the range of 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻³ , the body region 28 is in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ , and the body contact region 34 is 1 × 10 10. ¹⁸ in the range of ~1 × 10 ²⁰ cm ^-3, preferably emitter region 36 is formed in a range of ^{1 × 10 18 ~1 × 10 20} cm -3.

A plan view of FIG. 1 is shown in FIG. 2, and a cross-sectional view taken along line II in FIG. 2 corresponds to the front of FIG. This plan view is a cross-sectional view taken along a plane orthogonal to the direction between the collector and emitter electrodes.
A plurality of trench gate electrodes 32 are formed in parallel in the y direction, and a portion having a wide trench width (L4 in the figure) is periodically formed in the longitudinal direction of the trench gate electrode 32 (x direction in the figure). Yes. Therefore, the wide part of the trench width (L4 in the figure) is formed at a certain ratio with respect to the period (L3 in the figure) including the part where the trench width is not wide. In other words, it can be said that the trench gate electrode 32 is formed at a certain ratio with respect to the total length of the trench gate electrode 32. This ratio is preferably formed in a range of 30 to 80%.
Further, a portion (L4 in the drawing) where the trench width of the trench gate electrode 32 is wide forms a region (L1 in the drawing) where the distance from the adjacent trench gate electrode 32 is narrow. Similarly, in the portion where the trench width of the trench gate electrode 32 is not wide, a region (L2 in the drawing) where the interval between the adjacent trench gate electrodes 32 is wide is formed. The direction in which the trench gate electrode 32 extends along the period of the planar pattern of the trench gate electrode 32 (L1 in the drawing) and the wide region (L2 in the drawing) between the adjacent trench gate electrodes 32 are narrow (L1 in the drawing) and wide regions (L2 in the drawing). In the middle x direction).
The surface area of the body contact region 36 is reduced by forming a region (L1 in the figure) where the interval between adjacent trench gate electrodes 32 is narrow.

An operation when the semiconductor device 1 is in the on state will be described.
When the emitter electrode is grounded, a positive voltage is applied to the collector electrode, and a positive voltage is applied to the trench gate electrode 32, the portion of the body region 28 facing the trench gate electrode 32 is inverted to n-type. For this purpose, electron carriers pass from the emitter region 34 to the n-type inverted portion along the trench gate electrode 32 and are injected into the drift region 26. The electron carriers injected into the drift region 26 flow in the drift region 26 toward the collector electrode, and the electron carriers accumulate in the buffer region 24. When electron carriers accumulate in the buffer region 24, the contact potential difference between the buffer region 24 and the collector region 22 decreases, hole carriers are introduced from the collector region 22 into the buffer region 24, and further hole carriers are injected into the drift region 26. Is done. As a result, a conductivity modulation phenomenon occurs in the buffer region 24 and the drift region 26, and a low on-voltage is realized.

The hole carriers injected from the collector region 22 into the drift region 26 are recombined with the electron carriers and disappear, or are discharged to the emitter electrode via the body region 28 and the body contact region 36.
At this time, since the body contact region 36 is formed in a region (region corresponding to L1 in FIG. 2) sandwiched between portions where the trench width of the trench gate electrode 32 is wide, it faces the body contact region 36. Thus, hole carriers flow from the drift region 26 into the body region 28 below the body contact region 36. However, since the body region 28 sandwiched between the trench gate electrodes 32 having a wide trench width is narrow, the diffusion resistance against hole carriers is large. Furthermore, since the area of the body contact region 36 is small, the contact resistance with respect to the hole carriers is also large. Therefore, the resistance value with respect to the hole carriers discharged to the emitter electrode via the body region 28 and the body contact region 36 corresponding to the wide trench width portion is large, so that the hole carrier concentration in the body region 28 is high. Get higher. Along with this, since the electron carriers injected from the emitter region 34 increase, the on-voltage decreases.

  By the way, the pn junction interface between the body region 28 and the drift region 26 corresponding to the region (L1 in FIG. 2) sandwiched by the portion (L4 in FIG. 2) where the trench width of the trench gate electrode 32 is wide. The area is smaller than the region (L2 in FIG. 2) where the interval between adjacent trench gate electrodes 32 is wide. Therefore, the electric field tends to concentrate on the gate oxide film 33 in the portion where the trench width of the trench gate electrode 32 is wide. However, in the semiconductor device 1 of the first embodiment, a region (L1 in FIG. 2) and a region (L2 in FIG. 2) in which the interval between adjacent trench gate electrodes 32 is narrow are the planar pattern of the trench gate electrode 32. Along the cycle, the trench gate electrode 32 is periodically formed in the longitudinal direction (x direction in FIG. 2). Therefore, an electric field that tends to concentrate in a region where the distance between adjacent trench gate electrodes 32 is narrow (L1 in FIG. 2) may be distributed to the region where the distance between adjacent trench gate electrodes 32 is large (L2 in FIG. 2). it can. Therefore, the gate insulating film 33 can be prevented from being destroyed. In order to achieve the effect of dispersing the concentrated electric field as described above, the longitudinal length of the trench gate electrode 32 (the length indicated by L4 in FIG. 2) of the trench gate electrode 32 having a wide trench width. The width of the trench gate electrode 32 is formed in a range of 5 times or less the length of the interval between adjacent trench gate electrodes 32 (the length indicated by L1 in FIG. 2). It is preferable. If the wide portion of the trench gate electrode 32 having a wide trench width is formed beyond this range, the electric field may concentrate on the bent portion of the gate insulating film 33 of the trench gate electrode 32 and may be destroyed.

A modification of the first embodiment will be described below with reference to the drawings. In addition, the same code | symbol is attached | subjected to the substantially same structure as 1st Example, and description is abbreviate | omitted.
Second Embodiment FIG. 3 schematically shows a perspective view of a main part of the semiconductor device 2. The semiconductor device 2 differs from the configuration of the semiconductor device 1 of the first embodiment in the position where the emitter region 34 is formed. An emitter region 34 is also formed on the body region 28 sandwiched between the wide portions of the trench gate electrode 32 having a large trench width.
In this case, the inversion layer formed in the body region 28 facing the wide trench width portion of the trench gate electrode 32 can effectively use the electron carriers injected from the emitter region 34 as a channel. Therefore, the channel width is widened and the on-voltage can be reduced.

Third Example FIG. 4 schematically shows a main part plane pattern of a trench gate electrode 32 of a semiconductor device 3.
The wide part of the trench width of the trench gate electrode 32 does not need to be rectangular like the semiconductor device 1 of the first embodiment, and may be formed in a polygon. In the case of the third embodiment, it has a substantially hexagonal shape. Even in this case, the diffusion resistance and the contact resistance with respect to the hole carriers in the region sandwiched between the wide portions of the trench gate electrode 32 are increased by the same effect as the semiconductor device 1 of the first embodiment, and the on-voltage is increased. Decreases.

(4th Example) The semiconductor device 4 of FIG. 5 has shown typically the case where the planar pattern of the adjacent trench gate electrode 32 is not line symmetrical.
Even in this case, the portion where the trench width of the trench gate electrode 32 is wide is narrowed between the adjacent trench gate electrodes 32, and the diffusion resistance and contact resistance with respect to hole carriers are increased at the narrow interval, and the on-voltage is lowered. .

Fifth Embodiment FIG. 6 schematically shows a perspective view of the main part of the semiconductor device 5.
In the semiconductor device 5 of the fifth embodiment, an emitter region 34 is formed in an upper portion of a region sandwiched between the wide portions of the trench gate electrode 32 having a trench width. Further, in this embodiment, the width (L1 in the drawing) of the region sandwiched between the wide portions of the trench gate electrode 32 having the wide trench width is formed to be extremely narrow. If formed extremely narrow, the body region 28 formed below the emitter region 34 is substantially completely depleted when no gate voltage is applied to the trench gate electrode 32. That is, if the depletion layer extending from the junction interface between the gate insulating film 32 and the body region 28 becomes extremely narrow, the depletion layer extending from the opposing trench gate electrode 32 is connected to the trench gate electrode 32. Thus, the body region 28 is substantially completely depleted in a state where no gate voltage is applied. As a result, when a gate voltage is applied to the trench gate electrode 32, the depletion layer cannot be expanded any more, so an inversion layer is formed immediately. That is, the turn-on time of the semiconductor device is shortened.
Also in the semiconductor device 5 of the fifth embodiment, since the area of the body contact region 36 is reduced, the contact resistance with respect to hole carriers is increased. Therefore, the hole carrier concentration in the body region 28 is high, and the ON voltage is also reduced.
In order to substantially completely deplete the region sandwiched between the wide portions of the trench gate electrode 32, the width of the region (L1 in the figure) and the thickness of the gate insulating film 33 of the trench gate electrode 32 are appropriately adjusted. do it. When this region is substantially completely depleted, the conductivity type of the region is not particularly problematic. Therefore, the body region 28 does not have to be formed below the emitter region 34, and the emitter region 34 is formed in the drift region. 26 may be in direct contact.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

22: collector region 24: buffer region 26: drift region 28: body region 32: trench gate electrode 33: gate oxide film 34: emitter region (second conductivity type semiconductor region)
36: Body contact area

Claims (5)

A pair of main electrodes;
A second conductivity type semiconductor region connected to one main electrode;
A first conductivity type body region surrounding the second conductivity type semiconductor region and connected to the one main electrode;
A drift region of a second conductivity type in contact with the body region and separated from the second conductivity type semiconductor region by the body region;
In the semiconductor device comprising a trench gate electrode facing the body region separating the second conductivity type semiconductor region and the drift region via a gate insulating film,
A portion of the trench gate electrode having a different trench width is formed in the longitudinal direction of the trench gate electrode.   2. The semiconductor device according to claim 1, wherein phases of the trench gate electrodes in the longitudinal direction of the trench width are aligned in adjacent trench gate electrodes. The wide part and the narrow part of the trench width are alternately formed in the longitudinal direction of the trench gate electrode,
3. The semiconductor device according to claim 1, wherein the total length of the wide portion of the trench width is formed in a range of 30 to 80% of the entire length of the trench gate electrode.   4. The semiconductor device according to claim 1, wherein portions of the trench gate electrode having different trench widths are periodically repeated along the longitudinal direction of the trench gate electrode.   5. The semiconductor region existing in a narrow region between adjacent trench gate electrodes is substantially completely depleted in a state where no gate-on voltage is applied to the trench gate electrode. Any of the semiconductor devices.

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