JP2009111237A - Semiconductor element - Google Patents

Abstract

A semiconductor device having a super junction region capable of preventing a decrease in breakdown voltage in a termination region is provided.
A semiconductor device includes an n + type semiconductor substrate and a super junction region in which n type pillar regions and p type pillar regions are alternately provided on the upper surface of the n + type semiconductor substrate. The shape of the n-type pillar region 2 and the p-type pillar region 3 in the cross section along the upper surface of the n + -type semiconductor substrate 1 is a stripe shape with the first direction as the longitudinal direction in the element region 20. In addition, the termination region 30 surrounding the outer periphery of the element region 20 has a stripe shape with the direction perpendicular to the outer periphery of the termination region 30 as the longitudinal direction, and the corner portion 34 of the termination region has a substantially L shape. Each of the two L-shaped sides extends in a direction orthogonal to the two outer peripheral straight lines L1 and L2 of the termination region 30 forming the corner portion 34.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a super junction region.

  Semiconductor elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) have high-speed switching characteristics and a reverse blocking voltage (withstand voltage) of several tens to several hundreds V. It is widely used for power conversion and control in equipment, communication equipment, in-vehicle motors and the like. In order to achieve miniaturization, high efficiency, and low power consumption of a power supply system using these semiconductor elements, MOSFETs, IGBTs, etc. constituting the system reduce on-state resistance while maintaining high withstand voltage. There is a need to.

  The on-resistance of the vertical power MOSFET greatly depends on the electric resistance of the conductive layer (drift layer) portion. The electrical resistance of the drift layer is determined by the impurity concentration. If the impurity concentration is increased, the on-resistance can be lowered. However, since the breakdown voltage of the PN junction formed by the drift layer and the base region decreases as the impurity concentration increases, the impurity concentration cannot be increased beyond the limit determined according to the breakdown voltage. Thus, there is a trade-off relationship between element breakdown voltage and on-resistance. Improving this trade-off is an important issue when trying to provide a semiconductor device with low power consumption. This trade-off has a limit determined by the element material, and exceeding this limit is the way to realizing a low on-resistance semiconductor element.

  As an example of a MOSFET that solves this problem, there is known a region in which vertically long strip-shaped p-type pillar regions and n-type pillar regions called super junction regions are alternately buried in the drift layer in the horizontal direction. The super junction region has the same charge amount (impurity amount) contained in the p-type pillar region and the n-type pillar region, thereby creating a pseudo non-doped layer, maintaining a high breakdown voltage, and highly doped n-type. By flowing current through the pillar region, low on-resistance exceeding the material limit is realized.

  During an off operation in a normal semiconductor element, a depletion layer spreads from the pn junction interface between the p-type base region and the n-type drift layer. The breakdown voltage of the semiconductor element is determined by the impurity concentration of the n-type drift layer and the depletion layer distance. On the other hand, when the semiconductor element having the super junction region is turned off, the depletion layer also spreads from the pn junction interface between the p-type pillar region and the n-type pillar region in the drift region. For this reason, the electric field concentration on the pn junction surface between the p-type base region and the n-type drift layer is relaxed, and the electric field of the entire drift region increases. Therefore, a high breakdown voltage can be obtained even if the impurity concentration in the n-type pillar region is higher than the impurity concentration in the drift region of a normal semiconductor element. On the other hand, when the semiconductor element having the super junction region is turned on, the current flows through the high-concentration n-type pillar region, so that the on-resistance is about 1/5 compared to the semiconductor element having the same breakdown voltage. Is possible.

  There are many methods for forming this super junction region. As one of them, there is a method in which a trench is formed on the surface of the n-type epitaxial layer by RIE (Reactive Ion Etching), and a p-type pillar region is epitaxially grown in the trench. When using this method, it is necessary to align the plane orientation for the purpose of aligning the epitaxial growth rate in the trench. For this reason, the p-type pillar region is always formed in a parallel or orthogonal direction.

  The purpose of the super junction region formed in the drift region is to improve the trade-off relationship between on-resistance and breakdown voltage by being present in a main current path (path through which current flows during gate-on operation) called an element region. In the vertical semiconductor device, a termination region exists around the device region in order to extend the depletion layer toward the end of the chip on which the semiconductor device is formed. Since this termination region is not a main current path, it does not contribute to a reduction in on-resistance. If the terminal region is designed to be wide in order to increase the breakdown voltage, the chip area increases, and the number of chips of the semiconductor device per wafer decreases, resulting in an increase in the unit cost of the chip. Therefore, reduction of the area of the termination region is required. In addition, in a semiconductor element, it is necessary to make the static withstand voltage and dynamic withstand voltage in the termination region surrounding it larger than the static withstand voltage and dynamic withstand voltage in the element region where the MOSFET is formed. When the breakdown voltage in the termination region is lower, the breakdown voltage in the entire semiconductor element is determined by the breakdown voltage in the termination region, and a high avalanche resistance cannot be obtained.

  In the semiconductor element manufacturing method described above, the degree of freedom of the p-type pillar region formed in the termination region is limited. For example, when p-type pillar regions are arranged in a stripe pattern in a chip, a depletion layer tends to extend in the longitudinal direction of the stripe connected to the p-type base region. However, when all the p-type pillar regions on the chip on which the semiconductor element is formed are formed in parallel in a stripe shape, there is a portion where the p-type pillar region has a floating potential in the termination region. In this case, there is a problem that a depletion layer is difficult to spread without causing a potential difference between the p-type pillar region having a floating potential and the n-type pillar region having a drain potential. On the other hand, Patent Document 1 describes a semiconductor element whose breakdown voltage is increased by changing the direction of the pillar region of the termination region.

However, in the structure described in Patent Document 1, the p-type pillar region and the n-type pillar region have a floating potential at the corner portion of the chip where the semiconductor element is formed, and the depletion layer is difficult to spread. A strong electric field is formed in the termination region, particularly in the corner portion, the termination breakdown voltage is lowered, and the reliability of the element is deteriorated.
JP 2001-298190 A

  An object of this invention is to provide the semiconductor element which has a super junction area | region which can prevent the fall of the proof pressure in a termination | terminus area | region.

  A semiconductor element according to one embodiment of the present invention includes a first conductivity type semiconductor substrate having an upper surface and a lower surface facing each other, a first conductivity type first semiconductor pillar region and a second conductivity on the upper surface of the semiconductor substrate. A first semiconductor pillar region and a second semiconductor in a cross-section along the upper surface of the semiconductor substrate, the second semiconductor pillar region of the mold being alternately provided along the upper surface of the semiconductor substrate. The pillar region has a stripe shape in which the first direction is the longitudinal direction in the element region, and in the termination region surrounding the outer periphery of the element region, the direction perpendicular to the outer periphery of the termination region is the longitudinal direction. The corner portion of the termination region is substantially L-shaped, and each of the two sides of the L-shape forms two corners of the termination region. Characterized in that it extends in a direction perpendicular to the straight outer periphery.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor element which has a super junction area | region which can prevent the fall of the proof pressure in a termination | terminus area | region can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, a MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

  FIG. 1 is a plan view showing the entire chip on which a semiconductor element according to the first embodiment of the present invention is formed. The chip shown in FIG. 1 is provided with an element region 20 where a semiconductor element such as a MOSFET is formed, and a termination region 30 formed so as to surround the outer periphery of the element region 20. A transition region 31 in which a part of the semiconductor element formed in the element region 20 is extended is provided in the termination region 30 around the element region 20.

  FIG. 2 is an enlarged plan view of a termination region 30 including a corner portion of a chip on which the semiconductor element according to the present embodiment shown by a two-dot chain line in FIG. 1 is formed. FIG. 3 is a cross-sectional view taken along the line A-A ′ of FIG. 2 schematically showing the configuration of the semiconductor element according to the present embodiment, and a plan view of the portion. The upper part of FIG. 3 is a cross-sectional view of the semiconductor element cut along the YZ plane, and the lower part of FIG. 3 is a plan view of the semiconductor element along the XY plane. The semiconductor element according to the present embodiment shown in FIGS. 2 and 3 relates to an n-channel planar gate type MOSFET having a super junction region. 2 and 3 show an element region 20, a termination region 30, and a transition region 31 of a chip on which a semiconductor element is formed.

  As shown in FIG. 3, the semiconductor element according to the present embodiment has an upper surface and a lower surface facing each other, and is formed on an n + type semiconductor substrate 1 made of, for example, silicon (Si). The element region 20 on the upper surface of the n + type semiconductor substrate 1 is provided with an n-type pillar region 2 and a p-type pillar region 3 having a cross-section of a vertically long strip. The n-type pillar regions 2 and the p-type pillar regions 3 are alternately provided in the lateral direction (y direction shown in FIG. 3) along the upper surface of the n + -type semiconductor substrate 1, and the first direction (x direction shown in FIG. 3). ) Is formed in a superjunction region having a stripe shape with the longitudinal direction in the vertical direction. A p-type base region 4 connected to the p-type pillar region 3 and the n-type pillar region 2 is selected on the p-type pillar region 3 repeatedly provided and the n-type pillar region 2 provided therebetween. In addition, they are provided in stripes. Furthermore, on the upper surface of the p-type base region 4, n-type source layers 5 connected to the p-type pillar regions 3 through the p-type base region 4 are selectively provided in a stripe shape.

  In the example of FIG. 3, the bottom of the p-type pillar region 3 is not in contact with the n + -type semiconductor substrate 1, and the n-type pillar region 2 is between the bottom of the p-type pillar region 3 and the n + -type semiconductor substrate 1. A part of This can be configured such that the bottom of the p-type pillar region 3 is in contact with the n + -type semiconductor substrate 1. The p-type base region 4 is partially extended not only to the element region 20 but also to the transition region 31 in order to improve breakdown voltage characteristics.

  On the n-type source layer 5, the p-type base region 4, and the n-type pillar region 2, gate electrodes 7 are formed in a stripe shape with a gate insulating film 6 interposed therebetween. As shown in FIG. 3, the gate insulating film 6 and the gate electrode 7 can be formed in common to two adjacent p-type base regions 4 with one n-type pillar region 2 interposed therebetween. The gate insulating film 6 can be a silicon oxide film having a thickness of 0.1 μm, for example. This gate electrode 7 is formed with a channel extending in the vertical direction (z direction shown in FIG. 3) in the p-type base region 4 with respect to the n + -type semiconductor substrate 1 when a gate voltage higher than the threshold voltage is applied. Thus, the MOSFET is made conductive.

  Further, the p-type base region 4 and the n-type source layer 5 are connected to the n-type source layer 5 and electrically connected to the p-type pillar region 3 through the p-type base region 4. A source electrode 8 is formed in common for each MOSFET. The source electrode 8 is insulated from the gate electrode 7 by the gate insulating film 6 or the like. A drain electrode 9 common to the plurality of MOSFETs is provided so as to be electrically connected to the lower surface of the n + type semiconductor substrate 1. An insulating film 10 is formed on the upper surface of the n + type semiconductor substrate 1 in the termination region of the semiconductor element.

  Here, in the element region 20 of the semiconductor element shown on the left side of FIG. 3, the n-type source layer 5 is provided on the surface of the p-type base region 4, and the direction perpendicular to the n + -type semiconductor substrate 1 (z direction shown in FIG. 3). A semiconductor element having an npn junction is provided. On the other hand, in the termination region 30 on the right side of FIG. 3, the n-type source layer 5 is not provided, and there is no semiconductor element having an npn junction in the vertical direction.

  As shown in FIGS. 2 and 3, in the semiconductor device of the present embodiment, the super junction region formed by the n-type pillar region 2 and the p-type pillar region 3 extends not only to the device region 20 but also to the termination region 30 on the outer periphery thereof. Is formed. As shown in FIG. 2, the termination region 30 includes a peripheral portion 32 formed in the y direction along the outer periphery L1 of the termination region 30, a peripheral portion 33 formed in the x direction along the outer periphery L2 of the termination region, and the termination region. It consists of each part of the corner part 34 formed of the outer periphery L1, L2.

  In the peripheral portion 32 of the termination region 30, a stripe-shaped super junction region whose longitudinal direction is a direction orthogonal to the outer periphery L <b> 1 of the termination region 30 (the x direction shown in FIG. 2) is formed. The longitudinal direction is the same direction as the super junction region formed in the element region 20, and the n-type pillar region 2 and the p-type pillar region 3 of the element region 20 are extended to form a super junction region. .

  In the peripheral portion 33 of the termination region 30, a stripe-shaped super junction region whose longitudinal direction is a direction orthogonal to the outer periphery L <b> 2 of the termination region 30 (y direction shown in FIG. 2) is formed. The longitudinal direction of the stripe of the super junction region in the peripheral portion 33 of the termination region 30 is a direction substantially orthogonal to the longitudinal direction of the stripe of the super junction region formed in the element region. As shown in the plan view at the bottom of FIG. 3, a part of the p-type pillar region 3 and the n-type pillar region 2 whose longitudinal direction is a direction orthogonal to the outer periphery in the peripheral portion 33 of the termination region 30 is the most part of the element region 20. It is folded back into a substantially U shape near the outer periphery. In the peripheral portion 33 of the termination region 30, a part of the p-type pillar region 3 is in contact with and connected to the p-type pillar region 3 formed on the outermost periphery of the element region 20.

  In the corner portion 34 of the termination region 30, stripe-shaped super junction regions are formed in the direction orthogonal to the outer periphery of the termination region 30. The n-type pillar region 2 and the p-type pillar region 3 are connected in the vicinity of the center of the corner portion 34 and are formed to have a substantially L shape. FIG. 4 is an enlarged view of the vicinity of the outer periphery of the corner portion 34. As shown in FIGS. 4A and 4B, the n-type pillar region 2 and the p-type pillar region 3 that form the two sides of the L-shaped super junction region, respectively, are the end points that form the corner portions 34. The region 30 extends in a direction orthogonal to the two outer straight lines L1 and L2. Here, the p-type pillar region 3 and the n-type pillar region 2 shown in FIGS. 2 to 4 have the same width.

  Next, the operation of the semiconductor element will be described with reference to FIGS. In this operation, it is assumed that the n-type source layer 5 and the p-type base region 4 of each MOSFET formed in the element region 20 are grounded via the source electrode 8. Further, it is assumed that a predetermined positive voltage is applied via the drain electrode 9 to the n + type semiconductor substrate 1 that is the drain region.

  When the semiconductor element is turned on, a predetermined positive voltage (a gate voltage equal to or higher than a threshold voltage) is applied to the gate electrode 7 of each MOSFET. As a result, an n-type inversion layer is formed in the channel region of the p-type base region 4. Electrons from the n-type source layer 5 pass through the inversion layer, are injected into the n-type pillar region 2 that is the drift region, and reach the n + -type semiconductor substrate 1 that is the drain region. Therefore, a current flows from the n + type semiconductor substrate 1 to the n type source layer 5.

  On the other hand, when the semiconductor element is turned off, the voltage applied to the gate electrode 7 is controlled so that the gate voltage applied to the gate electrode 7 of each MOSFET is equal to or lower than the threshold voltage. Thereby, the inversion layer of the channel region of the p-type base region 4 disappears, and the injection of electrons from the n-type source layer 5 to the n-type pillar region 2 is stopped. Therefore, no current flows from the n + type semiconductor substrate 1 serving as the drain region to the n type source layer 5. During the off operation, the breakdown voltage of the semiconductor element is maintained by the depletion layer extending laterally from the pn junction interface formed by the n-type pillar region 2 and the p-type pillar region 3.

  In this off operation, a depletion layer is formed in the peripheral portion 32 of the termination region 30 by extending from the p-type pillar region 3 of the super junction region extended from the element region 20. In the peripheral portion 33 of the termination region 30, the p-type pillar region 3 in the super junction region is connected to the p-type pillar region 3 in the element region 20. As a result, the p-type pillar region 3 does not become a floating potential, and a depletion layer extends from the p-type pillar region 3 also in the peripheral portion 33. Also in the corner portion 34 of the termination region 30, the p-type pillar region 3 in the super junction region is connected to the p-type base region 4 extending to the transition region 31. Thereby, in the corner part 34, a depletion layer is extended and formed in both a vertical direction (x direction shown in FIG. 2) and a horizontal direction (y direction shown in FIG. 2).

  In the termination region 30 of the semiconductor element according to the present embodiment, the p-type pillar region 3 and the n-type pillar region 2 extend in parallel in a direction that is always perpendicular to the four sides, thereby extending the depletion layer. Can be made uniform. The depletion layer formed in the termination region 30 of the semiconductor element does not have a portion with a large curvature, can reduce the concentration of the electric field, and can prevent the breakdown voltage of the termination region 30 of the semiconductor element from being lowered. Further, the p-type pillar region 3 and the n-type pillar region 2 are folded in a substantially U shape in the vicinity of the outermost peripheral portion of the element region 20. For this reason, the impurity concentration of the p-type pillar region 3 and the n-type pillar region 2 is almost equal in the vicinity of the boundary between the element region 20 and the termination region 30, and the charge balance is broken at the inflection point of the structure of the pillar region and the breakdown voltage is reduced. Can be prevented. Further, since the widths of the n-type pillar region 2 and the p-type pillar region 3 are the same, the charge balance is not broken in the termination region 30 due to the change in the width of the pillar region.

  By adopting such a structure, the termination region is depleted even at a low drain-source voltage, so that not only the static withstand voltage but also the termination withstand voltage (dynamic withstand voltage) when carriers remain in the drift layer is improved. Is done.

  In the semiconductor element according to the present embodiment shown in FIG. 2, a part of the p-type pillar region 3 and the n-type pillar region 2 of the super junction region formed in the peripheral portion 33 of the termination region 30 are part of the element region 20. It is folded back into a substantially U shape in the vicinity of the outer periphery, and a part thereof is connected to the p-type pillar region 3 formed on the outermost periphery of the element region 20. As shown in FIG. 5, the p-type pillar region 3 and the n-type pillar region 2 can all be in contact with the p-type pillar region 3 formed on the outermost periphery of the element region. Even in this case, it is possible to make the elongation of the depletion layer uniform in the termination region 30 of the semiconductor element. A depletion layer formed in the termination region 30 of the semiconductor element does not have a portion with a large curvature, can reduce the concentration of the electric field, and can prevent a decrease in breakdown voltage of the termination region of the semiconductor element.

  Next, a semiconductor element according to a second embodiment of the present invention will be described. FIG. 6 is an enlarged plan view of the termination region 30 including the corner portion of the chip on which the semiconductor element according to the second embodiment is formed. FIG. 6 shows an element region 20, a termination region 30, and a transition region 31 of a chip on which a semiconductor element is formed.

  As shown in FIG. 6, in the semiconductor element of the present embodiment, the super junction region formed by the n-type pillar region 2 and the p-type pillar region 3 is formed not only in the element region 20 but also in the termination region 30 on the outer periphery thereof. Yes. As shown in FIG. 6, the termination region 30 includes a peripheral portion 32 formed in the y direction along the outer periphery L1 of the termination region 30, a peripheral portion 33 formed in the x direction along the outer periphery L2 of the termination region, and the termination region. It consists of each part of the corner part 34 formed of the outer periphery L1, L2. In the peripheral portion 32 and the peripheral portion 33 of the termination region 30, the configuration of the super junction region formed by the n-type pillar region 2 and the p-type pillar region 3 is the same as that of the first embodiment shown in FIG.

  In the corner portion 34 of the termination region 30, striped super junction regions are formed in a direction orthogonal to the outer periphery of the termination region 30. The n-type pillar region 2 and the p-type pillar region 3 are connected in the vicinity of the center of the corner portion 34, and are formed to have a substantially L shape in the direction opposite to that of the first embodiment. Of the n-type pillar region 2 and the p-type pillar region 3 forming the L-shaped super junction region, the portion below the diagonal line of the corner portion 34 shown in FIG. 6 is a straight line on the outer periphery of the termination region 30 forming the corner portion. It extends in a direction perpendicular to L1. Of the n-type pillar region 2 and the p-type pillar region 3 that form the L-shaped super junction region, the portion above the diagonal line of the corner portion 34 shown in FIG. 6 is the outer periphery of the termination region 30 that forms the corner portion. It extends in the direction orthogonal to the straight line L2. The widths of the p-type pillar region 3 and the n-type pillar region 2 shown in FIG. 6 are the same.

  Also in the semiconductor element according to the present embodiment, the p-type pillar region 3 and the n-type pillar region 2 extend in parallel in the direction perpendicular to the four sides during the off operation, thereby extending the depletion layer. It becomes possible to make uniform. The depletion layer formed in the termination region 30 of the semiconductor element does not have a portion with a large curvature, can reduce the concentration of the electric field, and can prevent the breakdown voltage of the termination region 30 of the semiconductor element from being lowered. Further, the p-type pillar region 3 formed in the corner portion 34 of the termination region 30 is extended to the transition region 31 through the p-type pillar region 3 formed in the peripheral portion 32 and the peripheral portion 33. The p-type base region 4 is connected. Therefore, the p-type pillar region 3 formed in the corner portion 34 of the termination region 30 does not become a floating potential, and a depletion layer is reliably formed from the pn junction with the n-type pillar region 2. Further, since the widths of the n-type pillar region 2 and the p-type pillar region 3 are the same, the charge balance is not broken in the termination region 30 due to the change in the width of the pillar region.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to these, A various change, addition, etc. are possible in the range which does not deviate from the meaning of invention. For example, in the embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type.

  In the above-described embodiment, the semiconductor element is described as a planar gate type MOSFET. However, this may be a trench gate type MOSFET. Further, the present invention can be implemented in combination with various termination region structures such as providing a guard ring layer in the termination region and providing a field plate electrode.

  In the embodiment, the MOSFET using silicon as the semiconductor material has been described. As the semiconductor material, for example, a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN) or a wide band gap semiconductor such as diamond is used. Can be used. Further, the MOSFET having a super junction region has been described. However, if this is a semiconductor element having a super junction region, an SBD (Schottky Barrier Diode), a mixed element of MOSFET and SBD, SIT (Static Induction Transistor), IGBT, etc. This semiconductor device can also be applied.

1 is a plan view showing a structure of a semiconductor element according to a first embodiment. 1 is a plan view showing a structure of a semiconductor element according to a first embodiment. It is sectional drawing and the top view which show the structure of the semiconductor element which concerns on 1st Embodiment. 1 is an enlarged plan view showing a structure of a semiconductor element according to a first embodiment. It is a top view which shows the structure of the other example of the semiconductor element which concerns on 1st Embodiment. It is a top view which shows the structure of the semiconductor element which concerns on 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... n + type semiconductor substrate, 2 ... n-type pillar region, 3 ... p-type pillar region, 4 ... p-type base region, 5 ... n-type source layer, 6 ... gate Insulating film, 7 ... gate electrode, 8 ... source electrode, 9 ... drain electrode, 10 ... insulating film, 20 ... element region, 30 ... termination region.

Claims (5)

A first conductivity type semiconductor substrate having upper and lower surfaces facing each other;
A first junction type first semiconductor pillar region and a second conductivity type second semiconductor pillar region provided alternately on the upper surface of the semiconductor substrate along the upper surface of the semiconductor substrate;
The shape of the first semiconductor pillar region and the second semiconductor pillar region in a cross section along the upper surface of the semiconductor substrate is:
The element region has a stripe shape with the first direction as the longitudinal direction,
In the termination region surrounding the outer periphery of the element region, a stripe shape having a longitudinal direction in a direction orthogonal to the outer periphery of the termination region,
The corner portion of the termination region is substantially L-shaped, and each of the two sides of the L-shape extends in a direction perpendicular to the two outer straight lines of the termination region forming the corner portion. A semiconductor element.   In the termination region, a part of the first semiconductor pillar region and the second semiconductor pillar region whose longitudinal direction is substantially perpendicular to the first direction is substantially U-shaped in the vicinity of the outermost peripheral portion of the element region. The semiconductor element according to claim 1, wherein the semiconductor element is folded into a shape.   In the termination region, a part of the first semiconductor pillar region and the second semiconductor pillar region whose longitudinal direction is substantially perpendicular to the first direction is the first semiconductor pillar formed in the element region. The semiconductor element according to claim 1, wherein the semiconductor element is in contact with one of the region and the second semiconductor pillar region formed on the outermost periphery.   4. The semiconductor element according to claim 1, wherein widths of the first semiconductor pillar region and the second semiconductor pillar region are the same. 5. A first main electrode electrically connected to the lower surface of the semiconductor substrate;
A second conductive type semiconductor base region selectively provided on the upper surface of the super junction region;
A semiconductor diffusion region of a first conductivity type selectively provided on the upper surface of the semiconductor base region;
A second main electrode provided to be electrically connected to the semiconductor base region and the semiconductor diffusion region;
5. The control electrode according to claim 1, further comprising: a control electrode provided via an insulating film in a region extending from the semiconductor diffusion region through the semiconductor base region to the first semiconductor pillar region. Semiconductor element.

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