JP2005268679A - Semiconductor device and manufacturing method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the arrangement density of gate electrodes in a MISFET transistor and thereby to enable enhancing driving capability thereof and simply reducing on-resistance at a low cost. <P>SOLUTION: An n<SP>-</SP>type epitaxial layer 2 is formed on an n<SP>+</SP>type substrate 1, gate electrodes 4 of a linear pattern are provided on the surface of the n<SP>-</SP>type epitaxial layer 2 via gate dielectrics 3, the surface of the gate electrodes 4 are covered with interlayer dielectrics 5, and p type base diffusion layers 6 and n<SP>+</SP>type source diffusion layers 7 are formed relative to the gate electrodes 4 in a self-alignment manner. Here, the n<SP>+</SP>type source diffusion layers 7 are formed on the surface of the p type base diffusion layer 6, the surface of the p type diffusion layers 6, which overlap under the gate electrodes 4 vial the gate dielectrics 3, serves as a region of a DMOSFET, and some part of the n<SP>+</SP>type source diffusion layer 7 is cut to provide a p<SP>+</SP>type base contact diffusion layer 8 that connects to the p type base diffusion layer 6. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a transistor having a MISFET structure and a manufacturing method thereof.

  Conventionally, as a transistor having an insulated gate field effect transistor (MISFET) structure for controlling a large current at a high voltage, a MOS transistor (DMOSFET) by double diffusion is widely known, and both a source region and a rain region are semiconductor substrates. A lateral structure DMOSFET formed on the surface of the semiconductor substrate, or a vertical structure DMOSFET having a source region formed on the surface side of the semiconductor substrate and a drain region formed on the back side, or a single transistor semiconductor device, or It has been used for a semiconductor device called an intelligent IC embedded together with a control circuit unit or the like. In recent years, as a modified version of this DMOSFET, a vertical field effect transistor (hereinafter referred to as a TMOSFET) having a so-called trench gate structure in which a channel region is formed on the side surface of a trench (trench) to facilitate the miniaturization. Are also being newly used.

The conventional DMOSFET described above generally has a structure as shown in FIGS. FIG. 9 shows a planar structure of the DMOSFET, and FIG. 10 is a cross-sectional view taken along the line Y ₁ -Y ₂ in FIG. In the planar structure, as shown in FIG. 9, the gate electrodes 104 which are hatched for easy understanding are arranged in a mesh shape, and each of the squares partitioned by the mesh gate electrode 104 is p. The base contact portion 103a of the type base diffusion layer 103 (described later) and the n ⁺ type source diffusion layer 105 are provided. By making the gate electrode 104 mesh like this, the effective length of the edge of the gate electrode 104 is increased, the entire channel width of the transistor is increased, and the large current driving capability of the transistor is improved. The source electrode 107 covers the entire surface (not shown).

As shown in FIG. 10, the DMOSFET has a cross-sectional structure in which an n ⁻ type epitaxial layer 102 is formed on an n ⁺ type substrate 101, and the above p type is formed on the n ⁻ type epitaxial layer 102 by a thermal diffusion method. A base diffusion layer 103 is provided. In this p-type base diffusion layer 103, an n ⁺ -type source diffusion layer 105 is provided so as to form the base contact portion 103a of the p-type base diffusion layer 103 with the gate electrode 104 interposed therebetween. Here, the gate electrode 104 is formed in a form having the surface of the p-type base diffusion layer 103 as a channel region through a gate insulating film straddling the n ⁻ -type epitaxial layer 102, and the surface portion of the gate electrode 104 is an interlayer layer. An insulating film 106 is covered. The thermal diffusion for forming the p-type base diffusion layer 103 and the thermal diffusion for forming the n ⁺ -type source diffusion layer 105 are called so-called double diffusion. A source electrode 107 electrically connected to the base contact portion 103a and the n ⁺ -type source diffusion layer 105 is formed of a conductor film such as aluminum metal. Here, the base contact portion 103a between the n ⁺ -type source diffusion layers 105 may be doped with boron impurities to make this region a high concentration region.

In the above structure, a large current is controlled by the gate electrode 104, passes from the n ⁺ type substrate 101 on the drain side through the n ⁻ type epitaxial layer 102, through the channel region of the p type base diffusion layer 103, and into the source It flows from the n ⁺ -type source diffusion layer 105 on the side to the source electrode 107. Although the above structure is an n-channel DMOSFET, a p-channel DMOSFET has a similar structure although its conductivity type is reversed.

On the other hand, the above-described TMOSFET has a basic structure as shown in FIG. As shown in the figure, an n ⁻ type epitaxial layer 202 is formed on an n ⁺ type substrate 201, and a p type well layer 203 is formed on the n ⁻ type epitaxial layer 202 by a thermal diffusion method. This p type well layer An n ⁺ -type source diffusion layer 204 is formed in 203, and a body contact portion 203a is further provided. A trench 205 is formed so as to penetrate part of the n ⁻ type epitaxial layer 202, the p type well layer 203 and the n ⁺ type source diffusion layer 204. A gate insulating film 206 is formed on the side surface of the trench 205, and a trench gate electrode 207 filling the trench 205 is formed of impurity-doped polycrystalline silicon. The upper portion of the trench gate electrode 207 is covered with an insulating oxide film 208, and a source electrode 209 is formed on the entire surface with a conductor film such as aluminum metal. Here, the source electrode 209 is connected to the body contact portion 203 a and the n ⁺ -type source diffusion layer 204.

  Various studies have been made so far on the planar structure of the TMOSFET in order to increase the driving capability of the transistor and reduce its on-resistance. 12 and 13 show two examples of the planar structure of the vertical field effect transistor. FIG. 12 shows a case where the arrangement of the trench gate electrodes is a mesh, and FIG. 13 shows a case where the arrangement of the trench gate electrodes is a straight line.

When the arrangement of the trench gate electrodes is a mesh shape, as shown in FIG. 12, the hatched trench gate electrodes 207 are arranged in a mesh shape, and a number of squares partitioned by the mesh-like trench gate electrodes 207 are arranged. The body contact portion 203a and the n ⁺ -type source diffusion layer 204 are provided in each of them (see, for example, Patent Document 1). By forming the trench gate electrode 207 in a mesh shape in this manner, the effective length of the trench gate electrode 207 is increased, the entire channel width of the transistor is increased, and the driving capability of the transistor is improved. Here, the cross section shown by the dotted line in FIG. 12 corresponds to the cross section shown in FIG. The source electrode 209 shown in FIG. 11 covers the entire surface (not shown).

When the trench gate electrodes are arranged in a straight line, as shown in FIG. 13, a large number of trench gate electrodes 207 are arranged in a straight line, and the gate peripheral wiring located at the terminal portion thereof. Under 210, they are connected to each other. Then, an n ⁺ type source diffusion layer 204 is provided along the straight and long trench gate electrode 207, and a body contact portion 203a is formed between adjacent n ⁺ type source diffusion layers 204 (for example, Patent Document 2). Here, the cross section shown by a dotted line in FIG. 13 corresponds to the cross section shown in FIG. The source electrode 209 shown in FIG. 11 covers the entire surface (not shown).
Japanese Patent No. 2662217 (FIG. 9) Japanese Patent No. 3367857 (FIG. 1)

  In the above-described DMOSFET and TMOSFET, improvement of driving capability and reduction of on-resistance, which are the most important issues, increase the arrangement density of the gate electrode 104 and the trench gate electrode 207 and increase the edge length of the gate electrode. Can be achieved more effectively. This is because the channel length in a predetermined region of the DMOSFET or TMOSFET increases. Thus, as described above, the planar pattern shape of the (trench) gate electrode has been variously studied, and a meshed gate electrode, a straight gate electrode, or the like has been proposed.

However, in the conventional DMOSFET, the gate electrodes 104 are arranged in a mesh shape, and an n ⁺ -type source diffusion layer 105 and a base contact portion 103a are provided in a large number of rectangles partitioned by the mesh-like gate electrode 104, respectively. ing. For this reason, as shown in FIG. 9, the arrangement pitch of the gate electrodes 104 is (G + C + 2S) where G is the width of the gate electrode 104, C is the size of the base contact portion 103a, and S is the width of the n ⁺ -type source diffusion layer 105. Thus, there is a limit in increasing the pitch and increasing the arrangement density, and there is a problem that it is difficult to improve the driving capability and reduce the on-resistance of the DMOSFET under a design standard with a constant pattern dimension.

Further, in the manufacture of the conventional DMOSFET, the n ⁺ type source diffusion layer 105 and the base contact portion 103a are partitioned by the mesh gate electrode 104 by aligning with the pattern of the mesh gate electrode 104. Must be placed in a number of rectangles. Therefore, an alignment margin is required in the photolithography process, which further increases the arrangement pitch of the gate electrodes 104 described above. In addition, pattern alignment by photolithography in the entire DMOSFET manufacturing process is particularly severe in the process of forming the n ⁺ -type source diffusion layer 105 and the base contact portion 103a, and is one of the major factors that increase the manufacturing cost. It is also.

Similarly, when the trench gate electrodes are arranged in a mesh shape in the conventional TMOSFET, the trench gate electrodes 207 are arranged in a mesh shape, and a large number of rectangular regions defined by the mesh-like trench gate electrodes 207 are arranged. An n ⁺ type source diffusion layer 204 and a body contact portion 203a are provided therein. For this reason, as in the case of the DMOSFET described above, it is difficult in terms of structure to increase the pitch of the arrangement of the trench gate electrodes 207 and increase the arrangement density. There was a problem that there was a limit to the reduction.

  The restriction on the reduction in the arrangement pitch of the mesh-like trench gate electrodes in the TMOSFET has become a more important problem to be solved in the case of the TMOSFET having the trench gate electrode structure that can be easily miniaturized than in the case of the DMOSFET. . This is because the most effective method of increasing the gate length by increasing the arrangement density due to the miniaturized trench gate electrode structure does not work effectively.

In the TMOSFET disclosed in Patent Document 2, a large number of linear trench gate electrodes 207 are arranged in parallel, and an n ⁺ -type source diffusion layer 204 is formed along the linear thin trench gate electrodes 207. A body contact portion 203 a is provided between adjacent n ⁺ -type source diffusion layers 204. For this reason, the arrangement pitch of the trench gate electrodes 207 is (G + C + 2S) as shown in FIG. 13 as in the case of the arrangement of the mesh-like (trench) gate electrodes, and even in such a structure, There is a limit in increasing the arrangement density by increasing the arrangement pitch of the trench gate electrodes 207.

  The present invention has been made in order to solve the above-described conventional problems, and improves the arrangement density of the gate electrode or the trench gate electrode of the transistor having the MISFET structure and further facilitates the miniaturization thereof. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can achieve improvement in driving capability and reduction in on-resistance at a low cost.

  The semiconductor device of the present invention is a semiconductor device comprising a transistor having a MISFET structure formed on a semiconductor substrate, a semiconductor substrate provided with one conductivity type semiconductor layer, a drain region formed at least in the one conductivity type semiconductor layer, On the surface of the one-conductivity-type semiconductor layer, a gate electrode formed of a plurality of linear patterns of conductors parallel to each other via a gate insulating film, and on the surface of the one-conductivity-type semiconductor layer partitioned by the adjacent conductors One conductivity type formed in the reverse conductivity type diffusion layer formed, the channel region overlapping with the gate electrode through the gate insulating film, and the entire surface of the reverse conductivity type diffusion layer surface partitioned by the conductor And a source region made of a diffusion layer.

  Preferably, a diffusion layer that is a lead-out portion of the reverse conductivity type diffusion layer is partitioned by the adjacent conductor in a partial region of the one conductivity type diffusion layer that is a source region partitioned by the conductor. It is formed.

  With such a configuration, the arrangement pitch of the gate electrodes of a transistor such as a DMOSFET is improved, and a high-density gate electrode can be formed on a semiconductor substrate. Drive or higher power can be easily achieved.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a gate insulating film on the surface of one conductive type semiconductor layer of the semiconductor substrate; Forming a conductor having a linear pattern, and forming the opposite conductivity type diffusion layer and the one conductivity type diffusion layer in self-alignment with the conductor.

  Alternatively, the method for manufacturing a semiconductor device according to the present invention is the method for manufacturing a semiconductor device described above, wherein a gate insulating film is formed on the surface of the one-conductivity-type semiconductor layer of the semiconductor substrate and parallel to each other on the gate insulating film. A step of forming a conductor having a plurality of linear patterns, a step of forming the reverse conductivity type diffusion layer and the one conductivity type diffusion layer in self-alignment with the conductor, Forming a diffusion layer as the lead portion in a predetermined region in a self-aligned manner with respect to the conductor.

  With this configuration, the source diffusion layer of a transistor such as a DMOSFET can be formed in a self-aligned manner with respect to the gate electrode pattern. For this reason, the alignment margin of the source diffusion layer in the photolithography process becomes unnecessary, and the arrangement pitch of the gate electrodes can be improved under a certain design standard without miniaturization. Further, the necessity of the alignment greatly reduces the manufacturing cost of a transistor such as a DMOSFET.

  According to another aspect of the present invention, there is provided a semiconductor device including a transistor having a MISFET structure formed on a semiconductor substrate, and a semiconductor including a one-conductivity-type semiconductor layer and a reverse-conductivity-type semiconductor layer formed on the one-conductivity-type semiconductor layer. A plurality of linear patterns parallel to the substrate and the reverse-conductivity type semiconductor layer, and conductive through a gate insulating film in a trench that penetrates the reverse-conductivity type semiconductor layer and extends to the one-conductivity type semiconductor layer. A gate electrode formed by embedding a body, and a source region made of one conductivity type diffusion layer formed over the entire surface of the reverse conductivity type diffusion layer partitioned by the conductor.

  Preferably, a diffusion layer that is a lead-out portion of the reverse conductivity type semiconductor layer is partitioned by the adjacent conductor in a partial region of the one conductivity type diffusion layer that is a source region partitioned by the conductor. It is formed.

  With such a configuration, the arrangement pitch can be greatly improved by miniaturizing the trench gate electrode of a transistor such as a TMOSFET, the density of a semiconductor device driven by a large current can be increased, and the driving capability and on-resistance can be improved. Is easily achieved. Further, reduction in the size of the semiconductor device, high current drive, or high power can be easily achieved.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a plurality of linear patterns parallel to each other on the opposite conductivity type semiconductor layer of the semiconductor substrate, wherein the opposite conductivity type is provided. Forming a trench penetrating the semiconductor layer and extending to the one conductivity type semiconductor layer; forming a gate insulating film on the inner surface of the trench; and covering the gate insulating film in the trench to fill the conductor And a step of forming the one conductivity type diffusion layer on the surface of the reverse conductivity type semiconductor layer in a self-aligned manner with respect to the conductor.

  Alternatively, the method of manufacturing a semiconductor device according to the present invention is a method of manufacturing the semiconductor device, wherein the semiconductor device includes a plurality of linear patterns parallel to each other on the reverse conductivity type semiconductor layer of the semiconductor substrate, and the reverse conductivity type. Forming a trench penetrating the semiconductor layer and extending to the one conductivity type semiconductor layer; forming a gate insulating film on the inner surface of the trench; and covering the gate insulating film in the trench to fill the conductor A step of forming the one conductivity type diffusion layer on the surface of the reverse conductivity type semiconductor layer in a self-aligned manner with respect to the conductor, and a step of forming a predetermined region of the one conductivity type diffusion layer with respect to the conductor. And a step of forming a diffusion layer as the lead-out portion in the self-alignment.

  With such a configuration, the source diffusion layer of the transistor can be formed in a self-aligned manner with respect to the trench gate electrode pattern also in this case. As in the case of the DMOSFET structure described above, the trench gate electrode arrangement pitch can be improved and the transistor manufacturing cost can be reduced.

  According to the present invention, the DMOSFET and the TMOSFET having the new structure can improve the arrangement density of the gate electrode or the trench gate electrode, and further facilitate the miniaturization thereof, improving the driving capability and the on-resistance of the DMOSFET and the TMOSFET. This can be achieved easily and at low cost.

  A feature of the present invention is that a transistor having a MISFET structure that controls a large current with a high voltage, such as a DMOSFET or a TMOSFET, has a structure in which a plurality of linear pattern gate electrodes or trench gate electrodes are arranged in parallel and adjacent to each other (trench ) The source diffusion layer is formed in a self-aligned manner in the region partitioned by the gate electrode without a gap.

(First embodiment)
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a perspective view for explaining the basic structure of a DMOSFET of the present invention, and FIG. 2 is a plan view of a part of a semiconductor device made of the DMOSFET of the present invention. 3 and 4 are cross-sectional views in the order of the manufacturing process for showing the manufacturing method of the semiconductor device. In this embodiment, an n-channel MOS transistor will be described.

First, the basic structure of the DMOSFET of the present invention will be described. As shown in FIG. 1, an n ⁻ type epitaxial layer 2, which is a one conductivity type semiconductor layer, is formed on an n ⁺ type substrate 1 that becomes a drain region, and a gate insulating film 3 is interposed on the surface of the n ⁻ type epitaxial layer 2. The gate electrode 4 is provided by a conductor having a linear pattern in a stripe shape. Here, the surface portion of the gate electrode 4 is covered with an interlayer insulating film 5.

Then, a p-type base diffusion layer 6 which is a reverse conductivity type diffusion layer is formed by self-alignment with respect to the gate electrode 4 by ion implantation or thermal diffusion, and is similarly self-aligned with respect to the gate electrode 4. An n ⁺ type source diffusion layer 7 which is a one conductivity type diffusion layer is provided. Here, the n ⁺ -type source diffusion layer 7 is formed so as to cover the entire surface portion of the p-type base diffusion layer 6.

A portion of the surface of the p-type base diffusion layer 6 that overlaps under the gate electrode 4 via the gate insulating film 3 is a channel region of the DMOSFET. Further, as shown in FIG. 1, a p ⁺ -type base contact diffusion layer 8 which is a lead-out portion of the p-type base diffusion layer 6 cuts the n ⁺ -type source diffusion layer 7 in the middle and connects to the p-type base diffusion layer 6 It is set in the form to do. Although not shown, the source electrode electrically connected to the n ⁺ type source diffusion layer 7 and the p ⁺ type base contact diffusion layer 8 is made of aluminum in the same manner as described in the prior art of FIG. It is formed of a conductor film such as metal. Here, the p ⁺ -type base contact diffusion layer 8 may be a p-type diffusion layer having a low impurity concentration.

In the above structure, a large current is controlled by the gate electrode 4 as described with reference to FIG. 10, and passes from the n ⁺ type substrate 1 on the drain side through the n ⁻ type epitaxial layer 2 to the p type base diffusion layer 6. Flows from the n ⁺ -type source diffusion layer 7 on the source side to the source electrode. Then, a back gate voltage (the same voltage as the source) is applied to the p-type base diffusion layer 6 through the p ⁺ -type base contact diffusion layer 8. Although the above structure is an n-channel type DMOSFET, a p-channel type DMOSFET has a similar structure although its conductivity type is reversed.

Next, the planar structure of the semiconductor device comprising the DMOSFET of the present invention will be described with reference to FIG. Here, the same components as those shown in FIG. As shown in FIG. 2, gate peripheral wiring 9 is formed, and gate electrodes 4 made of a large number of long and thin linear pattern conductors connected thereto are arranged in parallel at a constant pitch. A striped n ⁺ -type source diffusion layer 7 is formed between these gate electrodes 4 without a gap, and a p ⁺ -type base contact diffusion layer 8 having a pattern shape orthogonal to the pattern of the gate electrode 4 has a predetermined pitch arrangement. The striped n ⁺ -type source diffusion layer 7 is cut. Here, the arrangement pitch of the p ⁺ -type base contact diffusion layers 8 may be very large, and may be 10 to 100 times the pitch of the gate electrodes 4. A source electrode 10 electrically connected to the n ⁺ type source diffusion layer 7 and the p ⁺ type base contact diffusion layer 8 is formed of a conductor film such as aluminum metal.

In this embodiment, as shown in FIG. 2, the arrangement pitch of the gate electrodes 4 is (G + S), where G is the width of the gate electrodes 4 and S is the width of the n ⁺ -type source diffusion layer 7. For this reason, if the calculation is simply performed assuming that the design criteria are the same, the arrangement pitch is improved by (S + C) from the arrangement pitch of the gate electrodes 104 in the case of the conventional technique described in FIG. For example, if the design standard is 1 μm, the distance between the gate electrodes 4 decreases by 2 μm (S + C) = (1 μm + 1 μm). Then, as will be described later in the method of manufacturing a semiconductor device, when the width of the gate electrode 4 is designed to be 2.5 μm, the arrangement pitch of the gate electrodes 104 of the prior art becomes 5.5 μm. In the embodiment, the arrangement pitch of the gate electrodes 4 is 3.5 μm, which is improved by a little over 1.5 times. The improvement in the arrangement pitch of the gate electrodes becomes more remarkable as the design dimension becomes smaller and finer. In this way, the arrangement pitch of the gate electrodes of the transistors is improved, high density gate electrodes can be formed on the semiconductor substrate, the density or size of the semiconductor device is increased, and further, the current is driven or the power is increased. Can be easily achieved.

Next, the method for manufacturing the semiconductor device will be described more specifically with reference to FIGS. 3 and 4 are cross-sectional views in the order of the manufacturing process of the semiconductor device constituted by the DMOSFET described with reference to FIG. Here, these figures are cross-sectional views taken along the line X ₁ -X ₂ in FIG. 1 and 2 are denoted by the same reference numerals.

As shown in FIG. 3A, n having a thickness of about 5 μm and an impurity concentration of about 5 × 10 ¹⁵ cm ⁻³ on an n ⁺ -type substrate 6 having a specific efficiency of about 0.001 to 0.005. ^- -type epitaxial layer 2. Then, a silicon oxide film having a thickness of about 10 nm to 100 nm is grown on the surface of the n ⁻ type epitaxial layer 2 by a thermal oxidation method to form a gate insulating film 3.

  Next, a phosphorous impurity-containing polycrystalline silicon film having a film thickness of about 300 nm is deposited by a known chemical vapor deposition (CVD) method, and a silicon oxide film is further deposited on the upper surface thereof. The silicon oxide film and the polycrystalline silicon film are processed by an etching technique to form a stripe-shaped gate electrode 4 and a cap insulating film 5a as shown in FIG. Here, the width of the gate electrode 4 is about 2.5 μm, and the space between the parallel gate electrodes 4 is about 1 μm. The cap insulating film 5a has a thickness of about 0.25 μm.

Next, ion implantation including boron impurities and heat treatment are performed on the entire surface, and as shown in FIG. 3C, a p-type base having a bottom depth of about 1 μm and an impurity concentration of about 1 × 10 ¹⁶ cm ^−3. A diffusion layer 6 is formed on the gate electrode 4 in a self-aligned manner. Here, the overlap width of the p-type base diffusion layer 6 which becomes the channel region of the DMOSFET and the gate electrode 4 is about 0.8 μm.

  Next, a side wall insulating film 5b having a film thickness of about 0.2 μm is formed by a known silicon oxide film formation by CVD and etch back by anisotropic dry etching, and the cap insulating film 5a and the side wall insulation are formed. The surface of the gate electrode 4 is covered with an interlayer insulating film 5 composed of the film 5b.

Next, as shown in FIG. 4A, a resist mask 12 having a predetermined opening 11 is formed by a known photolithography technique, and boron ions containing a boron impurity portion are implanted using the resist mask 12 as an implantation mask. A p ⁺ -type base contact diffusion layer 8 is formed. Here, the impurity concentration of the p ⁺ -type base contact diffusion layer 8 after the heat treatment is set to about 5 × 10 ¹⁹ cm ⁻³ .

Then, phosphorus or arsenic ions are implanted and heat-treated on the entire surface. As a result, as shown in FIG. 4B, the n ⁺ -type source diffusion layer 7 having a depth of about 0.2 μm and an impurity concentration of about 1 × 10 ¹⁹ cm ^{−3 is} formed into the gate electrode 4 and the sidewall insulating film 5b. To be self-aligned. Here, since the impurity concentration of the p ⁺ type base contact diffusion layer 8 is about 5 × 10 ¹⁹ cm ^−3, which is higher than the impurity concentration of the n ⁺ type source diffusion layer 7, the conductivity type of this region remains p ⁺ type. It is.

Finally, the source electrode 10 electrically connected to the n ⁺ type source diffusion layer 7 and the p ⁺ type base contact diffusion layer 8 is formed of a conductor film such as aluminum metal. In this way, as shown in FIG. 4C, the n ⁻ type epitaxial layer 2 is formed on the n ⁺ type substrate 6, and a large number of gate insulating films 3 are formed on the surface of the n ⁻ type epitaxial layer 2. A gate electrode 4 made of a conductor having a linear pattern is formed, and a p-type base diffusion layer 6 is formed in a self-aligned manner with respect to the gate electrode 4. Similarly, n ⁺ is formed in a self-aligned manner with respect to the gate electrode 4. A type source diffusion layer 7 is formed, and a portion of the surface of the p-type base diffusion layer 6 that overlaps the gate electrode 4 via the gate insulating film 3 becomes a channel region of the DMOSFET, and further a p ⁺ -type base contact diffusion layer 8 is provided in figure to connect to the p-type base diffusion layer 6 is cut in the middle of the n ⁺ -type source diffusion layer 7, n ⁺ -type source diffusion layer 7 and the p ⁺ -type base contact diffusion layer 8 second electrodeposition To the source electrode 10 which is provided connected to the semiconductor device of the present invention is completed.

In the above embodiments, although to form an n ⁺ -type source diffusion layer 7 after the formation of the p ⁺ -type base contact diffusion layer 8 is a lead-out portion of the p-type base diffusion layer 6, the n ⁺ -type source diffusion conversely The p ⁺ type base contact diffusion layer 8 may be formed after the layer 7 is formed in self-alignment with the gate electrode 4.

In this embodiment, the n ⁺ type source diffusion layer 7 is formed in a self-aligned manner with respect to the gate electrode 4. For this reason, as described above, the alignment margin of the n ⁺ -type source diffusion layer 7 in the photolithography process becomes unnecessary, and the arrangement pitch of the gate electrodes can be greatly improved even under a certain design standard. It becomes possible. In addition, since alignment is not required in this way, the gate electrode array pitch can be reduced without using a high-performance manufacturing device such as a high-performance stepper device used in a photolithography process in manufacturing a transistor such as a DMOSFET. Thus, the driving capability of the transistor can be increased and its on-resistance can be lowered. And since the alignment is not necessary, the manufacturing cost of a transistor such as a DMOSFET is reduced.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a perspective view for explaining the basic structure of the TMOSFET of the present invention, and FIG. 6 is a plan view of a part of the semiconductor device made of the TMOSFET of the present invention. 7 and 8 are cross-sectional views in order of the manufacturing process for showing the manufacturing method of the semiconductor device. In this embodiment, the case of a p-channel MOS transistor will be described.

Here, as shown in FIG. 5, the basic structure of the TMOSFET of the present invention is that a p ⁻ type epitaxial layer 22 which is a one-conductivity type semiconductor layer is formed on a p ⁺ type substrate 21 serving as a drain region. ^An n-type well layer 23 which is a reverse conductivity type semiconductor layer is formed on the ⁻ type epitaxial layer 22 by an ion implantation method or a thermal diffusion method. Here, the n-type well layer 23 corresponds to a so-called base diffusion region in the DMOS structure. A trench 24 is linearly formed in parallel on the n-type well layer 23 so as to penetrate part of the p ⁻ -type epitaxial layer 22 and the n-type well layer 23. A gate insulating film 25 is formed on the side surface of the trench 24, and a trench gate electrode 26 filling the trench 24 is formed of impurity-doped polycrystalline silicon as a conductor. The upper portion of the trench gate electrode 26 is covered with a protective insulating film 27. Further, there is no gap in the surface region of the n-type well layer 23 partitioned by the trench gate electrode 26, and a p ⁺ -type source diffusion layer 28 serving as a source region which is a one-conductivity type diffusion layer is provided. Further, an n ⁺ type body diffusion layer 29 connected to the n type well layer 23 is formed in a pattern shape orthogonal to the trench gate electrode 26 pattern. Here, the n ⁺ -type body diffusion layer 29 is a lead portion of the n-type well layer 23. Although not shown in FIG. 5, the source electrode is formed on the entire surface and is connected to the p ⁺ type source diffusion layer 28 and the n ⁺ type body diffusion layer 29. In the above structure, the n-type well layer 23 which is a reverse conductivity type semiconductor layer may be an n-type epitaxial layer formed by known epitaxial growth.

In the above structure, a large current is controlled by the trench gate electrode 26, passes from the p ⁺ type source diffusion layer 28 on the source side through the channel region of the n type well layer 23, passes through the p ⁻ type epitaxial layer 22, and drains. It flows to the p ⁺ type substrate 1 which is the side. Then, a back gate voltage (the same voltage as the source) is applied to the n-type well layer 23 through the n ⁺ -type body diffusion layer 29. Although the above structure is a p-channel type TMOSFET, an n-channel type TMOSFET has a similar structure although its conductivity type is reversed.

Next, the planar structure of the semiconductor device comprising the TMOSFET of the present invention will be described with reference to FIG. Here, the same components as those shown in FIG. As shown in FIG. 6, a gate peripheral wiring 30 is formed, and trench gate electrodes 26 made of a conductor having a long and thin linear pattern connected to the gate peripheral wiring 30 are arranged in parallel at a constant pitch. A striped p ⁺ -type source diffusion layer 28 is formed between these trench gate electrodes 26 without any gap, and an n ⁺ -type body diffusion layer 29 having a pattern shape orthogonal to the pattern of the trench gate electrode 26 is formed in a predetermined manner. The striped p ⁺ -type source diffusion layer 28 is formed so as to be cut in a pitch arrangement. Here, the arrangement pitch of the n ⁺ -type body diffusion layers 29 may be very large, and may be about 100 times the pitch of the trench gate electrodes 26. A source electrode 31 electrically connected to the p ⁺ type source diffusion layer 28 and the n ⁺ type body diffusion layer 29 is formed of a conductor film such as aluminum metal.

Also in this embodiment, as described in the first embodiment, the arrangement pitch of the trench gate electrodes 11 is such that the width of the trench gate electrode 26 is G and the width of the p ⁺ -type source diffusion layer 28 is S (G + S). ) Here, since it is a transistor like a TMOSFET for miniaturization, for example, as will be described later, if the design standard is 0.25 μm, the arrangement pitch is 0.5 μm. On the other hand, in the conventional TMOSFET structure, as shown in FIGS. 12 and 13, the arrangement pitch increases by 0.5 μm corresponding to (S + C) = (0.25 μm + 0.25 μm). As described above, in this embodiment, the arrangement pitch of the trench gate electrodes 26 is doubled as compared with the conventional case. In this manner, the arrangement pitch of the gate electrodes of the transistors is further improved, and the semiconductor device can be easily increased in density or reduced in size, further driven at a large current or increased in power.

Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 7 and 8 are cross-sectional views in the order of the manufacturing process of the semiconductor device constituted by the TMOSFET described with reference to FIG. Here, these figures are cross-sectional views taken along the line X ₃ -X ₄ in FIG. Here, components similar to those in FIGS.

As shown in FIG. 7A, a p ⁻ type epitaxial layer 22 of about 5 μm is formed on a p ⁺ type substrate 21. Then, an n-type well layer 23 having a depth of about 1 μm is formed on a portion of the p ⁻ -type epitaxial layer 22 by ion implantation or thermal diffusion, and a mask insulating film 32 is formed of a silicon oxide film on the surface. .

Then, as shown in FIG. 7B, a predetermined region of the mask insulating film 32 is etched by a known photolithography technique and dry etching technique to form a desired opening, and this is used as an etching mask to form an n-type well. A large number of trenches 24 having a depth of about 1.5 μm are formed so as to penetrate the layer 23 and extend to the p ⁻ -type epitaxial layer 22. Here, the widths of these trenches 24 are the same and are about 0.25 μm, and the interval between the trenches 24 is also about 0.25 μm.

  Next, as shown in FIG. 7C, a gate insulating film 25 is formed with a silicon oxide film having a thickness of about 15 nm by thermal oxidation of the sidewalls of the trench 24, and then polycrystalline silicon is formed by a known CVD method. A film 33 is deposited on the entire surface so as to fill the trench 24, and is doped with boron impurities or phosphorus impurities. Then, the polycrystalline silicon film 33 is etched by etch back or the like, and a trench gate electrode 26 is buried in the trench 24 as shown in FIG.

  Next, as shown in FIG. 8A, a protective oxide film 34 is formed by depositing a silicon oxide film on the entire surface by plasma (PE) CVD using high density plasma (HDP). Here, in the PECVD method, bias CVD is preferably used so that the silicon oxide film is a dense insulating film. Subsequently, unnecessary portions are removed by chemical mechanical polishing (CMP) or etch back, and a protective insulating film 27 is formed on the trench gate electrode 26 as shown in FIG. 8B.

Then, by ion implantation of phosphorus using a resist mask formed by photolithography as an implantation mask and subsequent heat treatment, as shown in FIG. 8C, n ^{+ is} formed on the surface of the n-type well layer 23 in a predetermined region. A body diffusion layer 29 is formed.

Then, as shown in FIG. 8D, a p ⁺ -type source diffusion layer 28 is formed by ion implantation of boron at a lower dose than the case of the above-described phosphorus ion implantation and subsequent heat treatment. Then, although not shown, the p ⁺ type source diffusion layer 28 and the n ⁺ body diffusion layer 29 are exposed, and the source electrode 31 is formed. In this way, the semiconductor device composed of the TMOSFET described with reference to FIG. 5 is completed. Here, all the trench gate electrodes 26, the p ⁺ -type source diffusion layer 28 and the n ⁺ -type body diffusion layer 29 are formed without any gaps on the surface of the n-type well layer 23.

The above embodiments, although to form a p ⁺ -type source diffusion layer 28 after forming the n ⁺ -type body diffusion layer 29 is a lead-out portion of the n-type well layer 23, p ⁺ -type source diffusion layer 28 in the opposite May be formed in a self-aligned manner with respect to the trench gate electrode 26, and then the n ⁺ type body diffusion layer 29 may be formed.

In this embodiment, the p ⁺ type source diffusion layer 28 is formed in a self-aligned manner with respect to the trench gate electrode 26. For this reason, the alignment margin of the p ⁺ -type source diffusion layer 28 in the photolithography process becomes unnecessary exactly as described in the first embodiment. And this alignment unnecessary further promotes the miniaturization of the transistor composed of the TMOSFET, further improves the arrangement pitch of the trench gate electrodes, further increases the driving capability of the transistor, further reduces its on-resistance, and By eliminating the need for alignment, the manufacturing cost of a transistor such as a TMOSFET can be reduced.

The present invention is not limited to the above-described embodiment, and the embodiment can be appropriately changed within the scope of the technical idea of the present invention. In the above-described embodiments, the case of a vertical structure DMOSFET or TMOSFET has been described. However, the present invention can be similarly applied to a case of a horizontal structure DMOSFET or TMOSFET. In the present invention, the p-type base contact diffusion layer 8 serving as the lead portion of the p-type base diffusion layer 6 and the n ⁺ -type body diffusion layer 14 serving as the lead portion of the n-type well layer 8 are provided in the peripheral portion of the semiconductor chip 1. Or you may make it form in a part of inside. This is because it is sufficient that a back gate voltage (same as the source potential) can be applied to the p-type base diffusion layer 6 and the n-type well layer 8. Further, the present invention can be applied to a semiconductor device in which a DMOSFET or TMOSFET constituting a power transistor and a normal MOS transistor constituting a control circuit unit are mixedly mounted on the same semiconductor chip. It is.

It is a perspective view which shows the basic structure of DMOSFET for demonstrating the 1st Embodiment of this invention. 1 is a plan view of a part of a semiconductor device for explaining a first embodiment of the present invention; It is sectional drawing of the order of the manufacturing process of the semiconductor device for demonstrating the 1st Embodiment of this invention. It is sectional drawing of the process order of the continuation of the said process. It is a perspective view which shows the basic structure of TMOSFET for demonstrating the 2nd Embodiment of this invention. It is a partial top view of the semiconductor device for demonstrating the 2nd Embodiment of this invention. It is sectional drawing of the order of the manufacturing process of the semiconductor device for demonstrating the 2nd Embodiment of this invention. It is sectional drawing of the process order of the continuation of the said process. It is a top view of DMOSFET for demonstrating the prior art. It is sectional drawing which shows the basic structure of DMOSFET for demonstrating the prior art. It is sectional drawing which shows the basic structure of TMOSFET for demonstrating the prior art. It is a top view of TMOSFET for demonstrating the prior art. It is a top view of another TMOSFET for demonstrating a prior art.

Explanation of symbols

1 n ⁺ type substrate 2 n ⁻ type epitaxial layer 3, 25 gate insulating film 4 gate electrode 5 interlayer insulating film 6 p type base diffusion layer 7 n ⁺ type source diffusion layer 8 p ⁺ type base contact diffusion layer 9, 30 gate periphery Wiring 10, 31 Source electrode 11 Opening 12 Resist mask 21 p ⁺ type substrate 22 p ⁻ type epitaxial layer 23 n type well layer 24 trench 26 trench gate electrode 27 Protective insulating film 28 p ⁺ type source diffusion layer 29 n ⁺ type body diffusion Layer 32 Mask insulating film 33 Polycrystalline silicon film 34 Protective insulating film

Claims (8)

A semiconductor device including a transistor having a MISFET structure formed on a semiconductor substrate,
A semiconductor substrate provided with one conductivity type semiconductor layer;
A drain region formed at least in the one conductivity type semiconductor layer;
A gate electrode formed of a plurality of linearly patterned conductors on the surface of the one-conductivity-type semiconductor layer through a gate insulating film;
A channel region consisting of a reverse conductivity type diffusion layer formed on the surface of the one conductivity type semiconductor layer partitioned by the adjacent conductor, and overlapping the gate electrode and the gate insulating film;
A source region composed of one conductivity type diffusion layer formed over the entire surface of the reverse conductivity type diffusion layer partitioned by the conductor;
A semiconductor device.   A diffusion layer that is a lead-out portion of the reverse conductivity type diffusion layer is partitioned and formed by the adjacent conductor in a partial region of the one conductivity type diffusion layer that is a source region partitioned by the conductor. The semiconductor device according to claim 1. A method of manufacturing a semiconductor device according to claim 1,
Forming a gate insulating film on the surface of the one-conductive semiconductor layer of the semiconductor substrate, and forming a plurality of linearly patterned conductors parallel to each other on the gate insulating film;
Forming the reverse conductivity type diffusion layer and the one conductivity type diffusion layer in a self-aligned manner with respect to the conductor;
A method for manufacturing a semiconductor device comprising: A method of manufacturing a semiconductor device according to claim 2,
Forming a gate insulating film on the surface of the one-conductivity-type semiconductor layer of the semiconductor substrate, and forming a plurality of linear pattern conductors parallel to each other on the gate insulating film;
Forming the reverse conductivity type diffusion layer and the one conductivity type diffusion layer in a self-aligned manner with respect to the conductor;
Forming a diffusion layer as the lead portion in a self-aligned manner with respect to the conductor in a predetermined region of the one conductivity type diffusion layer;
A method for manufacturing a semiconductor device comprising: In a semiconductor device comprising a transistor having a MISFET structure formed on a semiconductor substrate,
A semiconductor substrate comprising a one conductivity type semiconductor layer and a reverse conductivity type semiconductor layer formed on the one conductivity type semiconductor layer;
A plurality of linear patterns parallel to each other on the reverse conductivity type semiconductor layer, and a conductor is embedded through a gate insulating film in a trench that penetrates the reverse conductivity type semiconductor layer and extends to the one conductivity type semiconductor layer. A gate electrode comprising:
A source region composed of one conductivity type diffusion layer formed over the entire surface of the reverse conductivity type semiconductor layer partitioned by the conductor;
A semiconductor device.   A diffusion layer that is a lead-out portion of the reverse conductivity type semiconductor layer is partitioned and formed by the adjacent conductor in a partial region of the one conductivity type diffusion layer that is a source region partitioned by the conductor. The semiconductor device according to claim 5. A method of manufacturing a semiconductor device according to claim 5,
Forming a plurality of linear patterns parallel to each other on the opposite conductivity type semiconductor layer of the semiconductor substrate, and forming a trench penetrating the opposite conductivity type semiconductor layer and extending to the one conductivity type semiconductor layer;
Forming a gate insulating film on the inner surface of the trench, further covering the gate insulating film in the trench and filling a conductor;
Forming the one conductivity type diffusion layer on the surface of the reverse conductivity type semiconductor layer in a self-aligned manner with respect to the conductor;
A method for manufacturing a semiconductor device comprising: A method of manufacturing a semiconductor device according to claim 6,
Forming a plurality of linear patterns parallel to each other on the opposite conductivity type semiconductor layer of the semiconductor substrate, and forming a trench penetrating the opposite conductivity type semiconductor layer and extending to the one conductivity type semiconductor layer;
Forming a gate insulating film on the inner surface of the trench, further covering the gate insulating film in the trench and filling a conductor;
Forming the one conductivity type diffusion layer on the surface of the reverse conductivity type semiconductor layer in a self-aligned manner with respect to the conductor;
Forming a diffusion layer as the lead portion in a self-aligned manner with respect to the conductor in a predetermined region of the one conductivity type diffusion layer;
A method for manufacturing a semiconductor device comprising:

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