JP2007129098A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a trade-off of an on voltage and a turned-off loss to prevent a decrease in latch-up resistant quantity. <P>SOLUTION: A semiconductor device comprises an n<SP>-</SP>single crystal silicon substarte 29, a cathode film 24 provided on the n<SP>-</SP>single crystal silicon substrate 29 and having an n<SP>++</SP>source region 26 and a p<SP>+</SP>base region 33 alternately arranged, a gate polysilicon 22 provided on the cathode film 24, and an electrode provided so as to contact with the p<SP>+</SP>base region 33 and the n<SP>++</SP>source region 26 of the cathode film 24. A first contacting region 30a of an electrode to the p<SP>+</SP>base region 33 is positioned to the side closer to the gate polysilicon 22 than a second contacting region 30b of an electrode to the n<SP>++</SP>source region 26. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a power semiconductor device constituting an IGBT (Insulated Gate Bipolar Transistor).

  Conventionally, the performance of an IGBT has been improved by many improvements. Here, the performance of the IGBT is as a switch that keeps the voltage and shuts off the current completely when it is off, while flowing the current with the smallest possible voltage drop, that is, the smallest on-resistance when it is on. It's about performance. In the present specification, in view of the essence of the operation of the IGBT, the collector is denoted as “anode” and the emitter is denoted as “cathode”.

Here, an example of the structure of the IGBT will be described. FIG. 7 is an explanatory diagram showing the configuration of the IGBT. In FIG. 7, for example, an oxide film 121 is selectively formed on the first main surface of an n ⁻ single crystal silicon substrate 129 to be a drift layer. Then, the surface of the oxide film 121, n ^- of the single crystal silicon substrate 129, the portion not covered by the oxide film 121, n ^- cathode layer 124 n-type heavily doped than the single crystal silicon substrate 129 Covered by.

In the cathode film 124, a portion of the cathode film 124 that contacts the n ⁻ single crystal silicon substrate 129 becomes an n ⁺ buffer region 125. A portion of the cathode film 124 adjacent to the n ⁺ buffer region 125 is provided with a p base region 127 selectively doped p-type. An n ⁺ source region 126 is provided inside the p base region 127.

A gate oxide film 123 is selectively formed on the surface of the cathode film 124 so as to cover the n ⁺ buffer region 125 and a part of the p base region 127. On the gate oxide film 123, polysilicon 122 (hereinafter referred to as gate polysilicon) serving as a gate electrode is deposited. The periphery of the gate polysilicon 122 is covered with an interlayer insulating film 128. The gate polysilicon 122 is insulated from the emitter electrode 130 by the interlayer insulating film 128.

In the interlayer insulating film 128, the n ⁺ source region 126, and the p base region 127, an aluminum layer that becomes the emitter electrode 130 is formed. The emitter electrode 130 is in contact with a part of the n ⁺ source region 126.

A p ⁺ anode layer 131 is formed on the second main surface of the n ⁻ single crystal silicon substrate 129. An aluminum layer to be the anode electrode 132 is formed on the surface of the p ⁺ anode layer 131.

Next, a method for manufacturing the IGBT shown in FIG. 7 will be described with reference to FIGS. 8-15 is sectional drawing which shows the manufacturing method of IGBT shown in FIG. For example, an n-type FZ silicon substrate of 30 Ωcm is prepared as the n ⁻ single crystal silicon substrate 129. Then, thermal oxidation is performed to grow an oxide film 121 having a thickness of, for example, 0.1 μm on the mirror polished surface of the substrate (FIG. 8). Next, patterning and etching are performed to remove part of the oxide film 121 (FIG. 9).

Next, on the exposed portion of the oxide film 121 and the n ⁻ single crystal silicon substrate 129 in the window portion of the oxide film 121, for example, polysilicon doped in the n-type at a concentration of 1 × 10 ¹⁶ cm ⁻³ is used. Deposit to a thickness of 0.25 μm. This polysilicon is a cathode film 124, which later becomes a source region, a channel region, and a buffer region (FIG. 10). Next, thermal oxidation is performed to oxidize the surface of the cathode film 124 to form a gate oxide film 123 having a thickness of, for example, 0.1 μm. At this time, the film thickness of the polysilicon is reduced by, for example, 0.05 μm, so that the thickness of the cathode film 124 is, for example, 0.2 μm.

Next, a gate polysilicon 122 serving as a gate electrode is deposited on the gate oxide film 123 to a thickness of 0.5 μm, for example. Then, for example, heat treatment is performed at 900 ° C. in a POCl ₃ atmosphere, and the gate polysilicon 122 is doped to a high concentration n-type (FIG. 11). Next, patterning and etching are performed to remove a part of the gate polysilicon 122. Using the remaining gate polysilicon 122 as a mask, boron having a dose of, for example, 5 × 10 ¹⁴ cm ⁻² and arsenic having a dose of, for example, 1 × 10 ¹⁵ cm ⁻² are ion-implanted into the cathode film 124. Then, for example, driving is performed at 1150 ° C. for 2 hours in a nitrogen atmosphere to form a p base region 127 and an n ⁺ source region 126 to be channel regions (FIG. 12).

Next, BPSG having a thickness of, for example, 1 μm is deposited as the interlayer insulating film 128, and patterning and etching are performed to form a contact hole penetrating the interlayer insulating film 128 and the gate oxide film 123. Next, a metal such as aluminum is sputtered on the interlayer insulating film 128 to a thickness of 5 μm, for example. Then, patterning and etching of a metal such as aluminum is performed to form the emitter electrode 130 (FIG. 13). Next, the back surface of the n ⁻ single crystal silicon substrate 129 is ground to a wafer thickness of, for example, 100 μm. Thereafter, boron having a dose of, for example, 1 × 10 ¹⁴ cm ⁻² is ion-implanted into the ground surface. Then, for example, annealing is performed at 380 ° C. for 1 hour to form the p ⁺ anode layer 131 (FIG. 14).

Next, a metal such as aluminum is vapor-deposited on the surface of the p ⁺ anode layer 131 to form the anode electrode 132 (FIG. 15). It should be noted that n-type impurities such as phosphorus may be ion-implanted into the ground surface of the back surface of the n ⁻ single crystal silicon substrate 129 before annealing. That way, by annealing, with p ⁺ anode layer 131, n ^- n ⁺ buffer layer is formed between the drift layer and the p ⁺ anode layer 131. Finally, the wafer is diced to complete the chip.

(About IGBT performance trade-off)
Next, IGBT characteristics and the like will be described. First, the trade-off of IGBT performance will be described. There is a trade-off relationship (so-called trade-off relationship) between the maximum voltage that can be held by the IGBT, that is, the magnitude of the withstand voltage and the voltage drop at the time of ON, and the higher the withstand voltage IGBT, the higher the on-voltage. Ultimately, the limit value of this trade-off relationship is determined by the physical properties of silicon. In order to improve this trade-off to the limit, it is necessary to devise on the design side, such as preventing local electric field concentration when holding the voltage.

  As another important index representing the performance of the IGBT, there is a trade-off relationship between on-voltage and switching loss (particularly, turn-off loss). Since the IGBT is a switching device, it operates from on to off or off to on. At the moment of this switching operation, a large loss per hour occurs. In general, an IGBT having a lower on-voltage has a slower turn-off loss, and therefore has a larger turn-off loss. By improving the trade-off relationship as described above, the performance of the IGBT can be improved. Note that the dependency of the turn-on loss on the on-voltage is small. The turn-on loss greatly depends on the characteristics of the freewheeling diode used in combination with the IGBT.

(Improvement of raid-off)
In order to optimize the trade-off relationship between the on-voltage and the turn-off loss (hereinafter referred to as the on-voltage-turn-off loss relationship), it is effective to optimize the internal excess carrier distribution when the IGBT is on. . In order to lower the on-voltage, the resistance value of the drift layer may be decreased by increasing the excess carrier amount. However, at the time of turn-off, it is necessary to sweep all the excess carriers out of the device or to disappear by electron-hole recombination. Therefore, increasing the excess carrier amount increases the turn-off loss. Therefore, in order to optimize this trade-off relationship, the turn-off loss may be minimized with the same on-voltage.

  To achieve the optimal trade-off, the ratio of the carrier concentration on the anode side and the cathode side should be about 1: 5 by lowering the carrier concentration on the anode side and increasing the carrier concentration on the cathode side. Good. Furthermore, the average carrier concentration in the drift layer may be increased by keeping the carrier lifetime of the drift layer as large as possible.

When the IGBT is turned off, the depletion layer extends from the pn junction on the cathode side into the drift layer and progresses toward the anode layer on the back surface. At that time, holes out of excess carriers in the drift layer are extracted from the end of the depletion layer by the electric field. In this way, an electron excess state occurs, and surplus electrons pass through the neutral region and are injected into the p-type anode layer. Then, since the anode side pn junction is slightly forward-biased, holes are reversely injected according to the injected electrons. The reversely injected holes merge with the holes extracted by the electric field described above and enter the depletion layer.

  Since carriers (here, holes) that are charge carriers pass through the electric field region and escape to the cathode side, the electric field works on the carriers. The work that the carriers receive from the electric field eventually becomes lattice vibration due to collision with a crystal lattice such as silicon, and is dissipated as heat. This dissipating energy becomes a turn-off loss. By the way, the energy dissipated by the carriers extracted before the depletion layer is fully extended is smaller than the energy dissipated by the carriers extracted when the depletion layer is fully extended. This is because if the depletion layer is not fully extended, the potential difference when carriers pass through the depletion layer is small, so that the work received from the electric field of the depletion layer is small.

  From a micro perspective, it looks like the above. From a macro viewpoint of the terminal voltage of the device, the product of the voltage and current (the current that flows before the anode-cathode voltage finishes rising, that is, the current that flows while the voltage rises) This means that the contribution to the loss expressed by (voltage × current) is small. From the above, the carrier distribution biased to the cathode side due to the IE effect described later turns off more than the carrier distribution of anode side bias under the condition that the proportion of carriers extracted at a low voltage is large and the on-voltage is the same. It can be seen that the loss is small.

  In order to lower the carrier concentration on the anode side, the total impurity amount in the anode layer may be lowered. This is not particularly difficult. However, in an IGBT having a low rated breakdown voltage such as 600 V, it is necessary to handle a wafer having a thickness of about 100 μm or thinner during the manufacturing process in order to reduce the total impurity amount of the anode layer. There are difficulties in production technology. On the other hand, the mechanism for increasing the carrier concentration on the cathode side is called the IE effect.

  As a cathode structure having a large IE effect, a HiGT structure in which a high-concentration n layer is inserted so as to surround a p base of a planar structure has been proposed (see, for example, Patent Document 1 and Patent Document 2). Further, in the trench gate structure, a CSTBT structure in which an n layer having a higher concentration than the drift layer is inserted in a mesa between adjacent trenches, an IEGT (Injection Enhancement Gate Transistor) structure, and the like have been proposed (for example, patents). Reference 3 and Non-Patent Document 1). In general, the IE effect in the trench type is larger than the IE effect in the planar type.

(IE effect)
The essence of the IE effect has been discussed and reported (for example, see Non-Patent Document 2). An IGBT equivalent circuit that is often drawn is a combination of a MOSFET (insulated gate field effect transistor having a metal-oxide-semiconductor structure) and a bipolar transistor. However, considering the actual device operation, it is considered to be a combination of the MOSFET 161, the pnp bipolar transistor 162, and the pin diode 163 as in the equivalent circuit shown in FIG.

FIG. 17 is a cross-sectional view showing a configuration of a main part of the planar IGBT. In FIG. 17, reference numeral 174 is a pnp bipolar transistor region (hereinafter referred to as a pnp-BJT region), and reference numeral 175 is a pin diode region. In FIG. 17, the solid line arrow represents the flow of electron current, and the dotted line arrow represents the flow of hole current. In this specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. In addition, the n ⁺ or p ⁺ region (including the layer) means a higher impurity concentration than the n or p region (including the layer) not marked with “+”. Further, the n ⁺⁺ region (including the layer) means a higher impurity concentration than the n ⁺ region (including the layer).

As shown in FIG. 17, electrons from the n ⁺⁺ region 176 of the surface of the MOS portion, an n ⁺ inversion layer 178 in the surface of the p layer 177 surrounding the n ⁺⁺ region 176, n ^- of the surface of the drift layer 179 It flows toward the p anode layer 181 on the back surface via the n ⁺ electron storage layer 180. A part of this electron current becomes a base current of the pnp-BJT region 174. In the pnp-BJT region 174, holes that have flowed from the p anode layer 181 by diffusion or drift only flow into the p layer 177, and the pn junction is slightly reverse-biased. Therefore, the concentration of minority carriers in the n ⁻ drift layer 179 near the pn junction, that is, the hole concentration, is extremely low.

On the other hand, the n cathode of the pin diode region 175 is the n ⁺ electron storage layer 180 on the surface of the n ⁻ drift layer 179. Since this n ⁺ / n ⁻ junction is slightly forward-biased, electrons are injected into the n ⁻ drift layer 179. At a large current, the electron concentration is much higher than the doping concentration of the n ⁻ drift layer 179 (high injection state). In order to satisfy the charge neutrality condition, holes having the same concentration as the electrons also exist. Therefore, the concentration of minority carriers in the n ⁻ drift layer 179 near the n ⁺ / n ⁻ junction, that is, the hole concentration, is extremely high.

In the IGBT, it is important to reduce the pnp-BJT region and increase the pin diode region in order to realize an optimum carrier distribution with cathode side bias. N ⁺ /
It is very important to increase the n ⁻ forward bias amount to facilitate electron injection. In the structure having the IE effect proposed so far, the ratio of the pin diode region is increased, and at the same time, the increase of the n ⁺ / n ⁻ forward bias amount is realized.

By the way, in the planar structure, when the ratio of the p base in the cell pitch is reduced, the on-voltage is reduced. This is because the ratio of the pin diode region is increased, the lateral current density near the surface is increased, and the voltage drop is increased, whereby n ⁺ /
It is considered that the effect of increasing the forward bias of the n ⁻ junction is great. The reason why the forward bias of the n ⁺ / n ⁻ junction becomes large is that the n ⁺ layer has a low resistance, so its potential is equal to the cathode potential, but the n ⁻ layer has a high resistance, so that the potential is Because it is lifted.

Similarly, the IE effect can be enhanced by reducing the ratio of the pnp-BJT region in the trench structure. In order to reduce the ratio of the pnp-BJT region, for example, the p base region may be set in a floating state in some mesa portions. The IE effect can also be increased by deepening the trench and separating the bottom of the trench from the pn junction. Further, the IE effect is increased by reducing the width of the mesa portion. In any case, it is considered that the density of the hole current flowing through the mesa portion increases, and the n ⁺ / n ⁻ forward bias due to the voltage drop increases.

Here, assuming that the doping concentration of the drift layer is Nd and the forward bias applied to the n ⁺ / n ⁻ junction is Vn, the electron concentration n on the n ⁻ layer side of the n ⁺ / n ⁻ junction is expressed by the following equation. . However, k is a Boltzmann constant and T is an absolute temperature.
n = Nd * exp (Vn / kT)

As is clear from the above equation, the electron concentration n on the cathode side increases exponentially according to the forward bias applied to the n ⁺ / n ⁻ junction. As means for increasing the forward bias amount, there is one that uses a voltage drop due to a large current as described above. Further, as described in Patent Documents 1 to 3, the forward bias amount can be increased by increasing the n ⁺ concentration. However, since the HiGT structure described in Patent Document 1 is a planar structure, if the concentration of the n ⁺ buffer layer on the surface side is too high, the forward breakdown voltage is greatly reduced.

On the other hand, in the CSTBT structure described in Patent Document 3, the n ⁺ buffer layer on the surface side is
It is sandwiched between trench gate oxide films and continues to the polysilicon potential via the gate oxide film. Therefore, when the forward voltage is maintained, that is, in the blocking mode, the n ⁺ buffer layer on the surface side is depleted not only from the pn junction but also from the boundary with the trench gate oxide film on both sides, so it is completely depleted with a low forward bias. Turn into. Therefore, the electric field inside the n ⁺ buffer layer on the surface side is relaxed despite the high concentration. Even if the forward bias is further increased, a local peak electric field is unlikely to appear due to the relaxation of the electric field at the mesa between the trenches.

This drifts a parallel pn structure in which vertical layered n-type regions and vertical layered p-type regions with increased impurity concentration are alternately joined instead of a uniform and single drift type drift layer. This is also in accordance with the principle of the superjunction MOSFET provided in the part. As described above, the CSTBT structure has a characteristic that the forward breakdown voltage is hardly lowered while enhancing the IE effect. Since the n ⁺ buffer layer on the surface side creates a diffusion potential with the n ⁻ drift layer and becomes a potential barrier for holes, the hole concentration in the drift layer increases.

Another explanation is that electrons are injected from the n ⁺ layer because a forward bias is applied between the n ⁺ buffer layer and the n ⁻ layer on the surface side. That is, in the n ⁺ / n ⁻ junction, if the n ⁺ layer has a high concentration, the electron injection efficiency is improved. Therefore, the ratio of the electron current injected into the n ⁻ layer with respect to the hole current entering the n ⁺ layer. Becomes larger. In order for holes to diffuse and flow as minority carriers in the n ⁺ layer, the n ⁺ / n ⁻ junction needs to be forward biased. The higher the n ⁺ layer concentration, the smaller the hole concentration as a minority carrier in the thermal equilibrium state. Therefore, a higher forward bias amount is required to flow the same hole current. When the forward bias amount is large, the electron current flowing into the n ⁻ layer increases, so that the electron concentration increases. This second description is physically a paraphrase of the first description.

JP 2003-347549 A Japanese translation of PCT publication No. 2002-532885 JP-A-8-316479 Eye. Ohmura (I. Omura) and three others, "Carrier injection enhancement effect of high voltage MOS devices-Devices physics and design concept-Devices of high voltage MOS devices-Devices physics and design concepts-Devices physics and design concepts-Devices ), ISPSD '97, p. 217-220 Florin Udrea, 1 other, "A unified analytic model for the carrier dynamics in trench insulated gate bipolar transistors (TIGBT) (A unified analytical for T ISPSD '95, p. 190-195

  A top gate type power device has been studied as a device for improving the trade-off between on-voltage and turn-off loss. However, the top gate type power device can improve the trade-off between on-state voltage and turn-off loss, but the hole current flows in a very narrow region in the cathode layer, so that the latch-up capability cannot be secured sufficiently. A point is mentioned as an example.

  In addition, in order to ensure the latch-up withstand capability, a means such as increasing the cathode layer may be considered, but if the cathode film is increased in thickness, the on-voltage increases or the breakdown voltage decreases, and the device characteristics deteriorate. A point is mentioned as an example.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of preventing a decrease in latch-up withstand capability in order to eliminate the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to a first aspect of the present invention is a semiconductor substrate of a first conductivity type and second conductors provided on the semiconductor substrate and arranged alternately. Type semiconductor region and semiconductor film having the first conductivity type semiconductor region, a polycrystalline semiconductor region provided on the semiconductor film via an insulating film, and the second conductivity type semiconductor region of the semiconductor film And an electrode provided so as to be in contact with the first conductivity type semiconductor region, and the first contact region of the electrode with respect to the second conductivity type semiconductor region is the first contact type semiconductor region with respect to the first conductivity type semiconductor region. It is a position closer to the polycrystalline semiconductor region than the second contact region of the electrode.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the first contact region has a larger area than the second contact region.

  According to a third aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein a difference in position between the first contact region and the second contact region is 1 μm or more with respect to the polycrystalline semiconductor region. It is characterized by being.

  According to the first to third aspects of the present invention, the first contact region can be formed more inside the semiconductor device than the second contact region. Therefore, a hole current can easily flow, and a decrease in the latch-up withstand capability can be reduced.

  According to the semiconductor device of the present invention, it is possible to prevent a decrease in latch-up resistance, which is a problem peculiar to a top gate type power device, without reducing the on-voltage and breakdown voltage characteristics of the top gate type power device. Play.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

(Embodiment 1)
First, a semiconductor device according to Embodiment 1 of the present invention will be described. FIG. 1 is an explanatory diagram showing the configuration of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, for example, an oxide film 21 is selectively formed on a first main surface of an n ⁻ single crystal silicon substrate (first conductivity type semiconductor substrate) 29 to be a drift layer.

The surface of oxide film 21 serving as an insulating film and the portion of n ⁻ single crystal silicon substrate 29 that is not covered with oxide film 21 are n-type at a higher concentration than the drift layer (n ⁻ single crystal silicon substrate 29). It is covered with a doped cathode film (semiconductor film) 24. The cathode film 24 may be made of, for example, polysilicon, or may be made of n-type single crystal silicon that is epitaxially grown from a portion of the n ⁻ single crystal silicon substrate 29 that is not covered with the oxide film 21. A portion of the cathode film 24 that contacts the n ⁻ single crystal silicon substrate 29 becomes an n ⁺ buffer region 25.

A portion of the cathode film 24 adjacent to the n ⁺ buffer region 25 is provided with a p base region 27 that is selectively p-doped. A p ⁺ base region 33 (second conductivity type semiconductor region) having a higher concentration than the p base region 27 is provided in a portion of the cathode film 24 away from the n ⁺ buffer region 25. The p ⁺ base region 33 is formed in a discontinuous island shape (rectangular shape) when viewed from above the stripe cell.

The n ⁺⁺ source region 26 (first conductivity type semiconductor region) is formed so as to be in contact with and sandwiched between the islands of the p ⁺ base region 33 when viewed from above the stripe cell. A gate oxide film 23 is selectively formed on the surface of the cathode film 24 so as to cover the n ⁺ buffer region 25 and a part of the p base region 27. On the gate oxide film 23, polysilicon (gate polysilicon) 22 (polycrystalline semiconductor region) serving as a gate electrode is deposited. The periphery of the gate polysilicon 22 is covered with an interlayer insulating film (not shown).

On the interlayer insulating film, n ⁺⁺ source region 26, p base region 27, and p ⁺ base region 33, an aluminum layer serving as an emitter electrode (not shown) is formed as an electrode. The emitter electrode is in contact with a part of the n ⁺⁺ source region 26 and is in contact with a part of the p ⁺ base region 33. The emitter electrode is in contact with the first contact region 30 a on the p ⁺ base region 33.

Further, the n ⁺⁺ source region 26 and a part of the p ⁺ base region 33 are in contact with each other at the second contact region 30b. The first contact region 30a and the second contact region 30b have a step with respect to a direction perpendicular to the direction (first direction) in which the p ⁺ base region 33 and the n ⁺⁺ source region 26 are formed and arranged. ing. Specifically, the first contact region 30 a is formed on the p ⁺ base region 33 at a position close to the p base region 27. That is, the first contact region 30a is formed at a position closer to the gate polysilicon 22 than the second contact region 30b.

  At this time, it is preferable that the step between the first contact region 30a and the second contact region 30b is 1 μm or more so that the step is reliably formed in consideration of a mask error. As described above, by forming the first contact region 30a closer to the gate polysilicon 22 than the second contact region 30b, that is, closer to the p base region 27, the hole current can easily flow.

A p ⁺ anode layer is formed on the second main surface (not shown) of the n ⁻ single crystal silicon substrate 29. An aluminum layer serving as an anode electrode is formed on the surface of the p ⁺ anode layer. Although not particularly illustrated, an n ⁺ buffer layer having a higher impurity concentration than the drift layer (n ⁻ single crystal silicon substrate 29) may be provided between the drift layer and the p ⁺ anode layer.

  As described above, according to the first embodiment, the first contact region is the gate polysilicon side, that is, the side on which the hole current close to the p base region is concentrated. Therefore, it is possible to facilitate the flow of hole current.

(Embodiment 2)
Next, the configuration of the semiconductor device according to the second embodiment of the present invention will be described. FIG. 2 is an explanatory diagram showing the configuration of the semiconductor device according to the second embodiment of the present invention. The difference from the first embodiment is that the width of the first contact region 30a in the direction (second direction) in which the p ⁺ base region 33 and the p base region 27 are formed is widened. . Thereby, the area of the first contact region 30a is larger than the area of the second contact region 30b.

Further, the side surface of the gate polysilicon 22 covering a part of the p base region 27 is set back in the second direction. The exposed area of the surface of the p base region 27 is increased. The first contact region 30 a is in contact with both the p ⁺ base region 33 and the p base region 27. Similar to the first embodiment, the first contact region 30a is formed at a position closer to the gate polysilicon 22 than the second contact region 30b.

  Specifically, the first contact region 30a is formed closer to the gate polysilicon 22 than the second contact region 30b. The rest of the configuration is the same as that of FIG.

  As described above, according to the second embodiment of the present invention, the first contact region is on the gate polysilicon side where the hole current is concentrated. Therefore, it is possible to facilitate the flow of hole current.

Next, the configuration of the semiconductor device used for comparing the characteristics of the semiconductor devices of the first and second embodiments described above will be described. FIG. 3 is an explanatory diagram (part 1) illustrating a configuration of a semiconductor device used for comparison of characteristics of the semiconductor devices of the first and second embodiments. In FIG. 3, the difference from the first embodiment is that the n ⁺⁺ source region 26 is formed in a discontinuous island shape (rectangular shape) when viewed from above the stripe cell.

A part of the n ⁺⁺ source region 26 extends below the emitter electrode (not shown) and contacts the emitter electrode, and the base region 27 is formed between the island of the n ⁺⁺ source region 26 and the island. The emitter electrode is in contact. Moreover, the contact part is formed with a first contact region 30a and a second contact region 30b in a straight line. Others are the same as those in the first embodiment, and thus description thereof is omitted.

  Next, another configuration of the semiconductor device used for comparing the characteristics of the semiconductor devices of the first and second embodiments described above will be described. FIG. 4 is an explanatory diagram (part 2) of the configuration of the semiconductor device used for comparing the characteristics of the semiconductor devices of the first and second embodiments. In FIG. 4, the difference from Embodiment 1 is that the first contact region 30a and the second contact region 30b are formed in a straight line. Others are the same as those in the first embodiment, and thus description thereof is omitted.

(Measurement result 1)
Next, as a measurement result 1, the positional relationship of the contact area of the cathode electrode is shown, and the characteristics of the anode current with respect to the voltage (Vak) applied between the anode and the cathode when the position of the contact area of the cathode electrode is changed are shown. .

FIG. 5A is an explanatory diagram illustrating the positional relationship of the cathode electrode (first contact region). 5A will be described using the semiconductor device illustrated in FIG. 3 as an example. 5A, portions corresponding to the respective portions of the semiconductor device illustrated in FIG. 3 are denoted by the same reference numerals as those in FIG. 3. In FIG. 5A, the vertical axis represents the distance in the thickness direction of the semiconductor device, and the horizontal axis represents the distance from one end of the p ⁺ base region 33 in the second direction. Here, on the horizontal axis, one end of the p ⁺ base region 33 is set to zero.

Reference numeral 50 denotes a first contact region 30 a in which the emitter electrode is in contact with the p ⁺ base region 33. In FIG. 5A, the first contact region 30a is displayed with a thickness for convenience. In the first embodiment, the width of the first contact region 30a is 0.6 μm. In the description of FIGS. 5A and 5B, the first contact areas are denoted by reference numerals 51 to 57 in order to distinguish the positions where the first contact areas 30a are formed.

Specifically, reference numerals 51 to 56 denote first contact regions formed so as to be shifted from the one end of the p ⁺ base region 33 of the semiconductor device toward the gate polysilicon 22 by 0.3 μm in the second direction. Specifically, the first contact region 51 is formed between one end (0 μm) to 0.6 μm of the p ⁺ base region 33. The first contact region 52 is formed in a range of 0.3 to 0.9 μm from the outer end of the p ⁺ base region 33.

The first contact region 57 is the first contact region 30a shown in the second embodiment. Specifically, reference numeral 57 is formed in the range of 0.6 μm to 3.0 μm from one end of the p ⁺ base region 33. In addition, the first contact region 30a (51 to 57) is in contact with the surface of the p ⁺ base region 33. However, in FIG. It is displayed with a step.

Next, the characteristics of the anode current with respect to the voltage (Vak) applied between the anode and the cathode by changing the position of each contact electrode described above will be described. FIG. 5-2 is a graph showing the characteristics of the anode current with respect to the voltage (Vak) applied between the anode and the cathode. In FIG. 5B, the vertical axis represents Ia (anode current) (A / cm ² ), and the horizontal axis represents the voltage (Vak) (V) applied between the anode and the cathode. Moreover, the waveform 60 shows the case where the 1st contact area | region 30a is not formed, and the code | symbols 61-67 have the contact area 0-0.6 micrometer, 0.3-0.9 micrometer, 0.6-1.2 micrometer. , 0.9 to 1.8 μm, 1.5 to 2.1 μm, and 0.6 to 3.0 μm. The anode current was measured at 125 ° C. with a gate voltage of 15V.

Reference numeral 68 denotes an anode current characteristic of a conventional IGBT (ON voltage = 2.58 V). As shown in FIG. 5B, as the first contact region 30a approaches the gate polysilicon 22 side from one end of the p ⁺ base region 33, the value of the voltage at which the anode current increases sharply increases. Thus, it can be seen that the latch-up resistance increases as the first contact region 30a is closer to the gate polysilicon 22 side from one end of the p ⁺ base region 33.

(Measurement result 2)
Next, as the measurement result 2, the characteristics of the anode current with respect to the voltage (Vak) applied between the anode and the cathode of the semiconductor device shown in FIGS. FIG. 6 is a graph showing the characteristics of the anode current with respect to the voltage applied between the anode and the cathode.

In FIG. 6, the vertical axis indicates Ia (anode current) (A / cm ² ), and the horizontal axis indicates the voltage (Vak) (V) applied between the anode and the cathode. The anode current was measured at 125 ° C. with a gate voltage of 15V. Furthermore, the rated voltage is 1200 V and the rated current is 100 A / cm ² . A waveform 71 is the current characteristic of the semiconductor device of the first embodiment (FIG. 1), a waveform 72 is the second embodiment (FIG. 2), a waveform 73 is FIG. 3, and a waveform 74 is the current characteristic of the semiconductor device of FIG.

  As a reference, the waveform 75 shows the anode current characteristics of a conventional planar IGBT. As shown in FIG. 6, in the waveform 73 and the waveform 74, the anode current increases from about 10 V, and the anode current increases and latches up. On the other hand, in the waveform 71, the voltage applied between the anode and the cathode is greatly increased from about 500V, and the latch-up resistance is improved. Further, in the waveform 74, the latch-up resistance is further improved.

  In the top gate type device, the path through which the hole current flows is narrower than that of the planar IGBT and the trench IGBT. As a result, current concentrates and latch-up is likely to occur. As shown in the graph of FIG. 6, in the case of the semiconductor device having the configuration shown in FIG. 3, a sufficient latch-up resistance is not obtained. Further, the semiconductor device having the configuration shown in FIG. 4 has a structure in which the channel is thinned out, and the latch-up resistance is increased as compared with the configuration of the semiconductor device in FIG.

In contrast, in the first embodiment (FIG. 1), the hole current is brought into contact with the p ⁺ base region 33 and the cathode electrode on the side where the hole current is concentrated (the side where the gate polysilicon 22 is formed). The drawer is done. For this reason, the latch-up resistance is increased as compared with the semiconductor devices of FIGS. Further, in the semiconductor device shown in FIG. 2, the cathode electrode is brought into contact with the p ⁺ base region 33 and the p base region 27 in order to draw a hole current inside the semiconductor device. As a result, the latch-up tolerance became a value close to that of the prior art shown by the waveform 75.

  As described above, according to the semiconductor device of the present invention, it is possible to prevent a decrease in latch-up resistance, which is a problem peculiar to the top gate type power device, without reducing the on-voltage and breakdown voltage characteristics of the top gate type power device. Can do.

  As described above, the semiconductor device according to the present invention is useful for a power semiconductor device used for a power conversion device or the like, and is particularly suitable for an IGBT.

It is explanatory drawing shown about the structure of the semiconductor device concerning Embodiment 1 of this invention. It is explanatory drawing which shows the structure of the semiconductor device concerning Embodiment 2 of this invention. FIG. 3 is an explanatory diagram (No. 1) showing a configuration of a semiconductor device used for comparison of characteristics of the semiconductor devices of the first and second embodiments. FIG. 5 is an explanatory diagram (No. 2) showing a configuration of a semiconductor device used for comparison of characteristics of the semiconductor devices of the first and second embodiments. It is explanatory drawing shown about the positional relationship of a cathode electrode (1st contact area | region). It is a graph which shows about the characteristic of the anode electric current with respect to the voltage (Vak) applied between anode and cathode. It is a graph which shows the characteristic of the anode current with respect to the voltage applied between anode and cathode. It is explanatory drawing shown about the structure of IGBT. It is sectional drawing which shows the manufacturing method of IGBT shown in FIG. It is sectional drawing which shows the manufacturing method of IGBT shown in FIG. It is sectional drawing which shows the manufacturing method of IGBT shown in FIG. It is sectional drawing which shows the manufacturing method of IGBT shown in FIG. It is sectional drawing which shows the manufacturing method of IGBT shown in FIG. It is sectional drawing which shows the manufacturing method of IGBT shown in FIG. It is sectional drawing which shows the manufacturing method of IGBT shown in FIG. It is sectional drawing which shows the manufacturing method of IGBT shown in FIG. It is explanatory drawing which shows the equivalent circuit of IGBT. It is sectional drawing which shows the structure of the principal part of planar type IGBT.

Explanation of symbols

21 oxide film 22 gate polysilicon 23 gate insulating film 24 cathode film 25 n ⁺ buffer region 26 n ⁺⁺ source region 27 p base region 29 n ^- single crystal silicon substrate 30a first contact region 30b second contact region 33 p ⁺ base region

Claims (3)

A first conductivity type semiconductor substrate;
A semiconductor film having a second conductivity type semiconductor region and a first conductivity type semiconductor region provided on the semiconductor substrate and arranged alternately;
A polycrystalline semiconductor region provided on the semiconductor film via an insulating film;
An electrode provided in contact with the semiconductor region of the second conductivity type and the semiconductor region of the first conductivity type of the semiconductor film,
The first contact region of the electrode with respect to the semiconductor region of the second conductivity type is
A semiconductor device, wherein the semiconductor device is located closer to the polycrystalline semiconductor region than a second contact region of the electrode with respect to the first conductivity type semiconductor region.   The semiconductor device according to claim 1, wherein the first contact region has a larger area than the second contact region. The semiconductor device according to claim 1, wherein a difference in position between the first contact region and the second contact region is 1 μm or more with respect to the polycrystalline semiconductor region.

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