JP2007157861A - Mos semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a MOS semiconductor device capable of improving the trade-off relationship of an on-state voltage and a turn-off loss without a trench MOS gate structure, and capable of preventing the lowering of a latch-up resistance. <P>SOLUTION: In the MOS semiconductor device, a substrate insulating film with first and second openings and one conductive semiconductor deposit film are formed on one conductive semiconductor substrate. In the semiconductor device; the semiconductor deposit film has the other conductive base region, one conductive emitter region, a first buffer region brought into contact with the substrate in the first opening section, and a second buffer region positioned on the reverse side and brought into contact with the substrate in the second opening section. In the semiconductor device, a gate electrode film and an inter-layer insulating film are formed on the surface of a base region held by the first buffer region and the emitter region through a gate insulating film, and an emitter electrode is brought into contact with the emitter region and the base region. In such a MOS semiconductor device, the width of the first opening section is set at 5 μm or less. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a MOS semiconductor device, and more particularly to a power MOS semiconductor device constituting an IGBT (insulated gate bipolar transistor).

With regard to IGBTs, performance has been improved by many improvements so far. Here, the performance of the IGBT means that when it is off, the voltage is maintained and the current is completely cut off. On the other hand, when it is on, the current can flow with the smallest possible voltage drop, that is, with low on-resistance. It is the performance as a switch with few. In view of the nature of the operation of the IGBT, when the IGBT is described, the collector is expressed as “anode” and the emitter is expressed as “cathode”. Hereinafter, in order to explain the present invention to be described later, an IGBT is particularly taken up as an example of the present invention, and its characteristics and the like will be described.
(About IGBT performance trade-off)
There is a trade-off relationship (so-called trade-off relationship) between the maximum voltage that can be held by the IGBT, that is, the magnitude of the withstand voltage and the voltage drop at the time of ON, and the higher the withstand voltage IGBT, the higher the on-voltage. Ultimately, the limit value of this trade-off relationship is determined by the physical properties of silicon. In order to improve this trade-off to the limit, it is necessary to devise in terms of the structural design of the element, such as preventing local electric field concentration during voltage holding.

  As another important index representing the performance of the IGBT, there is a trade-off relationship between on-voltage and switching loss (particularly, turn-off loss). Since the IGBT is a switching device, a switching operation, that is, an on / off operation is repeatedly performed. A large loss per unit time occurs during the transition period of the switching operation. In general, an IGBT having a lower on-voltage has a slower turn-off, so that the turn-off loss increases, and an attempt to reduce the turn-off loss increases the on-voltage. It is said that there is a trade-off relationship between on-state voltage and turn-off loss. By improving such a trade-off relationship, the IGBT can further improve electrical characteristics. On the other hand, the turn-on loss is less dependent on the on-voltage. The turn-on loss greatly depends on the characteristics of the freewheeling diode used in combination.

In order to optimize the trade-off relationship between the on-voltage and the turn-off loss, it is effective to optimize the excess carrier distribution in the on-state of the IGBT. In order to lower the on-voltage, the resistance value of the drift layer may be decreased by increasing the excess carrier amount. However, if excessive carriers are increased in order to reduce the on-voltage, at the time of turn-off, it is necessary to sweep all the increased excess carriers out of the drift layer or to disappear by carrier recombination. This results in an increase in turn-off loss because more is required. Therefore, in order to optimize this trade-off relationship, the turn-off loss may be minimized with the same on-voltage.
To achieve the optimal trade-off, the ratio of the carrier concentration on the anode side and the cathode side should be about 1: 5 by lowering the carrier concentration on the anode side and increasing the carrier concentration on the cathode side. Good. Furthermore, the average carrier concentration in the drift layer may be increased by keeping the carrier lifetime in the drift layer as large as possible. This will be described below.

When the IGBT is turned off, the depletion layer extends from the pn junction on the cathode side into the drift layer and progresses toward the anode layer on the back surface. At that time, holes out of excess carriers in the drift layer are extracted from the end of the depletion layer by the electric field. In this way, an electron excess state occurs, and surplus electrons pass through the neutral region and are injected into the p-type anode layer. Then, since the anode side pn junction is slightly forward-biased, holes are reversely injected according to the injected electrons. The reversely injected holes merge with the holes extracted by the electric field described above and enter the depletion layer.
Since carriers (here, holes) that are charge carriers pass through the electric field region and escape to the cathode side, the electric field works on the carriers. The work that carriers receive from the electric field at the time of turn-off eventually becomes lattice vibration due to collision with a crystal lattice such as silicon, and is dissipated as heat. This dissipating energy becomes a turn-off loss. By the way, the energy dissipated by the carriers extracted before the depletion layer is fully extended is smaller than the energy dissipated by the carriers extracted when the depletion layer is fully extended. This is because if the depletion layer is not fully extended, the potential difference when carriers pass through the depletion layer is small, so that the work received from the electric field of the depletion layer is small.

From the microscopic viewpoint of career movement, it is as described above. From a macro viewpoint of the terminal voltage of the device, the product of the voltage and current (the current that flows before the anode-cathode voltage finishes rising, that is, the current that flows while the voltage rises) This means that the contribution to the loss expressed by (voltage × current) is small. From the above, the carrier distribution biased to the cathode side due to the IE effect described later turns off more than the carrier distribution of anode side bias under the condition that the proportion of carriers extracted at a low voltage is large and the on-voltage is the same. It can be seen that the loss is small.
In order to lower the carrier concentration on the anode side, the total impurity amount in the anode layer may be lowered. This is not particularly difficult. However, in an IGBT having a low rated breakdown voltage such as 600 V, it is necessary to handle a wafer having a thickness of about 100 μm or thinner during the manufacturing process in order to reduce the total impurity amount of the anode layer. Difficulties exist from a production engineering perspective. On the other hand, the mechanism for increasing the carrier concentration on the cathode side is called the IE effect.

As a cathode structure having a large IE effect, a HiGT structure in which a high-concentration n layer is inserted so as to surround a p base of a planar structure has been proposed (see, for example, Patent Document 1 and Patent Document 2). Further, in the trench gate structure, a CSTBT structure in which an n layer having a higher concentration than the drift layer is inserted in a mesa between adjacent trenches, an IEGT (Injection Enhancement Gate Transistor) structure, and the like have been proposed (for example, patents). Reference 3 and Non-Patent Document 1). In general, the IE effect in the trench type is larger than the IE effect in the planar type.
The technical concept of the IE effect is a known technique as already discussed and reported on its essence (see, for example, Non-Patent Document 2). An IGBT equivalent circuit that is often drawn is a combination of a MOSFET (insulated gate field effect transistor having a metal-oxide-semiconductor structure) and a bipolar transistor. However, considering the actual device operation, it is considered that the combination of the MOSFET 101, the pnp bipolar transistor 102, and the pin diode 103 is equivalent to the equivalent circuit shown in FIG.

FIG. 7 is a cross-sectional view showing a configuration of a main part of the planar IGBT. In FIG. 7, reference numeral 102 denotes a pnp bipolar transistor region (hereinafter referred to as a pnp-BJT region), and reference numeral 103 denotes a pin diode region. In FIG. 7, the solid line arrows represent the flow of electron current, and the dotted line arrows represent the flow of hole current.
As shown in FIG. 7, n electrons, the n ⁺⁺ region 6 of the surface of the MOS section 101, the surface of p base region 7 surrounding the n ⁺⁺ region 6, which is formed by the gate voltage applied to the gate electrode (not shown) It flows toward the p anode layer 11 on the back surface via the channel 8 and the n ⁺ electron storage layer 10 on the surface of the n ⁻ drift layer 9. A part of this electron current becomes a base current of the pnp-BJT region 102. In the pnp-BJT region 102, the holes coming from the p anode layer 11 by diffusion or drift are only collected in the p base region 7, and the pn junction (the pn junction between the p base region 7 and the n ⁻ drift layer 9). The junction is slightly reverse biased. Therefore, the concentration of minority carriers, that is, holes in the n ⁻ drift layer 9 near the pn junction is extremely low.

On the other hand, the n cathode of the pin diode region 103 is the n ⁺ electron storage layer 10 on the surface of the n ⁻ drift layer 9. Since the junction between the n ⁺ electron storage layer 10 and the n ⁻ drift layer 9 (hereinafter abbreviated as n ⁺ / n ⁻ junction) is slightly forward-biased, electrons are injected into the n ⁻ drift layer 9. The When the current is large, the electron concentration is much higher than the doping concentration of the n ⁻ drift layer 9 (high injection state). In order to satisfy the charge neutrality condition, holes having the same concentration as the electrons also exist. Accordingly, the concentration of minority carriers in the n ⁻ drift layer 9 near the n ⁺ / n ⁻ junction, that is, the hole concentration, is extremely high.
In the IGBT, it is important to reduce the pnp-BJT region and increase the pin diode region in order to realize an optimum carrier distribution with cathode side bias. It is very important to increase the forward bias amount of the n ⁺ / n ⁻ junction to promote electron injection. In the structure having the IE effect proposed so far, the forward bias of the n ⁺ / n ⁻ junction is increased at the same time as the ratio of the pin diode region is increased.

By the way, in the planar structure IGBT, when the ratio of the p base in the cell pitch is reduced, the on-voltage is reduced. This is because, in addition to the increase in the ratio of the pin diode region, the lateral current density near the surface is increased and the voltage drop is increased, so that the forward bias of the n ⁺ / n ⁻ junction is increased. It is explained that the effect is large. Changing the viewpoint, the n ^{+ /} n ^- because the layer is a high resistance ^- the forward bias of the junction becomes large, since the n ⁺ layer has a low resistance, the potential is approximately equal to the cathode potential, n It can also be said that the potential is raised by a voltage drop due to a large current.
Similarly, in a trench structure IGBT, the IE effect can be enhanced by reducing the ratio of the pnp-BJT region. In order to reduce the ratio of the pnp-BJT region, for example, the p base region may be set in a floating state in some mesa portions. The IE effect can also be increased by deepening the trench and separating the bottom of the trench from the pn junction. Further, the IE effect is increased by reducing the width of the mesa portion. In any case, it is considered that the hole current density flowing through the mesa portion is increased and the forward bias of the n ⁺ / n ⁻ junction due to the voltage drop is increased.

Here, when the doping concentration of the drift layer is Nd and the forward bias applied to the n ⁺ / n ⁻ junction is Vn, the electron concentration n on the n ⁻ layer side of the n ⁺ / n ⁻ junction is expressed by the following equation: . However, k is a Boltzmann constant and T is an absolute temperature.
n = Nd exp (Vn / kT)
As is apparent from the above equation, the electron concentration n on the cathode side increases exponentially according to the forward bias applied to the n ⁺ / n ⁻ junction. As means for increasing the forward bias amount, there is one that uses a voltage drop due to a large current as described above. Further, as described in Patent Documents 1 to 3, the forward bias amount can be increased by increasing the n-type impurity concentration. However, since the HiGT structure described in Patent Document 1 is a planar structure, if the n-type impurity concentration in the n ⁺ buffer region on the surface side is too high, the forward breakdown voltage is greatly reduced.

On the other hand, in the CSTBT structure described in Patent Document 3, the n ⁺ buffer region on the surface side is sandwiched between trench gate oxide films, and continues to the polysilicon potential via the gate oxide film. Therefore, when the forward voltage is maintained, that is, in the blocking mode, the n ⁺ buffer region on the surface side is depleted not only from the pn junction but also from the boundary with the trench gate oxide film on both sides, so that it is completely depleted with a low forward bias. Turn into. Therefore, although the n ⁺ buffer region on the surface side has a high concentration, the electric field inside it is relaxed. Even if the forward bias is further increased, a local peak electric field is unlikely to appear due to the relaxation of the electric field at the mesa between the trenches. As described above, the CSTBT structure has a characteristic that the forward breakdown voltage is hardly lowered while enhancing the IE effect. The n ⁺ buffer region on the surface side creates a diffusion potential with the n ⁻ drift layer and becomes a potential barrier for holes, so that the hole concentration in the drift layer increases (first explanation).

As a second explanation, n ⁺ buffer region and the n surface-side ^- because between the layers is forward biased, it is possible that the n ⁺ buffer region is because electrons are injected. That is, in the n ⁺ / n ⁻ junction, if the n ⁺ buffer region has a high concentration, the electron injection efficiency is improved. Therefore, the electron current injected into the n ⁻ layer with respect to the hole current entering the n ⁺ buffer region. The ratio of increases. In order for holes to diffuse and flow as minority carriers in the n ⁺ buffer region, the n ⁺ / n ⁻ junction needs to be forward biased. The higher the n ⁺ buffer region concentration, the smaller the hole concentration as minority carriers in the thermal equilibrium state. Therefore, a higher forward bias amount is required to allow the same hole current to flow. When the forward bias amount is large, the electron current flowing into the n ⁻ layer increases, so that the electron concentration increases. This second explanation is physically a paraphrase of the first explanation. As described above, it is known that even in the conventional IGBT, in order to optimize the trade-off between the on-voltage and the turn-off loss, it is preferable that the element structure has a carrier distribution concentrated on the cathode side due to the IE effect. ing.

In addition, it is described that by providing a buried oxide film so as to be in contact with the bottom surface of the base region, an excessive current is prevented by flowing a parasitic transistor current in a region having a low current amplification factor, thereby improving breakdown resistance ( Patent Document 4-Abstract). Furthermore, by using a buried oxide film, the current amplification factor of the parasitic bipolar transistor is effectively reduced without increasing the on-resistance of the MOSFET, and the invention relates to a MOSFET that can simultaneously satisfy the low on-resistance and the high breakdown resistance. Is known (Patent Document 5-Abstract).
JP 2003-347549 A Japanese translation of PCT publication No. 2002-532885 JP-A-8-316479 JP-A-9-153609 JP-A-9-270513 Eye. Ohmura (I. Omura) and three others, "Carrier injection enhancement effect of high voltage MOS devices-Devices physics and design concept-Devices of high voltage MOS devices-Devices" 97, p. 217-220 Florin Udrea, 1 other, "A unified analytic model for the carrier dynamics in trench insulated gate bipolar transistors (TIGBT) (A unified analytical for T ISPSD '95, p. 190-195

However, the above-described optimization of the on-voltage-turn-off loss trade-off is not necessarily sufficient, and if the cathode-side carrier concentration in the on-state can be further increased, the trade-off can be further improved. it is conceivable that. That is, it cannot be said that the above-mentioned IE effect is sufficiently exhibited in a conventional MOS type semiconductor device such as an IGBT. This is because even if the trench gate structure is adopted like the CSTBT structure and the IEGT structure described above, the trade-off characteristic is improved as compared with the previous one, but the trade-off characteristic is still improved by further miniaturization. Because there is room to do.
On the other hand, the manufacturing process of the MOS type semiconductor device having the trench gate structure shows a certain trade-off improvement effect as described above, but is longer and complicated than the manufacturing process of the planar structure. As a result, the yield of non-defective products is low, and the product cost tends to be relatively high. However, if further refinement is attempted to improve the characteristics, the yield of non-defective products decreases and the manufacturing cost further increases. Expected to be higher. Therefore, it is important from the viewpoint of the yield rate and the product cost that the trade-off characteristics can be improved even if miniaturization is not advanced to the ultimate or the trench gate structure is not used. Further, in the MOS type semiconductor device having a trench gate structure, an electric field is likely to be concentrated on the bottom of the trench, and a breakdown in breakdown voltage is likely to occur. Further, there is a problem peculiar to the trench gate structure in that when the gate is set to a negative potential with respect to the cathode, the electric field strength at the bottom of the trench increases and the breakdown voltage deteriorates.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to eliminate problems such as a decrease in non-defective product rate and an increase in product cost caused by the adoption of a trench gate structure. The present invention provides a MOS type semiconductor device that can further improve the trade-off relationship between the on-state voltage and the turn-off loss without using a MOS gate structure, and can prevent a decrease in latch-up resistance.

  According to the first aspect of the present invention, the substrate insulating film having the first opening and the second opening on one main surface of the one-conductivity type semiconductor substrate, the substrate insulating film, and the A one-conductivity-type semiconductor crystal film deposited on both openings, wherein the one-conductivity-type semiconductor crystal film is selectively formed in the film; and in the other-conductivity-type base region One-conductivity-type emitter region formed on the surface, a first buffer region including the one-conductivity-type semiconductor crystal film portion in contact with the semiconductor substrate at the first opening, and the other-conductivity-type base region A first buffer region comprising a second buffer region that is formed of the one-conductivity-type semiconductor crystal film portion located on the opposite side of the first buffer region and contacts the semiconductor substrate at the second opening, The sandwiched between the one conductivity type emitter region The surface of the conductive base region is provided with a polycrystalline semiconductor gate electrode film and an interlayer insulating film covering the polycrystalline semiconductor gate electrode film with a gate insulating film interposed therebetween, and an emitter electrode is connected to the surface of the one conductive type emitter region and the other conductive material. In the MOS type semiconductor device in contact with the surface of the mold base region, the object is achieved by making the MOS type semiconductor device wherein the width of the first opening is 5 μm or less.

According to a second aspect of the present invention, the MOS type semiconductor device according to the first aspect of the present invention is such that the distance between the other conductivity type base region and the first opening is 4 μm or less. Is.
According to the third aspect of the present invention, it is preferable that the MOS type semiconductor device according to the first or second aspect has a width of 2 μm or less.
According to the invention of claim 4, the distance between the other conductivity type base region and the end of the second opening is in the range of 0.5 μm to 1 μm. It is desirable that the MOS type semiconductor device according to any one of items 1 to 3 is used.
According to the invention of claim 5, the impurity concentration range of the first or second buffer region is any one of 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ . The MOS type semiconductor device according to any one of claims 1 to 4 is more preferable.
According to the invention described in claim 6, the thickness of the substrate insulating film is in the range of 0.05 to 1 μm. It is preferable to use the MOS type semiconductor device described in 1.

  According to the present invention, it is possible to provide a MOS type semiconductor device that can further improve the trade-off relationship between the on-voltage and the turn-off loss without using the trench MOS gate structure and prevent the latch-up withstand capability from being lowered.

Hereinafter, a method for manufacturing a MOS semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
FIG. 1 is a sectional view of an essential part of a MOS type semiconductor device according to the present invention. FIG. 2 is a cross-sectional view of the main part of a comparative MOS type semiconductor device for comparison with the MOS type semiconductor device according to the present invention. FIG. 3 is a cross-sectional view of the main part of the MOS semiconductor device for explaining the carrier flow of the MOS semiconductor device according to the present invention. FIG. 4 is a voltage-current waveform diagram of the top gate type MOS semiconductor device. FIG. 5 is a relationship diagram between the ON voltage and the distance between the second opening end and the p-type base region end according to the present invention. 8 to 10 are cross-sectional views of the main part of the semiconductor substrate in the main manufacturing process of the IGBT manufacturing method having the top gate type high surface injection structure according to the present invention, and FIG. FIG. 9 is a sectional view (Part 2) of a principal part of a semiconductor substrate shown in the order of the manufacturing process, and FIG. 10 is a sectional view (Part 3) of a relevant part of the semiconductor substrate shown in the order of the manufacturing process.

8 to 10 are for explaining a manufacturing method to which lateral epitaxial growth is applied to an IGBT having a top gate type high surface injection structure according to the present invention. In the above-mentioned top gate type, a gate electrode is disposed via a gate oxide film on a base region formed on an epitaxial semiconductor layer deposited on a semiconductor substrate with a substrate insulating film sandwiched therebetween, and the gate electrode is directly under the gate oxide film. A structure in which a channel region is formed on the surface of the base region. The manufacturing method using lateral epitaxial growth is a manufacturing method in which a semiconductor crystal layer is formed on the entire surface by epitaxially growing a semiconductor layer also laterally on the substrate insulating film using an opening provided in the substrate insulating film. Say.
As shown in FIG. 8A, the mirror polished surface of the n-type FZ-silicon substrate 21 is used as the substrate. The specific resistance of the substrate is preferably 30 to 200 Ωcm, and is selected according to the breakdown voltage of the IGBT. For example, if an 80Ωcm substrate 21 is used, an IGBT having a withstand voltage of 1200 V can be obtained. An oxide film 22 having a film thickness range of 0.3 μm to 1 μm is formed on the substrate 21 by thermal oxidation or CVD growth. Next, as shown in FIG. 8B, patterning with a photoresist is performed on the film, and the oxide film 22 is selectively dry etched in a stripe shape to form a large opening 23. At this time, the cell pitch is preferably 5 to 20 μm, and the width of the stripe-shaped oxide film 22 is preferably 0.5 μm to 2 μm. Here, the width of the oxide film 22 is 1 μm, and the cell pitch width is 10 μm. Subsequently, as shown in FIG. 8C, after the substrate oxide film 24 is formed on the entire surface by thermal oxidation or CVD, the first opening 25-1 having a width of 2 μm is formed in the center of the substrate oxide film 24 by photolithography. A second opening 25-2 having a width of 1 μm is formed. The thickness of the substrate oxide film 24 is preferably 0.05 μm to 0.2 μm, and the protruding amount of the end portion (thickness of the plate-like oxide film 22) is preferably in the range of 0.3 μm to 1 μm. The substrate oxide film thickness was 0.1 μm, and the protrusion amount (film thickness) at the end was 0.5 μm.

When the width of the first opening is 5 μm or less, the p base region is hidden by the substrate oxide film, and the hole extraction effect is effectively reduced. Therefore, the effect of the present invention that the on-voltage is lowered becomes significant.
Thereafter, as shown in FIG. 8D, an n-type silicon epitaxial layer 26 is grown using the surface of the silicon substrate 21 exposed through the opening as a seed layer. As a typical process gas, a main gas is dicyclosilane or trichlorosilane, hydrogen gas is a carrier gas, and arsine or phosphine is added as a doping gas. The reaction pressure is preferably 100 to 760 Torr (1 Torr = 133.3 Pa) and the semiconductor substrate (wafer) temperature is about 1000 ° C. Here, phosphine was used as a doping gas, and the conditions were controlled so that the phosphorus concentration in the film was 1 × 10 ¹⁶ cm ⁻³ . If the growth surface becomes higher than the position of the upper surface of the substrate oxide film 24 after starting the growth of the n-type epitaxial layer 26, the growth proceeds in the lateral direction. Thereafter, the gas supply is stopped when the entire surface is covered by overcoming the protruding portion (the film thickness portion of the oxide film 22) 22 at the end, and the growth is stopped.

  Next, the wafer 21 is loaded into a CMP apparatus and polished until the surface of the n-type epitaxial layer (single crystal silicon layer) 26 has a flat cross-sectional shape as shown in FIG. 9E using the oxide film 22 as a stopper film. I do. What is important at this time is that the etching selectivity (Si polishing rate / oxide film polishing rate) is increased to 50 times or more, preferably 100 times or more, and polishing is reliably stopped at the reference oxide film (stopper film) 22. That is. For this purpose, it is effective to use, for example, high-purity colloidal silica slurry planarlite-6103 manufactured by Fujimi Incorporated. Typical polishing conditions were a top ring pressure of 300 to 600 hPa and a table rotation speed of 50 to 100 rpm. The selection ratio at this time is about 100 times. Although the polishing time may be constant, it is effective to detect some end point in order to suppress the occurrence of insufficient polishing (epitaxial layer residue on the oxide film protrusion) and excessive polishing (dishing). For this purpose, motor torque detection, reflected light measurement, and the like can be considered. Here, by using motor torque detection, polishing defects are suppressed, and the thickness of the n-type epitaxial layer 26 is made substantially constant.

Subsequently, as shown in FIG. 9F, a gate oxide film 27 is formed on the entire surface by thermal oxidation or CVD. Here, the thermal oxide film was formed with a thickness of 0.1 μm. Next, as shown in FIG. 9G, a polysilicon layer 28 to be a gate electrode is formed on the entire surface by CVD with a thickness of about 0.5 .mu.m. Thereafter, as shown in FIG. The silicon layer 28 is partially removed. Subsequently, using the remaining polysilicon layer 28 as a mask, boron ions with a dose amount of 5 × 10 ¹⁴ cm ⁻² and a dose amount of 1 × 10 ¹⁵ cm ⁻² are applied to the n-type epitaxial layer (single crystal silicon layer) 26. Arsenic ions are implanted and drive diffusion is performed at 1150 ° C. for 2 hours in a nitrogen atmosphere to form a p-type channel region (p-type base region) 29 and an n ⁺⁺ type source region 30. Of the n-type epitaxial layer (single crystal silicon layer) 26 in which the p-type channel region (p-type base region) 29 is not formed, a portion in contact with the first opening 25-1 is defined as the first buffer region 26-1. A portion in contact with the second opening 25-2 is defined as a second buffer region 26-2. The on-voltage can be effectively lowered when the distance (interval) between the end of the p-type base region 29 and the end of the first opening 25-1 in the second opening 26-1 is 4 μm or less. However, since the voltage increases when the first opening 25-1 and the p-type base region 29 end overlap, it is not preferable. If the width of the second opening 25-2 is 2 μm or more, the p-type base region 29 (or the second p ⁺ region) overlaps with the second opening, which is not preferable.

Thereafter, as shown in FIG. 10I, a BPSG film 31 having a thickness of about 1 μm is formed on the entire surface to form an interlayer insulating film. Subsequently, an opening 32 for emitter electrode contact is formed. Next, by forming an aluminum electrode (emitter electrode) 33 having a film thickness of 5 μm as shown in FIG. 10J, the MOS gate structure on the surface side of the IGBT according to the embodiment of the present invention is completed. An enlarged view of FIG. 10 (j) is shown in FIG.
In FIG. 1, a p ⁺ contact region 34 (hereinafter referred to as a P ⁺ region) that has not been described in the manufacturing method using FIGS. 8 to 10 is written, but this layer improves the contact property with the metal emitter layer, It is desirable to form the p base region since the effect of reducing the resistance of the p base region can be obtained.
The IGBT according to this embodiment has the following advantages.
1. By forming the channel region 29 in the n-type epitaxial layer 26, carrier mobility increases and resistance loss decreases.

2. Since the channel region 29 is formed of an epitaxial layer (single crystal silicon layer), the leakage current during forward blocking is reduced.
3. The thickness of the epitaxial layer 26 can be reduced and the film thickness can be made uniform by CMP using the oxide film 22 as a stopper. This leads to an improvement in the breakdown voltage of the IGBT and a reduction in characteristic variation.
Next, the improvement of the latch-up resistance according to the effect of the present invention will be described in detail.
3A and 3B are cross-sectional views of the main part showing the flow of electrons and holes during latch-up of the IGBT according to the present invention. In FIG. 3A of the comparative structure, the channel layer (p base region) 29 is formed with a depth of about 0.7 μm, and the emitter region 30 is formed with a depth of about 0.3 μm. It flows through a narrow region of 0.4 μm (the remaining thickness obtained by subtracting the thickness of the emitter region of 0.3 μm from the thickness of the p base region of 0.7 μm). When a large current is applied, current concentration occurs in this portion, and sufficient latch-up resistance cannot be obtained.

In the IGBT according to the present invention, as shown in FIG. 3B, in addition to the central first opening 25-1 similar to the comparative structure, a second opening 25-2 (hole path) is newly provided. Thus, the hole current injected from the anode side can be distributed to the first and second openings to prevent current concentration, and sufficient latch-up resistance can be obtained.
In FIG. 4, the distance (μm) between the P ⁺ region end and the second opening end (hereinafter referred to as a hole path interval or HP) is used as a parameter, and the hole path interval (HP) is +2.5 μm, +1.5 μm, For the IGBT in the case of +0.5 μm, 0 μm, and −0.5 μm, the horizontal axis represents the anode-cathode voltage Vak at a gate voltage of 15 V and 125 ° C., and the anode current (Ia) when the voltage (Vak) is applied Is shown on the vertical axis. The rated voltage is 1200 V and the rated current is 100 A / cm ² . For reference, the voltage (Vak) current waveform of a conventional planar IGBT is also shown.

In the case of an IGBT having a comparative structure without a hole path (HP) shown in FIG. 2, the anode current increases and latches up when the anode-cathode voltage is as low as about 10 V, as indicated by no HP in FIG. . Bare structure of ^{P +} region opened from a second opening where the entering 0.5μm below the ^{P +} region (HP-0.5) is a latch-up immunity of the conventional IGBT parallel. This, P ⁺ regions, that are Expose, hole current is to flow sufficiently toward the P ⁺ region. The structure in which the P ⁺ region end and the second opening end are flush with each other (HP0) and the structure in which the P ⁺ region end is pushed into the 0.5 μm from the second opening end (HP + 0.5) are compared with the conventional IGBT. However, it can be seen that the latch-up resistance is improved as compared with the structure without HP. However, if the P + region is further pushed in by 1.5 μm and 2.5 μm respectively (HP + 1.5, HP + 2.5), the latch-up resistance is equivalent to that without HP, and the effect of improving the latch-up resistance is lost. Therefore, in order to improve the latch-up resistance, the interval (HP) between the P + region end and the second opening end is preferably set to 1.0 μm or less.

FIG. 5 shows the relationship between the distance (d) between the P + region end and the second opening end (HP) and the ON voltage. As described above, when the second opening is provided, the holes are dispersed and the latch-up resistance is improved, but there is a problem that the holes flow and the bulk hole concentration is lowered and the on-voltage is increased. From FIG. 5, it can be seen that when the distance (distance) d is set to 0.5 μm or more, the increase in the ON voltage can be reduced. Therefore, from FIG. 4 and FIG. 5, the distance d is preferably 0.5 μm or more and 1.0 μm or less.

Next, the operation and effect of the IGBT created in the above-described embodiment will be described.
(Regarding steady ON state)
As shown in FIGS. 1 and 3, when a positive potential is applied to the gate electrode (gate polysilicon layer) 28 with respect to the cathode (emitter) electrode 33, the interface of the p-type base region 29 with the gate oxide film 27 is obtained. The nearby surface region is inverted to n-type and an n-channel is formed. When a forward bias is applied between the collector (not shown) and the emitter (between the anode and the cathode) in this state, electrons move along the gate oxide film 27 of the n-channel and electron storage layer (n ⁺ buffer region 26-1). ) Through the drift layer (n ^- silicon substrate) 21 and reaches the p ⁺ anode layer on the back surface (not shown). As a result, the pn junction between the p ⁺ anode layer and the drift layer 21 is forward-biased, so that holes (solid arrows in FIG. 3) are injected from the p ⁺ anode layer into the drift layer 21.

Injected holes, when come to the surface of the drift layer 21, first, ^{n +} buffer region is ^{n +} epitaxial silicon layer through the second opening 25-1 and 25-2 26-1, 26-2 Enter dispersed. Some of holes entering the n ⁺ buffer region 26-1, and disappear recombined with electrons in the ^{n +} buffer region 26-1. The remaining holes pass through the n ⁺ buffer region 26-1 and are collected in the p-type base region 29. Since the hole current flows through a narrow and long silicon layer that is a layer forming the n ⁺ buffer region 26-1 and the p-type base region 29, a voltage drop occurs. Therefore, the n ⁺ / n ⁻ junction composed of the n ⁺ region and the n ⁻ drift layer 21 along the gate oxide film 27 of the n ⁺ buffer region 26-1 serving as the electron storage layer is forward biased. As a result, electrons are injected to increase the electron concentration on the cathode side, and accordingly, holes of the same concentration are accumulated to satisfy the charge neutrality condition.

When holes are injected into the n ⁺ buffer region 26-1, the n ⁺ / n ⁻ junction is further forward-biased, and electrons are injected. The epitaxial silicon layer and the n ^- silicon substrate 21 are insulated from each other in regions other than the first and second openings by the substrate oxide film 24, so that it is difficult to achieve a pnp-BJT configuration. Yes. The region constituting the pnp-BJT is a small part of the entire device, and the majority is the pin diode region. Further, the n channel can be formed by using a large area of the substrate surface, and the channel peripheral length can be freely increased. However, if the peripheral length is too large, the transfer characteristic becomes too high, the current limit at the time of short-circuiting increases, and the short-circuit withstand capability decreases, so it is necessary to determine the peripheral length in consideration of this point.
(For forward blocking state)
Next, an operation in the blocking mode in which a forward bias is applied between the collector and the emitter with the gate potential equal or negative compared to the emitter potential will be described. A depletion layer spreads from the pn junction composed of the p-type base region 29 and the n ⁺ buffer region 26-1, and a depletion layer also spreads from the gate oxide film 27. This is because the n ⁺ buffer region 26-1 is positively biased while the gate electrode 28 is below the emitter potential. Since n ⁺ buffer region 26-1 is only the thickness of the epitaxial silicon layer, it is completely depleted with a slight forward bias. If the total impurity amount of the n ⁺ buffer region 26-1 is set to a certain value or less, the maximum electric field strength in the n ⁺ buffer region 26-1 can be suppressed.

As the forward bias is further increased, the depletion layer extends into the n ⁻ drift layer 21. Since most of the applied forward bias is carried by the n ⁻ drift layer 21, the local peak of the electric field strength in the n ⁺ buffer region 26-1 can be suppressed, and avalanche breakdown due to local electric field concentration is suppressed. Hard to happen. Therefore, a sufficient forward breakdown voltage can be ensured. As a result, the on-voltage does not deteriorate even when the forward breakdown voltage is increased. This is a great advantage compared to conventional planar type or trench type IGBTs. In the conventional planar type or trench type IGBT, it is difficult to avoid local electric field concentration.
(About trade-off characteristics)
In the n ⁺⁺ type emitter region 30 having a high impurity concentration in the n ⁺ epitaxial silicon layer 26, since the doping concentration is very high and the resistance is low, there is almost no voltage drop. In addition, since the peripheral length of the p-type channel region (p-type base region) 29 having a configuration obtained by p-type conversion of the n ⁺ epitaxial silicon layer 26 can be set relatively freely by pattern design, By making the peripheral length longer so as to compensate for the voltage drop, the voltage drop can be made the same as that of the conventional IGBT.

On the other hand, when the opening provided in the substrate insulating film is the first and second openings, the effect of the present invention that optimizes the trade-off between on-voltage and turn-off loss is exhibited. This means that the voltage drop in the n ⁻ drift layer, which occupies most of the on-voltage sharing, particularly in a high voltage IGBT, is minimized for a certain turn-off loss.
(Latch-up tolerance)
When the carrier lifetime and carrier mobility in the n ⁺ buffer region 26-1 are low, the diffusion length of holes that are minority carriers is shortened, and the recombination of carriers in the n ⁺ buffer region 26-1 is increased. As a result, the hole current that passes through the p-type base region 29 and is collected by the emitter electrode 33 is reduced. For this reason, the hole current contributing to the latch-up is reduced, and the latch-up resistance is improved.

Therefore, if the hole diffusion length in the ^{n +} buffer region 26-1 is much shorter than the length of the ^{n +} buffer region 26-1, since most of the holes disappear by recombination in the ^{n +} buffer region 26-1 The hole current reaching the p-type base region 29 becomes zero, and a latch-up free IGBT is realized. In this case, since the p-type base region 29 does not operate as a collector of the BJT, a conventional IGBT equivalent circuit model in which a MOSFET and a BJT are combined does not hold. When such an IGBT is represented by an equivalent circuit, a circuit combining a MOSFET and a pin diode is obtained.
(About micro processes)
The IGBT structure described above has an advantage in design that it is not necessary to make the surface pattern extremely fine. As shown in FIG. 1, the cathode (emitter) contact region is electrically separated from the drift layer 21 by the substrate oxide film 24, and a portion without the substrate oxide film 24, that is, the first and second portions of the substrate oxide film 24. The drift layer 21 is connected only at the two openings. Therefore, the design dimension of the cathode (emitter) contact region does not directly contribute to the characteristics of the drift layer 21. This is symmetric to the conventional planar type or trench type IGBT. In the conventional IGBT, all of the cathode (emitter) contact regions are directly connected to the drift layer, and the design dimensions are directly related to the characteristics. Therefore, as described above, the IGBT according to the present invention has the advantage that the trade-off characteristics are unchanged even if the n ⁺⁺ type source region 9 is not particularly miniaturized.

It is principal part sectional drawing of the MOS type semiconductor device concerning this invention. It is principal part sectional drawing of the MOS type semiconductor device for a comparison for demonstrating contrast with the MOS type semiconductor device concerning this invention. It is principal part sectional drawing of the MOS type semiconductor device for demonstrating the flow of the carrier of the MOS type semiconductor device concerning this invention. It is a voltage-current waveform diagram of a top gate type MOS semiconductor device. It is a relationship figure of the space | interval and ON voltage of the 2nd opening part end concerning this invention, and a p-type base area | region end. It is an equivalent circuit diagram of a conventional IGBT. It is sectional drawing which shows the structure of the principal part of the conventional planar type IGBT. It is principal part sectional drawing (the 1) of the semiconductor substrate shown to the manufacturing process order of IGBT concerning this invention. It is principal part sectional drawing (the 2) of the semiconductor substrate shown to the manufacturing process order of IGBT concerning this invention. It is principal part sectional drawing (the 3) of the semiconductor substrate shown to the manufacturing process order of IGBT concerning this invention.

Explanation of symbols

6 n ⁺⁺ emitter region 7 p base region 8 n channel 9 drift layer 10 n ⁺ accumulation layer 11 p anode layer 21 silicon substrate 22 oxide film 24 substrate oxide film (substrate insulating film)
25-1 1st opening 25-2 2nd opening 26-1 1st n ⁺ buffer area | region 26-2 2nd n ⁺ buffer area | region 27 Gate oxide film 28 Gate electrode 29 p base area | region 30 n ⁺⁺ emitter area | region 31 interlayer Insulating film 32 Emitter electrode contact opening 33 Emitter electrode 34 p ⁺ contact region (p ⁺ region).

Claims (6)

A substrate insulating film having a first opening and a second opening on one main surface of a one-conductivity-type semiconductor substrate, and a one-conductivity-type semiconductor crystal film deposited on the substrate insulating film and on both the openings With
The other conductivity type base region in which the one conductivity type semiconductor crystal film is selectively formed in the film, the one conductivity type emitter region formed on the surface in the other conductivity type base region, and the first opening A first buffer region including the one-conductivity-type semiconductor crystal film portion in contact with the semiconductor substrate, and the one-conductivity-type semiconductor crystal film located on the opposite side of the first buffer region with respect to the other-conductivity-type base region A second buffer region in contact with the semiconductor substrate at the second opening,
On the surface of the other conductivity type base region sandwiched between the first buffer region and the one conductivity type emitter region, a polycrystalline semiconductor gate electrode film and an interlayer insulation covering the polycrystalline semiconductor gate electrode film via a gate insulation film In a MOS type semiconductor device comprising a film and having an emitter electrode in contact with the surface of the one conductivity type emitter region and the surface of the other conductivity type base region,
A MOS type semiconductor device, wherein the width of the first opening is 5 μm or less. 2. The MOS type semiconductor device according to claim 1, wherein a distance between the other conductivity type base region and the first opening is 4 [mu] m or less. 3. The MOS semiconductor device according to claim 1, wherein the width of the second opening is 2 [mu] m or less. 4. The MOS semiconductor device according to claim 1, wherein an interval between the other conductivity type base region and the end of the second opening is in a range of 0.5 μm to 1 μm. 5. 5. The impurity concentration range of the first or second buffer layer is any one of 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁶ cm ^{−3. 5.} The MOS type semiconductor device described. 6. The MOS semiconductor device according to claim 1, wherein the thickness of the substrate insulating film is in a range of 0.05 to 1 [mu] m.

Images