JP2009152522A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress variance of a threshold voltage even when the thickness of a cathode film is varied. <P>SOLUTION: An oxide film 2 is selectively formed on an n<SP>-</SP>-single crystal silicon substrate 1. The cathode film 3 doped with density higher than that of a drift layer is formed through the window part of the oxide film 2. A gate oxide film 4 is formed on the cathode film 3, and a gate polysilicon 5 is formed on the gate oxide film 4. In the cathode film 3, a part in contact with the n<SP>-</SP>-single crystal silicon substrate 1 becomes an n<SP>+</SP>buffer region 7 having high density, and a p base region 6 is formed adjacently to this region. A second p base region 26 doped with high density is formed in the inside of the p base region 6, and a p<SP>+</SP>body region 8 and an n<SP>+</SP>source region 9 are selectively formed in the inside of the second p base region 26. Furthermore, an interlayer dielectric 10 is selectively formed on the gate polysilicon 5, and an emitter electrode 11 is formed on the interlayer dielectric. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a power semiconductor device constituting an IGBT (insulated gate bipolar transistor) and a manufacturing method thereof.

  With regard to IGBTs, performance has been improved by many improvements so far. Here, the performance of the IGBT is as a switch that keeps the voltage and shuts off the current completely when it is off, while flowing the current with the smallest possible voltage drop, that is, the smallest on-resistance when it is on. It's about performance. In the present specification, in view of the essence of the operation of the IGBT, the collector is denoted as “anode” and the emitter is denoted as “cathode”. Below, the characteristic etc. of IGBT are demonstrated.

(About IGBT performance trade-off)
There is a trade-off relationship (the so-called trade-off relationship) between the maximum voltage that can be held by the IGBT, that is, the withstand voltage level and the voltage drop at the time of ON, and the higher the withstand voltage IGBT, the higher the ON voltage. The limit value of this trade-off relationship is approaching the value determined by the physical properties of silicon. In order to improve this trade-off to the limit, it is necessary to devise on the design side, such as preventing local electric field concentration when holding the voltage.

  As another important index representing the performance of the IGBT, there is a trade-off relationship between on-voltage and switching loss (particularly, turn-off loss). Since the IGBT is a switching device, it operates from on to off or off to on. At the moment of this switching operation, a large loss per hour occurs. In general, an IGBT having a lower on-voltage has a slower turn-off loss, and therefore has a larger turn-off loss. By improving the trade-off relationship as described above, the performance of the IGBT can be improved. Note that the dependency of the turn-on loss on the on-voltage is small. The turn-on loss greatly depends on the characteristics of the freewheeling diode used in combination with the IGBT.

(About improving trade-offs)
In order to optimize the trade-off relationship between the on-voltage and the turn-off loss (hereinafter referred to as the on-voltage-turn-off loss relationship), it is effective to optimize the internal excess carrier distribution when the IGBT is on. . In order to lower the on-voltage, the resistance value of the drift layer may be decreased by increasing the excess carrier amount. However, at the time of turn-off, it is necessary to sweep all the excess carriers out of the device or to disappear by electron-hole recombination. Therefore, when the excess carrier amount is increased, the turn-off loss increases. Therefore, in order to optimize this trade-off relationship, the turn-off loss should be minimized with the same on-voltage.

  To achieve the optimal trade-off, the ratio of the carrier concentration on the anode side and the cathode side should be about 1: 5 by lowering the carrier concentration on the anode side and increasing the carrier concentration on the cathode side. Good. Furthermore, the average carrier concentration in the drift layer may be increased by keeping the carrier lifetime of the drift layer as large as possible.

  When the IGBT is turned off, the depletion layer extends from the pn junction on the cathode side into the drift layer and progresses toward the anode layer on the back surface. At that time, holes out of excess carriers in the drift layer are extracted from the end of the depletion layer by the electric field. In this way, an electron excess state occurs, and surplus electrons pass through the neutral region and are injected into the p-type anode layer. Then, since the anode side pn junction is slightly forward-biased, holes are reversely injected according to the injected electrons. The reversely injected holes merge with the holes extracted by the electric field described above and enter the depletion layer.

  Since carriers (here, holes) that are charge carriers pass through the electric field region and escape to the cathode side, the electric field works on the carriers. The work that the carriers receive from the electric field eventually becomes lattice vibration due to collision with a crystal lattice such as silicon, and is dissipated as heat. This dissipating energy becomes a turn-off loss. By the way, the energy dissipated by the carriers extracted before the depletion layer is fully extended is smaller than the energy dissipated by the carriers extracted when the depletion layer is fully extended. This is because if the depletion layer is not fully extended, the potential difference when carriers pass through the depletion layer is small, so that the work received from the electric field of the depletion layer is small.

  From a micro perspective, it looks like the above. From a macro viewpoint of the terminal voltage of the device, the product of the voltage and current (the current that flows before the anode-cathode voltage finishes rising, that is, the current that flows while the voltage rises) This means that the contribution to the loss expressed by (voltage × current) is small. From the above, the carrier distribution biased to the cathode side due to the IE effect described later turns off more than the carrier distribution of anode side bias under the condition that the proportion of carriers extracted at a low voltage is large and the on-voltage is the same. It can be seen that the loss is small.

  In order to lower the carrier concentration on the anode side, the total impurity amount in the anode layer may be lowered. This is not particularly difficult. However, in an IGBT having a low rated breakdown voltage such as 600 V, it is necessary to handle a wafer having a thickness of about 100 μm or thinner during the manufacturing process in order to reduce the total impurity amount of the anode layer. There are difficulties in production technology. On the other hand, the mechanism for increasing the carrier concentration on the cathode side is called the IE (Injection Enhanced) effect.

Here, a top-gate IGBT having a structure that facilitates electron injection from the surface, that is, a structure having a large IE effect has been proposed (see, for example, Patent Document 1 or Patent Document 2 below). FIG. 13 is a cross-sectional view showing a configuration of a conventional top gate type IGBT. Note that in this specification, a semiconductor having n or p means that electrons and holes are majority carriers, respectively. Further, “ ⁺ ” or “ ⁻ ” attached to n or p, such as n ⁺ or n ^−, is relatively higher or lower than the impurity concentration of the semiconductor to which they are not attached. Represents that.

In FIG. 13, oxide film 2 having, for example, a thick portion and a thin portion is selectively formed on the first main surface of n ⁻ single crystal silicon substrate 1 serving as a drift layer. The surface of the thin portion of the oxide film 2 and the portion of the n ⁻ single crystal silicon substrate 1 that is not covered with the oxide film 2 are n-type doped at a higher concentration than the n ⁻ single crystal silicon substrate 1. Covered by the cathode film 3. The cathode film 3 is made of n-type single crystal silicon that is epitaxially grown from a portion of the n ⁻ single crystal silicon substrate 1 that is not covered by the oxide film 2 and that is laterally grown on a thin portion of the oxide film 2. . In this way, polycrystalline silicon may be used instead of single crystal silicon formed by selective epitaxial growth.

In the cathode film 3, the portion of the cathode film 3 that contacts the n ⁻ single crystal silicon substrate 1 becomes an n ⁺ buffer region 7. A portion of the cathode film 3 adjacent to the n ⁺ buffer region 7 is provided with a p base region 6 that is selectively doped in p-type. A p ⁺ body region 8 and an n ⁺ source region 9 having an impurity concentration higher than that of the p base region 6 are selectively provided inside the p base region 6. Here, p ⁺ body region 8 is provided away from directly under gate polysilicon 5. Therefore, the region where the p-type impurity concentration is maximum in the region immediately below the gate polysilicon 5 (hereinafter referred to as the maximum p concentration region) is the p base region 6.

A gate oxide film 4 is selectively formed on the surface of the cathode film 3 so as to cover the n ⁺ buffer region 7 and a part of the p base region 6. On the gate oxide film 4, polysilicon (hereinafter referred to as gate polysilicon) 5 serving as a gate electrode is deposited. The periphery of the gate polysilicon 5 is covered with an interlayer insulating film 10. The gate polysilicon 5 is insulated from the emitter electrode 11 by the interlayer insulating film 10.

An aluminum layer to be the emitter electrode 11 is formed on the surfaces of the interlayer insulating film 10, the n ⁺ source region 9 and the p base region 6. That is, the emitter electrode 11 is in contact with a part of the n ⁺ source region 9. A p ⁺ anode layer 12 is formed on the second main surface of the n ⁻ single crystal silicon substrate 1. An aluminum layer to be the anode electrode 13 is formed on the surface of the p ⁺ anode layer 12.

Here, when the gate electrode (gate polysilicon 5) is set to a positive potential with respect to the cathode, electrons are induced in a region of the p base region 6 near the interface with the gate oxide film 4 to form a channel. Electrons enter the n ⁺ buffer region 7 through this channel. Since an extremely high concentration electron storage layer is formed on the surface of the n ⁺ buffer region 7, most of the electron current flows through the electron storage layer. Then, when electrons enter the drift layer (n ⁻ single crystal silicon substrate 1), they are injected into the p ⁺ anode layer 12 on the back surface due to electric field drift. The electrons injected into the p ⁺ anode layer 12 move to the anode electrode 13 by diffusion.

Since the junction between the n ⁻ drift layer and the p ⁺ anode layer 12 is forward-biased, holes are injected from the anode, move in the n ⁻ drift layer due to electric field drift, and enter the n ⁺ buffer region 7. Since most of the holes have a short diffusion length, they recombine with electrons in the n ⁺ buffer region 7 and the electron storage layer of the n ⁺ buffer region 7 and disappear. Since the junction composed of the electron storage layer and the n ⁻ drift layer is forward-biased, electron injection from the electron storage layer is promoted (IE effect). For this reason, the carrier concentration on the cathode side is increased, and the trade-off between on-voltage and switching loss is improved.

As described above, according to the conventional top gate type IGBT, the carrier distribution in the drift layer made of the n ⁻ single crystal silicon substrate becomes the surface deviated type, so the trade-off between the on-voltage and the turn-off loss is optimized. On the other hand, by suppressing the local peak of the electric field strength in the cathode region, local avalanche breakdown is less likely to occur, and a sufficient breakdown voltage can be ensured. For this reason, it is possible to prevent the on-voltage-withstand voltage trade-off from deteriorating. Further, in the conventional top gate type IGBT, the cathode region is separated from the drift layer (n ⁻ single crystal silicon substrate) by the oxide film, so the design size of the cathode region does not directly contribute to the characteristics of the drift region. . Therefore, the trade-off characteristics remain unchanged even if the source region is not made smaller than before.

JP 2006-237553 A JP 2007-43028 A

  However, in the technique of Patent Document 1 or 2 described above, the cathode film 3 is formed by selective epitaxial growth until it becomes slightly thicker than the thick part of the oxide film 2, and then CMP (Chemical) to the height of the thick part of the oxide film 2 is formed. The cathode film 3 is reduced in thickness by mechanical polishing to form a flat cathode film 3. Even when the cathode film 3 is formed of polycrystalline silicon, the cathode film 3 is formed until it becomes slightly thicker than the thick part of the oxide film 2, and then the cathode film 3 is reduced to the height of the thick part of the oxide film 2 by CMP polishing. It is necessary to make the cathode film 3 flat. This is because since the current path is determined by the thickness of the cathode film 3, it is essential to flatten the cathode film 3 in order to prevent variation in characteristics. However, the variation in the cathode film 3 after polishing occurs not only for each wafer but also more or less for each chip in the wafer. For this reason, when the maximum p concentration region is formed with a constant dose, when the thickness of the cathode film changes due to variations, the volume of the maximum p concentration region changes, and the p-type impurity concentration of the maximum p concentration region changes. . FIG. 14 is a characteristic diagram showing the relationship between the threshold voltage and the film thickness of the cathode film in a conventional top gate IGBT. In FIG. 14, the vertical axis represents the threshold voltage (V), and the horizontal axis represents the thickness (μm) of the cathode film.

  As can be seen from FIG. 14, the threshold voltage decreases as the cathode film becomes thicker, and the threshold voltage increases as the cathode film becomes thinner. This is because the diffusion coefficient of the oxide film is about 1/10000 of the diffusion coefficient of silicon, so that the p-type impurity hardly diffuses into the oxide film even if it diffuses through the silicon and reaches the oxide film. Therefore, if the cathode film is thin, the volume of the maximum p concentration region is small, so that the impurity concentration is high and the threshold voltage is high. On the other hand, when the cathode film is thick, the volume of the maximum p concentration region is large, so that the impurity concentration is lowered and the threshold voltage is lowered. As described above, the conventional top gate IGBT has a problem that the threshold voltage varies depending on the thickness of the cathode film.

  The present invention provides a semiconductor device and a method of manufacturing the same that can suppress fluctuations in threshold voltage even if the film thickness of the cathode film fluctuates in order to solve the above-described problems caused by the prior art. Objective.

  In order to solve the above-described problems and achieve the object, in the semiconductor device according to the first aspect of the invention, the first main surface of the first conductivity type semiconductor substrate is selectively covered with the first insulating film. . In the window portion of the first insulating film, the first first conductivity type semiconductor region having an impurity concentration higher than that of the semiconductor substrate is in contact with the semiconductor substrate. In addition, outside the window portion of the first insulating film, a first second conductivity type semiconductor region is provided on the first insulating film. A second second conductivity type semiconductor region having an impurity concentration higher than that of the first second conductivity type semiconductor region is provided on the inner surface side of the first second conductivity type semiconductor region. A second first conductivity type semiconductor region is selectively provided on the inner surface side of the second second conductivity type semiconductor region. Further, the second insulating film is formed on the first first conductivity type semiconductor region, the second first conductivity type semiconductor region, the first second conductivity type semiconductor region, and the second second conductivity type semiconductor region. Covering. A control electrode is provided on the second insulating film. In addition, a third second conductivity type semiconductor region having an impurity concentration higher than that of the second second conductivity type semiconductor region is provided in a region away from immediately below the control electrode inside the second second conductivity type semiconductor region. ing. The first electrode is in contact with both the second first conductivity type semiconductor region and the second second conductivity type semiconductor region. A third insulating film is provided between the first electrode and the control electrode. Further, a fourth second conductivity type semiconductor region is provided along the second main surface of the semiconductor substrate, and the second electrode is in contact with the fourth second conductivity type semiconductor region. To do.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the second second conductivity type semiconductor region is provided apart from the first insulating film. .

  According to a third aspect of the present invention, there is provided a semiconductor device according to the first or second aspect of the present invention, wherein the semiconductor device and the fourth second conductivity type semiconductor region have a higher impurity concentration than the semiconductor substrate. 3 of the first conductivity type semiconductor region is provided.

  A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein the impurity concentration on the surface of the first second conductivity type semiconductor region is the second second level. The impurity concentration of the surface of the conductive semiconductor region is 1/10 or less.

  In the semiconductor device manufacturing method according to the fifth aspect of the invention, first, a first insulating film having a thick portion and a thin portion is formed on the first main surface of the first conductivity type semiconductor substrate. Next, a part of the thin portion of the first insulating film is removed to form a window portion, and the first conductivity type semiconductor is formed on the thin portion of the first insulating film and the exposed portion of the semiconductor substrate in the window portion. Laminate the films. Then, the stacked first conductive type semiconductor film is polished to the height of the thick part of the first insulating film. Next, a polycrystalline semiconductor film to be a second insulating film and a control electrode is sequentially formed on the first conductive type semiconductor film. Further, a part of the polycrystalline semiconductor film is removed to leave the polycrystalline semiconductor film in a portion of the first conductive type semiconductor film above the first first conductive type semiconductor region in contact with the semiconductor substrate. A first second conductive type semiconductor region is formed in a thin portion of the first insulating film of the conductive type semiconductor film. Next, a second second conductive type semiconductor region having an impurity concentration higher than that of the first second conductive type semiconductor region is formed on the inner surface of the first second conductive type semiconductor region. The depth is not reached. Then, a third second conductivity type semiconductor region is formed inside the second second conductivity type semiconductor region, and further, a second first conductivity type is formed on the surface inside the second second conductivity type semiconductor region. Forming a type semiconductor region; Next, a first electrode in contact with a part of the second first conductivity type semiconductor region and the second second conductivity type semiconductor region is formed. A fourth second conductivity type semiconductor region is formed along the second main surface of the semiconductor substrate. Next, a second electrode in contact with the fourth second conductivity type semiconductor region is formed.

  According to a sixth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the fifth aspect of the present invention, wherein the first conductive semiconductor film has a thickness of 0.8 μm or less. The region is formed by a heat treatment temperature of 1000 ° C. and a diffusion time of 60 minutes or less.

According to a seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the fifth or sixth aspect, wherein the ion implantation amount of the second second conductivity type semiconductor region is 1.0 × 10 ¹⁶ / cm. It is formed by ² or less.

  According to an eighth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the fifth aspect of the present invention, wherein after the second main surface of the semiconductor substrate is ground, the fourth second conductivity along the ground surface. And a third first conductivity type semiconductor region having a higher impurity concentration than the semiconductor substrate, and the third first conductivity type semiconductor region is deeper than the fourth second conductivity type semiconductor region. It is characterized by forming.

  According to each invention described above, the second second conductivity type semiconductor region is provided apart from the first insulating film. Therefore, even if the thickness of the first first conductivity type semiconductor region varies, the volume of the second second conductivity type semiconductor region does not vary. For this reason, the impurity concentration of the second second conductivity type semiconductor region does not change, and the threshold voltage of the semiconductor device does not change.

  According to the semiconductor device and the method of manufacturing the same according to the present invention, even if the film thickness of the cathode film varies, it is possible to suppress the variation of the threshold voltage.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and all the attached drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment)
FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment. As shown in FIG. 1, an oxide film (first insulation) having, for example, a thick portion and a thin portion on a first main surface of an n ⁻ single crystal silicon substrate (first conductivity type semiconductor substrate) 1 to be a drift layer. Film) 2 is selectively formed. The portion of the n ⁻ single crystal silicon substrate 1 that is not covered with the oxide film 2 is covered with a cathode film 3 that is n-type doped at a higher concentration than the drift layer (n ⁻ single crystal silicon substrate 1). The cathode film 3 is made of, for example, n-type single crystal silicon that is epitaxially grown from a portion of the n ⁻ single crystal silicon substrate 1 that is not covered with the oxide film 2 (hereinafter referred to as a window portion). Note that polycrystalline silicon may be used instead of n-type single crystal silicon formed by epitaxial growth. A portion of the cathode film 3 in contact with the n ⁻ single crystal silicon substrate 1, that is, a portion near the window portion of the oxide film 2 becomes an n ⁺ buffer region (first first conductivity type semiconductor region) 7.

In the cathode film 3, a p base region (first second conductivity type semiconductor region) 6 adjacent to the n ⁺ buffer region 7 and selectively doped to a high concentration p type is formed in the window portion of the oxide film 2. It is provided on the outer thin part. Further, the second p base region (second second conductivity type semiconductor region) 26 having a higher concentration than the p base region 6 does not reach the thin portion of the oxide film 2 in the surface region inside the p base region 6. Is provided. A very high concentration n ⁺ source region (second first conductivity type semiconductor region) 9 is formed in the surface region inside the second p base region 26 apart from the n ⁺ buffer region 7. Further, the p ⁺ body region (the second p-type region) having a higher concentration than the second p base region 26 is located inside the second p base region 26, in contact with the n ⁺ source region 9 and away from directly below the gate polysilicon 5. 3 second conductivity type semiconductor region) 8 is selectively provided. The p ⁺ body region 8 may be exposed on the surface of the second p base region 26.

  A gate oxide film (second insulating film) 4 is formed on the surface of the cathode film 3, and polysilicon (hereinafter referred to as gate polysilicon) 5 serving as a gate electrode (control electrode) is formed on the gate oxide film 4. Is deposited. An interlayer insulating film (third insulating film) 10 is provided on the gate polysilicon 5, and the gate polysilicon 5 is insulated from the emitter electrode 11 by the interlayer insulating film 10.

On the interlayer insulating film 10, an aluminum layer serving as an emitter electrode (first electrode) 11 is formed. Emitter electrode 11 is in contact with second p base region 26 and n ⁺ source region 9 through a contact hole penetrating interlayer insulating film 10. When p ⁺ body region 8 is exposed on the surface of second p base region 26, emitter electrode 11 is formed on second p base region 26, n ⁺ source region 9 and p ⁺ body region 8. It may be in contact.

A p ⁺ anode layer (fourth second conductivity type semiconductor region) 12 is formed on the second main surface of the n ⁻ single crystal silicon substrate 1. On the surface of the p ⁺ anode layer 12, an aluminum layer serving as an anode electrode (second electrode) 13 is formed. Although not particularly shown, an n ⁺ buffer layer (third first conductivity type semiconductor having a higher impurity concentration than the drift layer (n ⁻ single crystal silicon substrate 1)) is provided between the drift layer and the p ⁺ anode layer 12. Area) may be provided.

Next, a method for manufacturing the semiconductor device according to the present embodiment will be described. 2-5 is sectional drawing shown in order about the manufacturing method of the semiconductor device concerning this Embodiment. Although not particularly limited, in the present embodiment, for example, a case of manufacturing a non-punch through type IGBT having a rated withstand voltage of 600 V will be described. First, as shown in FIG. 2, an n-type FZ silicon substrate is prepared as the n ⁻ single crystal silicon substrate 1. Then, thermal oxidation is performed to grow an oxide film 2 on the mirror polished surface of the substrate. Further, patterning and etching are performed to remove a portion of the surface portion of the oxide film 2 to provide a thin portion, and further remove a portion of the thin portion to form a window portion. Note that the window may be formed by forming a thick oxide film on a part of the thin oxide film and then removing a part of the thin oxide film.

Then, n-type single crystal silicon is epitaxially grown from a portion of the n ⁻ single crystal silicon substrate 1 exposed at the window portion of the oxide film 2 to form the cathode film 3. Further, the cathode film 3 is smoothed by CMP polishing to the height of the thick part of the oxide film 2 so as to have a predetermined thickness. The cathode film 3 later becomes a source region, a channel region, and a buffer region. Further, thermal oxidation is performed to oxidize the surface of the cathode film 3 to form a gate oxide film 4.

  Then, gate polysilicon 5 to be a gate electrode is deposited on the gate oxide film 4. Then, heat treatment is performed, and the gate polysilicon 5 is doped to a high concentration n-type. Further, patterning and etching are performed to remove a part of the gate polysilicon 5. Boron ions are implanted into the cathode film 3 using the remaining gate polysilicon 5 as a mask. Then, for example, driving is performed at 1150 ° C. for 110 minutes in a nitrogen atmosphere to form the p base region 6 serving as a channel region (FIG. 2).

  Next, boron is ion-implanted into the p base region 6. Then, for example, driving is performed in a nitrogen atmosphere, and the second p base region 26 that is higher in concentration than the p base region 6 and serves as the second channel region is formed so as not to reach the oxide film 2 (FIG. 3). . The conditions for forming the second p base region 26 will be described later.

Next, a p ⁺ body region 8 having a higher concentration than that of the p base region 6 and the second p base region 26 is formed in a region inside the second p base region 26 and away from just below the gate polysilicon 5. (FIG. 4). Next, for example, arsenic ions are implanted into the second p base region 26. Then, driving is performed to form an n ⁺ source region 9 (FIG. 5).

Next, BPSG is deposited as the interlayer insulating film 10, and patterning and etching are performed to form a contact hole penetrating the interlayer insulating film 10. Next, a metal such as aluminum is sputtered on the interlayer insulating film 10. Then, patterning and etching of a metal such as aluminum is performed to form the emitter electrode 11. Next, the back surface of the n ⁻ single crystal silicon substrate 1 is ground. Thereafter, boron is ion-implanted into the ground surface to form the p ⁺ anode layer 12.

Next, a metal such as aluminum is deposited on the surface of the p ⁺ anode layer 12 to form the anode electrode 13 (FIG. 1). It should be noted that n-type impurities such as phosphorus may be ion-implanted into the ground surface of the back surface of the n ⁻ single crystal silicon substrate 1 before annealing. That way, by annealing, with p ⁺ anode layer 12, n ^- n ⁺ buffer layer is formed between the drift layer and the p ⁺ anode layer 12. Finally, the wafer is diced to complete the chip.

  According to the present embodiment, the maximum p concentration region immediately below the gate polysilicon 5 is the second p base region 26. Since the second p base region 26 is not in contact with the oxide film 2 formed on the surface of the drift layer, the volume of the second p base region 26 does not change even if the film thickness of the cathode film 3 changes. .

(Relationship between threshold voltage and cathode film thickness)
Next, the relationship between the threshold voltage and the thickness of the cathode film in the semiconductor device according to the embodiment will be described. FIG. 6 is a characteristic diagram showing the relationship between the threshold voltage and the thickness of the cathode film in the semiconductor device according to the present embodiment. In FIG. 6, the vertical axis represents the threshold voltage (V), and the horizontal axis represents the thickness (μm) of the cathode film. The solid line shows the characteristics of the present invention, and the dotted line shows the characteristics of the prior art as a contrast.

  As shown in FIG. 6, in the prior art, the threshold voltage fluctuates due to fluctuations in the thickness of the cathode film. However, according to the semiconductor device of this embodiment, the thickness of the cathode film varies. In addition, fluctuations in the threshold voltage can be suppressed.

(Suitable formation conditions for the second base region)
Next, suitable formation conditions for the second base region will be described. First, a preferable diffusion time of the second base region will be described. FIG. 7 is a characteristic diagram showing the relationship between the diffusion depth and the diffusion time of the second base region. In FIG. 7, the vertical axis represents the diffusion depth (μm), and the horizontal axis represents the diffusion time (min). FIG. 7 illustrates a case where boron having a dose of 1.0 × 10 ¹⁵ / cm ² is ion-implanted at a heat treatment temperature of 1000 ° C. The heat treatment temperature is preferably 980 ° C to 1020 ° C. As shown in FIG. 7, when the diffusion time exceeds 60 min, the diffusion depth becomes deeper than 0.8 μm.

  FIG. 8 is a characteristic diagram showing the relationship between the diffusion time of the second base region and the threshold voltage. In FIG. 8, the vertical axis represents the threshold voltage (V), and the horizontal axis represents the diffusion time (min). In FIG. 8, a case where the thickness of the cathode film is 0.8 μm will be described. Therefore, when the diffusion time exceeds 60 min, the diffusion depth becomes deeper than 0.8 μm, and the second base region reaches the oxide film formed on the surface of the drift layer. Impurity concentration increases. Therefore, as shown in FIG. 8, when the diffusion time exceeds 60 min, the threshold voltage increases. Accordingly, it can be seen that when the thickness of the cathode film is 0.8 μm, it is preferable to set the diffusion time to 60 min or less in order to suppress variations in threshold voltage.

Next, a suitable dose amount of the second base region will be described. FIG. 9 is a characteristic diagram showing the relationship between the dose amount of the second base region and the threshold voltage. In FIG. 9, the vertical axis represents the threshold voltage (V), and the horizontal axis represents the dose (/ cm ² ). In FIG. 9, a case where activation heat treatment is performed at a heat treatment temperature of 1000 ° C. and a diffusion time of 60 minutes will be described. As shown in FIG. 9, when the dose exceeds 1.0 × 10 ¹⁶ / cm ² , the threshold voltage increases rapidly. Accordingly, it can be seen that the ion implantation dose in the second base region is preferably 1.0 × 10 ¹⁶ / cm ² or less.

(Regarding the relationship between the base region and the second base region)
Next, the relationship between the base region and the second base region will be described. 10 to 12 are characteristic diagrams showing the relationship between the impurity concentration of the surface of the base region and the threshold voltage with respect to the impurity concentration of the surface of the second base region. 10 to 12, the vertical axis represents the threshold voltage (V), and the horizontal axis represents the impurity concentration (/ cm ³ ).

FIG. 10 shows the relationship between the impurity concentration on the surface of the base region and the threshold voltage when the impurity concentration on the surface of the second base region is 1.0 × 10 ¹⁷ / cm ³ . As shown in FIG. 10, when the impurity concentration on the surface of the base region exceeds 1.0 × 10 ¹⁶ / cm ³ , the threshold voltage rapidly increases.

FIG. 11 shows the relationship between the impurity concentration on the surface of the base region and the threshold voltage when the impurity concentration on the surface of the second base region is 5.0 × 10 ¹⁶ / cm ^3. . As shown in FIG. 11, when the impurity concentration on the surface of the base region exceeds 5.0 × 10 ¹⁵ / cm ³ , the threshold voltage rapidly increases.

Further, FIG. 12 shows the relationship between the impurity concentration on the surface of the base region and the threshold voltage when the impurity concentration on the surface of the second base region is 3.0 × 10 ¹⁶ / cm ^3. . As shown in FIG. 12, when the impurity concentration on the surface of the base region exceeds 3.0 × 10 ¹⁵ / cm ³ , the threshold voltage rapidly increases.

  As described above, when the impurity concentration on the surface of the base region is higher than 1/10 of the impurity concentration on the surface of the second base region, the threshold voltage increases. Thus, in order to prevent the impurity concentration on the surface of the base region from affecting the threshold voltage, the impurity concentration on the surface of the base region is set to 10 minutes of the impurity concentration on the surface of the second base region. It can be seen that it is preferably 1 or less.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for a power semiconductor device used for a power conversion device and the like, and are particularly suitable for an IGBT.

It is sectional drawing shown about the structure of the semiconductor device concerning this Embodiment. It is sectional drawing shown about the manufacturing method of the semiconductor device concerning this Embodiment. It is sectional drawing shown about the manufacturing method of the semiconductor device concerning this Embodiment. It is sectional drawing shown about the manufacturing method of the semiconductor device concerning this Embodiment. It is sectional drawing shown about the manufacturing method of the semiconductor device concerning this Embodiment. It is a characteristic view shown about the relation between threshold voltage and the film thickness of a cathode film in the semiconductor device concerning this embodiment. It is a characteristic view shown about the relation between the diffusion depth of the 2nd base field, and diffusion time. It is a characteristic view shown about the relation between the diffusion time of the 2nd base field, and threshold voltage. FIG. 10 is a characteristic diagram showing a relationship between a dose amount of a second base region and a threshold voltage. It is a characteristic view showing the relationship between the impurity concentration of the surface of the base region and the threshold voltage when the impurity concentration of the surface of the second base region is 1.0 × 10 ¹⁷ / cm ³ . FIG. 10 is a characteristic diagram showing the relationship between the impurity concentration on the surface of the base region and the threshold voltage when the impurity concentration on the surface of the second base region is 5.0 × 10 ¹⁶ / cm ³ . FIG. 10 is a characteristic diagram showing the relationship between the impurity concentration on the surface of the base region and the threshold voltage when the impurity concentration on the surface of the second base region is 3.0 × 10 ¹⁶ / cm ³ . It is sectional drawing which shows the structure of the conventional top gate type IGBT. It is a characteristic view shown about the relationship between the threshold voltage in the conventional top gate type IGBT, and the film thickness of a cathode film.

Explanation of symbols

1 n ^- single crystal silicon substrate (first conductive semiconductor substrate)
2 Oxide film (first insulating film)
3 Cathode film 4 Gate oxide film (second insulating film)
5 gate polysilicon 6 p base region (first second conductivity type semiconductor region)
7 n ⁺ buffer region (first first conductivity type semiconductor region)
8 p ⁺ body region (third second conductivity type semiconductor region)
9 n ⁺ source region (second first conductivity type semiconductor region)
10 Interlayer insulation film (third insulation film)
11 Emitter electrode (first electrode)
12 p ⁺ anode layer (fourth second conductivity type semiconductor region)
13 Anode electrode (second electrode)
26 second p base region (second second conductivity type semiconductor region)

Claims (8)

A first insulating film that selectively covers the first main surface of the first conductivity type semiconductor substrate;
A first conductive semiconductor region having a higher impurity concentration than the semiconductor substrate in contact with the semiconductor substrate in the window of the first insulating film;
A first second conductivity type semiconductor region provided on the first insulating film outside the window portion of the first insulating film;
A second second conductivity type semiconductor region having an impurity concentration higher than that of the first second conductivity type semiconductor region, provided on the inner surface side of the first second conductivity type semiconductor region;
A second first conductivity type semiconductor region selectively provided on the inner surface side of the second second conductivity type semiconductor region; the first first conductivity type semiconductor region; and the second first conductivity type. A second insulating film covering the type semiconductor region, the first second conductivity type semiconductor region, and the second second conductivity type semiconductor region;
A control electrode provided on the second insulating film;
A third second conductivity type semiconductor having an impurity concentration higher than that of the second second conductivity type semiconductor region provided in a region inside the second second conductivity type semiconductor region away from just below the control electrode. Area,
A first electrode in contact with both the second first conductivity type semiconductor region and the second second conductivity type semiconductor region;
A third insulating film provided between the first electrode and the control electrode;
A fourth second conductivity type semiconductor region provided along the second main surface of the semiconductor substrate;
A second electrode in contact with the fourth second conductivity type semiconductor region;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the second second-conductivity-type semiconductor region is provided apart from the first insulating film.   2. The third first-conductivity-type semiconductor region having a higher impurity concentration than the semiconductor substrate is provided between the semiconductor substrate and the fourth second-conductivity-type semiconductor region. Or the semiconductor device according to 2;   The impurity concentration on the surface of the first second conductivity type semiconductor region is 1/10 or less of the impurity concentration on the surface of the second second conductivity type semiconductor region. The semiconductor device according to any one of the above. A first step of forming a first insulating film having a thick portion and a thin portion on a first main surface of a first conductivity type semiconductor substrate;
A second step of forming a window portion by removing a part of the thin portion of the first insulating film;
A third step of laminating a first conductive type semiconductor film on a thin portion of the first insulating film and a portion of the semiconductor substrate exposed at the window;
A fourth step of polishing the first conductive semiconductor film to a height of a thick portion of the first insulating film;
A fifth step of sequentially forming a second insulating film and a polycrystalline semiconductor film serving as a control electrode on the first conductive semiconductor film;
Removing a portion of the polycrystalline semiconductor film, leaving the polycrystalline semiconductor film in a portion of the first conductive semiconductor film above the first first conductive semiconductor region in contact with the semiconductor substrate; A sixth step of forming a first second conductivity type semiconductor region on a thin portion of the first insulation film of the first conductivity type semiconductor film;
A thin portion of the first insulating film is formed on the inner surface of the first second conductivity type semiconductor region with a second second conductivity type semiconductor region having an impurity concentration higher than that of the first second conductivity type semiconductor region. A seventh step of forming at a depth not reaching
A third second conductivity type semiconductor region is formed inside the second second conductivity type semiconductor region, and further, a second first conductivity type is formed on the surface inside the second second conductivity type semiconductor region. An eighth step of forming the type semiconductor region;
A ninth step of forming a first electrode in contact with the second first conductive semiconductor region and a part of the second second conductive semiconductor region;
A tenth step of forming a fourth second conductivity type semiconductor region along a second main surface of the semiconductor substrate;
An eleventh step of forming a second electrode in contact with the fourth second conductivity type semiconductor region;
A method for manufacturing a semiconductor device, comprising:   In the seventh step, when the thickness of the first conductive type semiconductor film is 0.8 μm or less, the heat treatment temperature of the second second conductive type semiconductor region is 1000 ° C. and the diffusion time is within 60 min. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is formed by processing. 7. The semiconductor device according to claim 5, wherein, in the seventh step, the second second-conductivity-type semiconductor region has an ion implantation amount of 1.0 × 10 ¹⁶ / cm ² or less. Manufacturing method.   In the tenth step, after the second main surface of the semiconductor substrate is ground, the fourth second conductivity type semiconductor region along the ground surface and a third impurity having a higher impurity concentration than the semiconductor substrate. 6. The semiconductor according to claim 5, wherein the first conductivity type semiconductor region is formed, and the third first conductivity type semiconductor region is formed deeper than the fourth second conductivity type semiconductor region. Device manufacturing method.

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