CN112951905B - SiC reverse-conduction type insulated gate bipolar transistor device and manufacturing method thereof - Google Patents
SiC reverse-conduction type insulated gate bipolar transistor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN112951905B CN112951905B CN202110096995.6A CN202110096995A CN112951905B CN 112951905 B CN112951905 B CN 112951905B CN 202110096995 A CN202110096995 A CN 202110096995A CN 112951905 B CN112951905 B CN 112951905B
- Authority
- CN
- China
- Prior art keywords
- conductive type
- forming
- collector
- conductivity type
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 238000011049 filling Methods 0.000 claims abstract description 7
- 238000001704 evaporation Methods 0.000 claims description 12
- 238000004544 sputter deposition Methods 0.000 claims description 12
- 230000008020 evaporation Effects 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 230000000903 blocking effect Effects 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000005224 laser annealing Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 238000009740 moulding (composite fabrication) Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 26
- 229910010271 silicon carbide Inorganic materials 0.000 description 25
- 239000000463 material Substances 0.000 description 8
- 229910052709 silver Inorganic materials 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a SiC reverse-conduction insulated gate bipolar transistor device and a manufacturing method thereof, wherein the transistor device comprises a metal collector, and a first conduction type substrate, a first conduction type buffer layer, a second conduction type collector and a first conduction type drift region are sequentially arranged from the metal collector; a plurality of grooves are formed in the first conductive type substrate and the first conductive type buffer layer, penetrate through the first conductive type substrate and the first conductive type buffer layer, and a filling collector in the grooves penetrates through the first conductive type substrate and the first conductive type buffer and then is connected with a second conductive type collector; the second-conductivity-type collectors are of mutually separated array structures, and each second-conductivity-type collector corresponds to the groove. According to the transistor device, the freewheeling diode is integrated into the SiC IGBT, so that parasitic parameters of a circuit are reduced, and the utilization rate of the chip area is improved.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a SiC reverse-conduction insulated gate bipolar transistor device and a manufacturing method thereof.
Background
Silicon carbide (SiC) is used as a third-generation wide forbidden band material, has the advantages of large forbidden band width, high critical breakdown electric field, high thermal conductivity, high carrier saturation speed and the like, and is favored in the field of power devices.
The silicon carbide insulated gate bipolar transistor (SiC IGBT) not only has the characteristics of high voltage resistance, high working junction temperature, strong irradiation resistance, high working frequency and the like of a SiC material, but also has the advantages of easiness in driving, simplicity in control, low on-voltage, high on-state current and small loss of the IGBT, is one of ideal switching devices applied to high-voltage (more than or equal to 10 kV) high-power fields such as solid-state transformers, high-voltage pulse power supplies, high-voltage inverters, flexible alternating current/direct current power transmission systems, high-voltage direct current power transmission systems, static var compensators and the like, and has wide development prospect.
Generally, the use of IGBTs requires antiparallel connection of a freewheeling diode, and IGBTs with integrated antiparallel diodes are known in the industry as RC-IGBTs on silicon devices. However, the SiC substrate is thicker to 350 μm, the impurity diffusion coefficient is low, a separated collector region is difficult to realize, and the implementation mode of the RC-IGBT becomes a problem that a practitioner needs to think.
In the prior art, an N-channel IGBT is usually formed by adopting a P-type SiC substrate, even if the thickness of the substrate is up to-150 mu m after the substrate is thinned, the substrate is difficult to realize due to the fact that the substrate is thick, and a large amount of impurities are injected with high energy to possibly cause unrecoverable damage to SiC crystal lattices, so that the preparation of the reverse-conduction type SiC IGBT is expected to be difficult to realize due to the fact that a large amount of N-type impurities are injected into the substrate to be reversely doped. Therefore, when the SiC IGBT is used, a freewheeling diode with the same voltage level is required to be connected in anti-parallel, so that high additional cost is brought, and parasitic parameters of a circuit are increased.
Disclosure of Invention
The invention aims to solve the technical problems that: the SiC reverse-conduction type insulated gate bipolar transistor structure and the manufacturing method thereof are provided, and the chip area utilization rate is improved while circuit parasitic parameters are reduced.
The invention adopts the technical scheme that:
a SiC reverse-conduction type insulated gate bipolar transistor device comprises a metal collector arranged on the back surface, wherein a first conduction type substrate, a first conduction type buffer layer, a second conduction type collector and a first conduction type drift region are sequentially arranged from the metal collector;
a plurality of grooves are formed in the first conductive type substrate and the first conductive type buffer layer, penetrate through the first conductive type substrate and the first conductive type buffer layer, and a filling collector in the grooves penetrates through the first conductive type substrate and the first conductive type buffer and then is connected with a second conductive type collector;
the second-conductivity-type collectors are of mutually separated array structures, and each second-conductivity-type collector corresponds to the groove.
A manufacturing method of a SiC reverse conduction type insulated gate bipolar transistor device comprises the following steps:
1) Selecting a first conductive type substrate;
2) Growing an epitaxial layer on the first conductivity type substrate to form a first conductivity type buffer region and a part of the first conductivity type-drift region, and forming a separated second conductivity type collector region by selectively implanting second conductivity type impurities;
3) Continuing to grow a first conductivity type-drift region on the formed second conductivity type collector region;
4) Forming a second conductive type well region by selective ion implantation through the blocking of the pattern mask;
5) Forming a side wall on the side wall of the graph mask in a self-alignment mode;
6) Forming a first conductive type emission region by ion implantation;
7) Blocking the selective ion implantation through the pattern mask to form a heavily doped second conductive type region;
8) Removing the surface mask, coating a carbon film for protection, and then carrying out high-temperature annealing;
9) Removing the carbon film and sacrificing the oxidation treatment surface, and forming a gate insulating layer by a thermal oxygen growth or deposition mode;
10 Depositing doped polysilicon, and forming a gate electrode through photoetching;
11 Silicon dioxide or/and silicon nitride is deposited, and an insulating medium layer is formed through photoetching;
12 Forming an ohmic contact metal layer by evaporation or sputtering;
13 Forming a trench penetrating the first conductive type substrate and the first conductive type buffer layer on the back surface;
14 Filling conductive material into the trench to form a filled collector, and leading out a collector of the second conductivity type;
15 A metal emitter on the front surface is formed by evaporation or sputtering;
16 Forming an ohmic contact metal layer on the back surface by means of evaporation or sputtering, and forming ohmic contact with the first conductive type substrate through laser annealing;
17 A back metal emitter is formed by evaporation or sputtering.
The invention has the beneficial effects that:
according to the SiC reverse-conduction type insulated gate bipolar transistor device, the collector metal is connected with the collector of the second conductivity type through the back deep groove structure, the anti-parallel integration of the SiC diode and the SiC IGBT is realized, the reverse-conduction type SiC IGBT device is formed, the chip area utilization rate is effectively improved, and the application cost of the device is greatly reduced.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment 1 of a SiC reverse conducting insulated gate bipolar transistor device of the present invention;
fig. 2 is a schematic structural diagram of an embodiment 2 of a SiC reverse conducting insulated gate bipolar transistor device according to the present invention;
fig. 3 is a top view of a first trench structure on the back side of a transistor device according to the present invention:
FIG. 4 is a top view of a second trench structure on the back side of the transistor device of the present invention;
fig. 5 is a top view of a back side trench structure three of a transistor device of the present invention;
fig. 6 is a top view of a backside trench structure four of a transistor device of the present invention.
The reference numerals in the drawings are: 1-first conductivity type substrate, 2-first conductivity type buffer layer, 3-second conductivity type collector, 4-first conductivity type drift region, 5-second conductivity type well region, 6-first conductivity type emitter region, 7-heavily doped second conductivity type region, 8-gate insulation layer, 9-gate electrode, 10-insulating dielectric layer, 11-metal emitter, 12-filled collector, 13-metal collector.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical solution of the present invention and are not intended to limit the scope of the present invention.
Example 1
As shown in fig. 1, the SiC reverse-conduction type insulated gate bipolar transistor device of the present invention includes a metal collector 13 disposed on the back surface, and a first conductivity type substrate 1, a first conductivity type buffer layer 2, a second conductivity type collector 3, and a first conductivity type drift region 4 are disposed in this order from the metal collector 13;
a plurality of grooves are formed in the first conductive type substrate and the first conductive type buffer layer, the grooves penetrate through the first conductive type substrate and the first conductive type buffer layer, and a filling collector 12 in the grooves penetrates through the first conductive type substrate 1 and the first conductive type buffer2 and then is connected with a second conductive type collector 3;
a second conduction type well region, a first conduction type emission region and a heavily doped second conduction type region are arranged at the position, close to the front surface, of the first conduction type drift region;
the gate electrode 9 is isolated from the SiC material by a gate insulating layer 8 and isolated from a metal emitter 11 located on the front surface by an insulating dielectric layer 10; the SiC material comprises a well region, an emission region and a drift region;
the metal emitter 11 forms an ohmic contact connection with the first conductivity type emitter region 6, the heavily doped second conductivity type region 7 at the same time.
The front surface structure of the first conductive type drift region is a planar gate structure.
As shown in fig. 3 to 6, the number of the grooves in the first conductivity type substrate 1 and the first conductivity type buffer2 is one or more.
The shapes of the grooves in the first conductivity type substrate 1 and the first conductivity type buffer2 are bar, square, polygonal, circular, etc., and may be a combination of various shapes.
The dimensions of the trenches in the first conductivity type substrate 1 and the first conductivity type buffer2 are variable, such as being composed of two or more different sized trenches.
The materials filled in the grooves in the first conductive type substrate 1 and the first conductive type buffer2 are one or more of Cu, silver paste, alloy powder, polysilicon and the like.
All the top views described above cover only a portion of the top views of the backside trench of the present invention, and the top views of the backside trench that meet the requirements of the claims of the present invention are all within the scope of the present invention.
The plurality of gate electrodes 9 are connected by a planar polysilicon arrangement.
The first conductivity type mentioned in the present invention is P-type if it is N-type; and vice versa.
The invention discloses a manufacturing method of a SiC reverse conduction type insulated gate bipolar transistor device, which comprises the following steps:
1) Selecting an N-type substrate; the thickness of the N-type substrate ranges from 150 mu m to 350 mu m, and the resistivity ranges from 0.01Ω & cm to 0.02Ω & cm;
2) Growing an epitaxial layer on an N-type substrate to form an N-type buffer region and a part of N-drift region, and forming a separated P-type collector region by selectively injecting P-type impurities; wherein the concentration range of the N-type buffer zone is 1E18cm -3 -2e18cm -3 The thickness range is 0.3 μm-3 μm; the concentration range of the P-type collector region is 1E18cm -3 -1E19 cm -3 The thickness range is 1-10 mu m; the concentration and thickness of the N-drift region are determined according to the voltage level of the target device, and the concentration range is 8E14 cm -3 -1E16 cm -3 The thickness is in the range of 10 μm to 100 μm; optionally, the P-type collector region may be formed by epitaxy of the P-type region and then selective ion implantation of an N-type impurity inversion to form a separate P-type collector region;
3) Continuing to grow an N-drift region on the formed P-type collector region;
4) Blocking by a pattern mask, and selectively implanting ions to form a P-type well region; the concentration range of the well region is 1E18cm -3 -1E19 cm -3 The depth range is 1 μm-10 μm;
5) Forming a side wall on the side wall of the pattern mask in a self-alignment mode, and forming a spacer side wall by using silicon dioxide or silicon nitride, wherein the effective width of the side wall is generally 0.4-2 mu m;
6) Forming an N-type emission region by ion implantation; the concentration range of the emission region is 5E19 cm -3 -1E21 cm -3 The depth range is 0.3 μm-3 μm;
7) Blocking the selective ion implantation through a pattern mask to form a heavily doped P-type region; the concentration range of the heavily doped P-type region is 1E19 cm -3 -1E20 cm -3 The depth is close to that of the P-type well region, and the depth range is 1-10 mu m;
8) Removing the surface mask, coating a carbon film for protection, and then carrying out high-temperature annealing; the high-temperature annealing temperature ranges from 1600 ℃ to 1800 ℃ and the annealing time ranges from 15min to 60min;
9) Removing the carbon film and sacrificing the oxidation treatment surface, and forming a gate insulating layer by a thermal oxygen growth or deposition mode; the thickness of the oxide layer is 50-200 nm, and the channel mobility is improved through oxynitride annealing;
10 Depositing doped polysilicon, and forming a gate electrode by photoetching, wherein the thickness range of the gate electrode is 1-4 mu m, and the sheet resistance range is 6Ω/≡30Ω/≡ζ ≡ ∈square;
11 Silicon dioxide or/and silicon nitride is deposited, and an insulating medium layer is formed through photoetching; the total thickness of the insulating medium layer is 1-4 mu m;
12 An ohmic contact metal layer is formed by evaporation or sputtering, typical materials such as Ti, ni and the like, the thickness range is 800 angstrom-1000 angstrom (1 angstrom is 0.1 nm), and the ohmic contact layer of a metal emission set and a SiC material is formed by a high-temperature process at 800-1000 ℃;
the method further comprises the following steps:
13 Grinding the back of the workpiece formed in the step 11) through a grinding wheel to thin the N-type substrate or stripping the N-type substrate by utilizing laser; selecting grinding wheels with 2000 meshes and 8000 meshes as coarse thinning and fine thinning; the thinning time is related to the thinning thickness, the thickness range after thinning is 20-150 mu m, and partial stress of the chip is released by using a CMP polishing mode;
14 Forming a groove penetrating the N-type substrate and the N-type buffer layer on the back surface; implementations include laser drilling and chemical etching, or a combination of both implementations; grooving the SiC N-type substrate layer in the selected area by utilizing laser with the wavelength range of 300-600 nm, or forming a mask opening on the back surface by photoetching a mask, and grooving by utilizing chemical reaction, wherein the reaction gas is chlorine-based gas and fluorine-based gas and is Cl 2 、CCl 4 、SF 6 、CF 4 、CH 3 F, etc.;
15 Filling conductive material in the trench to form a filled collector, and leading out the P-type collector; the conductive material is Cu, silver paste, alloy powder or polysilicon, and the like, and is annealed to form good filling and good contact between a metal collector and a P-shaped collector, wherein the annealing temperature is 300-1000 ℃ and the annealing time is 15-120 min;
16 A metal emitter on the front surface is formed by evaporation or sputtering; al and/or Au and/or Ag are/is formed, a small amount of other metals can be doped in Al, and the thickness range is 2-6 mu m;
17 Forming ohmic contact metal layer on the back surface by evaporating or sputtering, forming back ohmic contact by laser annealing, wherein the thickness of the material is 800-1000 angstrom, such as Ti, ni, etc.;
18 The back metal emitter is formed by evaporation or sputtering, the metal layer is Ti/Ni/Ag or Ti/Ni/Au, the thickness of Ti is generally 0.1 μm-0.4 μm, the thickness of Ni is generally 0.2 μm-0.6 μm, the thickness of Ag is generally 1 μm-2 μm, and the thickness of Au is generally 0.01 μm-0.1 μm.
Example 2
As shown in fig. 2, the front structure of the first conductivity type drift region is a trench gate structure and a trench gate structure with a dummy trench gate. The lateral conduction channel in embodiment 1 is optimized to be longitudinal through the front-side groove design, which is favorable for the fine design of the device and reduces the conduction voltage drop and the GC capacitance of the device.
Other technical features are the same as those of embodiment 1.
While the embodiments of the present invention have been described in detail and with reference to the drawings, the foregoing description is only a preferred embodiment of the present invention, and it should be noted that modifications and variations can be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (2)
1. A method of fabricating a SiC reverse conducting insulated gate bipolar transistor device, comprising the steps of:
1) Selecting a first conductive type substrate;
2) Growing an epitaxial layer on the first conductivity type substrate to form a first conductivity type buffer region and a part of the first conductivity type-drift region, and forming a separated second conductivity type collector region by selectively implanting second conductivity type impurities;
3) Continuing to grow a first conductivity type-drift region on the formed second conductivity type collector region;
4) Forming a second conductive type well region by selective ion implantation through the blocking of the pattern mask;
5) Forming a side wall on the side wall of the graph mask in a self-alignment mode;
6) Forming a first conductive type emission region by ion implantation;
7) Blocking the selective ion implantation through the pattern mask to form a heavily doped second conductive type region;
8) Removing the surface mask, coating a carbon film for protection, and then carrying out high-temperature annealing;
9) Removing the carbon film and sacrificing the oxidation treatment surface, and forming a gate insulating layer by a thermal oxygen growth or deposition mode;
10 Depositing doped polysilicon, and forming a gate electrode through photoetching;
11 Silicon dioxide or/and silicon nitride is deposited, and an insulating medium layer is formed through photoetching;
12 Forming an ohmic contact metal layer by evaporation or sputtering;
13 Forming a trench penetrating the first conductive type substrate and the first conductive type buffer layer on the back surface;
14 Filling conductive material into the trench to form a filled collector, and leading out a collector of the second conductivity type;
15 A metal emitter on the front surface is formed by evaporation or sputtering;
16 Forming an ohmic contact metal layer on the back surface by means of evaporation or sputtering, and forming ohmic contact with the first conductive type substrate through laser annealing;
17 A back metal emitter is formed by evaporation or sputtering.
2. The method for manufacturing a SiC reverse conducting insulated gate bipolar transistor device according to claim 1, wherein: after step 11), further comprising the steps of;
and (3) grinding the back surface of the product formed in the step 12) through a grinding wheel to thin the first conductive type substrate, or peeling off and thinning the first conductive type substrate through laser.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110096995.6A CN112951905B (en) | 2021-01-25 | 2021-01-25 | SiC reverse-conduction type insulated gate bipolar transistor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110096995.6A CN112951905B (en) | 2021-01-25 | 2021-01-25 | SiC reverse-conduction type insulated gate bipolar transistor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112951905A CN112951905A (en) | 2021-06-11 |
| CN112951905B true CN112951905B (en) | 2024-03-29 |
Family
ID=76236422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110096995.6A Active CN112951905B (en) | 2021-01-25 | 2021-01-25 | SiC reverse-conduction type insulated gate bipolar transistor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112951905B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116153992B (en) * | 2023-04-21 | 2023-06-23 | 上海陆芯电子科技有限公司 | Reverse-conduction insulated gate bipolar transistor |
| CN117613076A (en) * | 2023-12-08 | 2024-02-27 | 无锡用芯微电子科技有限公司 | Partitioned dual-mode conductive insulated gate bipolar transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103703566A (en) * | 2011-08-02 | 2014-04-02 | 罗姆股份有限公司 | Semiconductor device, and manufacturing method for same |
| CN104681434A (en) * | 2015-01-26 | 2015-06-03 | 电子科技大学 | Preparation method of FS-IGBT |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004066391A1 (en) * | 2003-01-20 | 2004-08-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JP5526811B2 (en) * | 2010-01-29 | 2014-06-18 | 富士電機株式会社 | Reverse conducting insulated gate bipolar transistor |
| US9236433B2 (en) * | 2013-10-10 | 2016-01-12 | Cree, Inc. | Semiconductor devices in SiC using vias through N-type substrate for backside contact to P-type layer |
-
2021
- 2021-01-25 CN CN202110096995.6A patent/CN112951905B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103703566A (en) * | 2011-08-02 | 2014-04-02 | 罗姆股份有限公司 | Semiconductor device, and manufacturing method for same |
| CN104681434A (en) * | 2015-01-26 | 2015-06-03 | 电子科技大学 | Preparation method of FS-IGBT |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112951905A (en) | 2021-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7414268B2 (en) | High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities | |
| JP4967200B2 (en) | Bidirectional IGBT with reverse blocking IGBTs connected in antiparallel | |
| TWI534902B (en) | Method of forming a power semiconductor device and power semiconductor device | |
| US9627486B2 (en) | Semiconductor device | |
| US20170213908A1 (en) | Self-aligned shielded-gate trench mos-controlled silicon carbide switch with reduced miller capacitance and method of manufacturing the same | |
| JP2015128180A (en) | Silicon carbide semiconductor device and manufacturing method of the same | |
| US11961904B2 (en) | Semiconductor device including trench gate structure and buried shielding region and method of manufacturing | |
| JP2019165206A (en) | Insulated gate semiconductor device and method for manufacturing the same | |
| JP2009130266A (en) | Semiconductor substrate and semiconductor device, and method of manufacturing the same | |
| JP2009054931A (en) | Bipolar element and its manufacturing method | |
| JP5646044B2 (en) | Silicon carbide semiconductor device and manufacturing method thereof | |
| JP6802454B2 (en) | Semiconductor devices and their manufacturing methods | |
| JP2010147405A (en) | Semiconductor device and method of manufacturing the same | |
| CN112382655B (en) | Wide bandgap power semiconductor device and preparation method thereof | |
| CN112951905B (en) | SiC reverse-conduction type insulated gate bipolar transistor device and manufacturing method thereof | |
| JP2007288172A (en) | Semiconductor device | |
| JP2015056644A (en) | Silicon carbide semiconductor device and silicon carbide semiconductor device manufacturing method | |
| JP6946824B2 (en) | Semiconductor devices and manufacturing methods for semiconductor devices | |
| JP4049095B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN112951906B (en) | SiC insulated gate bipolar transistor device and manufacturing method thereof | |
| JP5028749B2 (en) | Manufacturing method of semiconductor device | |
| WO2015111177A1 (en) | Semiconductor device, power module, power conversion device, and railway vehicle | |
| JP2018082056A (en) | Semiconductor device and method of manufacturing the same | |
| CN111261713A (en) | Trench type IGBT device structure | |
| JP2006237553A (en) | Semiconductor device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |