CN104681434A - Preparation method of FS-IGBT - Google Patents
Preparation method of FS-IGBT Download PDFInfo
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- CN104681434A CN104681434A CN201510037235.2A CN201510037235A CN104681434A CN 104681434 A CN104681434 A CN 104681434A CN 201510037235 A CN201510037235 A CN 201510037235A CN 104681434 A CN104681434 A CN 104681434A
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Abstract
The invention provides a method for preparing an FS-IGBT (Field Stop-Insulated Gate Bipolar Translator) on a silicon wafer, which is used for solving the problems caused by a thin silicon wafer during a preparation process of a medium/low-voltage FS-IGBT that the preparation technology is complicated, the difficulty is large, the thin silicon wafer warps and deforms and is segmented, the size of the thin silicon wafer (a wafer) is limited, the yield is low, the cost is high, and industrialization is difficult to realize and overcoming the huge technical challenge caused by the thin silicon wafer in follow-up scribing of the wafer and encapsulating of a chip. The preparation method comprises the steps of selecting light-doped FZ silicon as a first silicon wafer and heavy-doped CZ silicon or FZ silicon as a second silicon wafer; firstly, making an N-type FS layer and a P-type transparent collecting zone on the back surface of the first silicon wafer; then, bonding the first silicon wafer and the second silicon wafer; making a front-surface structure by thinning the thickness of the first silicon wafer; finally, thinning the second silicon wafer; forming a collector electrode through etching, metal depositing and chemical-mechanical polishing; obtaining the FS-IGBT.
Description
Technical field
The invention belongs to power semiconductor device technology field, relate to insulated gate bipolar transistor (IGBT), be specifically related to a preparation method for cut-off type insulated gate bipolar transistor (FS-IGBT).
Background technology
Insulated gate bipolar transistor (IGBT) is the novel power transistor of a kind of MOS field effect and bipolar transistor compound, its existing MOSFET is easy to drive, control simple advantage, there is again the pressure drop of power transistor turns low, on state current is large, the advantage that loss is little, becomes one of core electron components and parts in modern power electronic circuit, is widely used in the every field of the national economy such as such as communication, the energy, traffic, industry, medical science, household electrical appliance and Aero-Space.Invention and the application of IGBT serve very important effect to the lifting of power electronic system performance, since the nineties in last century, through the development of device architecture and preparation technology, the IGBT device of commercial production and module thereof have contained voltage from 370V to 6500V, the range of application of electric current from 2A to 4000A.
From device drift region structure and preparation method thereof, IGBT to experienced by from PT (punch) to NPT (non-punch) again to the development of FS (field cut-off type).First generation PT type structure cellular as shown in Figure 1, adopts P
+type CZ monocrystalline silicon piece as substrate, by P
+extension N-type buffer layer and N successively on type CZ silicon chip
-drift region, then at N
-mOS structure prepared by drift region to form.During this structure blocks, device drift region electric field presents class trapezoidal profile, at the N of certain device of resistance to pressure
-drift region thickness is thinner, and forward conduction voltage drop is little; But due to the P as collector region
+substrate doping is high, and thickness is large, and cause collector electrode emission effciency excessive, the turn-off time is long, and current tail phenomenon is obvious, causes turn-off power loss very large, is difficult to the requirement meeting high-speed applications.Therefore, usual PT type IGBT needs to adopt carrier lifetime control technology to reduce carrier lifetime, thus reduces turn-off time and turn-off power loss, but after adopting the method, the forward conduction voltage drop of PT type IGBT device presents negative temperature coefficient, is unfavorable in parallel use.For PT type IGBT structure, owing to being at thicker P
+extension N-type buffer layer and N on substrate
-drift region, therefore can obtain thin N
-drift region thickness, easily prepares the IGBT device of mesolow.
In order to improve the performance of IGBT device, on the basis of PT type IGBT, industry proposes NPT type IGBT structure, and cellular as shown in Figure 2.NPT type structure does not re-use P
+extension N on type substrate
-the technique of layer, but directly use N
-the FZ silicon chip of type, utilizes N
-type FZ backing material as drift region, at N
-mOS structure is prepared in front, type drift region, and is injected by backside particulate and the mode of annealing forms P type collector region.For NPT type IGBT structure, owing to passing through to adopt transparent anode (collector electrode) technology, reduce concentration and the thickness of P type collector region, the back side, substantially reduce collector electrode emission effciency, improve the problem that turn-off power loss is large, by avoiding using the technology such as carrier lifetime control, the forward conduction voltage drop of NPT type IGBT is positive temperature coefficient, makes big current parallel connection application become possibility.But during owing to blocking, the Triangle-Profile of NPT type structure electric field, long in certain resistance to pressure drift region, cause conducting resistance and turn-off power loss comparatively large, be still difficult to the requirement meeting high-speed applications.
In order to improve the performance of IGBT device further, in conjunction with the advantage of PT type and NPT type IGBT, industry proposes FS (field cut-off) type IGBT structure, and cellular as shown in Figure 3.FS-IGBT directly uses N
-type FZ silicon chip, utilizes N
-type FZ backing material as drift region, at N
-mOS structure is prepared in front, type drift region, and adopted diffusion or ion implantation technology to introduce N-type FS layer before being formed in P type transparent collecting zone, thus make drift region electric field present class trapezoidal profile when blocking, substantially reduce the drift region thickness of device in certain resistance to pressure, reduce forward conduction voltage drop; Simultaneously by adopting transparent anode (collector electrode) technology, ensure that the positive temperature characterisitic of conduction voltage drop.In addition, because the P type collector region thickness of FS-IGBT is little, concentration is low, and therefore emission effciency is low, and its tail currents is very little, and switching loss, far below NPT type and PT type structure, becomes the main flow device of high speed low-loss application.But for the FS-IGBT of mesolow, if puncture voltage is the FS-IGBT of 600V, its chip thickness is less than 70um usually, and the FS-IGBT of puncture voltage 400V, its chip thickness only 40um.No matter be adopt first to do front technique (comprising front MOS structure and terminal structure), the mode of the thinning back note in back introduces FS layer and P type collector region, still back process (comprising FS layer and P type collector region) is first done, then the method for front technique is done after thinning, prepare so thin chip, complicated process of preparation, difficulty is large, need very expensive and accurate process equipment, and the too thin distortion easily causing silicon chip of silicon chip, warpage and fragment, the size of silicon chip (wafer) is restricted, yields is low, cost is high, be difficult to realization commercially produce, and the restriction of wafer size makes the preparation of device be difficult to apply the advanced technologies corresponding with large wafer size.In addition, thin chip thickness also brings huge technological challenge for the scribing of silicon chip and the encapsulation etc. of chip, increases process complexity and difficulty, cause preparing similar problem with wafer, the i.e. too thin easy cracking of chip, fragment, yields is low, cost is high, is difficult to realization and commercially produces.
For the PT type IGBT device of mesolow, although P
+the resistivity of type single crystalline substrate is very little, but in order to reduce thick P further
+type resistance substrate is on the impact of device property, Jun Zeng proposes by back cutting and the preparation method of filled conductive material, obtain structure cell (J.Zeng as shown in Figure 4, Semiconductor Devices Having Reduced Effective Substrate Resistivity and Associated Methods, US patent#6104062, #7098108).This structure utilizes the materials such as the metal of high conductivity and thermal conductivity to reduce P
+the conducting resistance of type substrate and thermal resistance, but this structure is still PT type structure, P
+the doping content of type substrate is very high, and P
+type substrate is thicker, particularly in the position not having back cutting to fill, high for this IGBT device collector electrode injection efficiency, still need to adopt the technology such as carrier lifetime control to obtain low switching loss, forward conduction voltage drop is negative temperature coefficient, is not therefore suitable for the preparation of FS-IGBT.
For difficulty prepared by mesolow FS-IGBT, the present invention proposes a kind of preparation method to realize preparing FS-IGBT on thicker silicon chip.
Summary of the invention
The object of the invention is to propose a kind of method preparing FS-IGBT on thick silicon chip, in order to solve in mesolow FS-IGBT preparation process, complicated process of preparation, difficulty that thin silicon wafer is brought are large, silicon warp, distortion, fragment, the size of silicon chip (wafer) is restricted, yields is low, cost is high, be difficult to the problem realizing industrialization, and due to huge technological challenge that thin silicon wafer is brought in the scribing of subsequent wafer and the encapsulation of chip.
The present invention solves the problems of the technologies described above adopted technical scheme:
A preparation method of FS-IGBT, comprises the following steps:
The first step: choose two panels n type single crystal silicon sheet as the first silicon chip and the second silicon chip, wherein the first silicon chip is the lightly doped FZ silicon of thickness 300 ~ 500 microns, and doping content is 10
13~ 10
14individual/cm
3, in order to form the drift region of FS-IGBT; Second silicon chip is heavily doped CZ silicon or the FZ silicon of thickness 300 ~ 500 microns, and doping content is 10
19~ 10
20individual/cm
3, in order to form the N+ district, back of FS-IGBT;
Second step: also annealed by ion implantation N-type impurity at the back side of the first silicon chip and make the N-type FS layer of FS-IGBT, the thickness of the FS layer of formation is 2 ~ 5 microns, and ion implantation energy is 40keV ~ 500keV, and implantation dosage is 10
13~ 10
14individual/cm
2, annealing temperature is 1150-1200 DEG C, and annealing time is 60 ~ 300 minutes;
3rd step: also annealed by ion implantation p type impurity at the back side of the first silicon chip again and make the P type transparent collecting zone of FS-IGBT, the thickness of the P type collector region of formation is 0.5 ~ 2 micron, and ion implantation energy is 30keV ~ 100keV, and implantation dosage is 10
13~ 10
14individual/cm
2, annealing temperature is 1150-1200 DEG C, and annealing time is 0 ~ 60 minute;
4th step: adopt bonding techniques the first silicon chip back side and the second front side of silicon wafer to be bonded together formation the 3rd silicon chip, bonding temperature is 300 ~ 600 DEG C, first silicon chip side of the 3rd silicon chip formed by bonding techniques is front, second silicon chip side is the back side, namely the first front side of silicon wafer is the 3rd front side of silicon wafer, and the second silicon chip back side is the 3rd silicon chip back side;
5th step: thinning 3rd front side of silicon wafer is 30 ~ 80 microns to former first silicon wafer thickness in front, i.e. drift region thinned;
6th step: making the Facad structure of FS-IGBT through the 3rd thinning front side of silicon wafer by repeatedly photoetching, oxidation, ion implantation, annealing, depositing technics, comprise cellular MOS structure and terminal structure etc., wherein, the junction depth of P type tagma and terminal field limiting ring is 2 ~ 3 microns, ion implantation energy is 40keV ~ 120keV, and implantation dosage is 10
13~ 10
14individual/cm
2, annealing temperature is 1100 ~ 1150C, and annealing time is 30 ~ 150 minutes;
7th step: thinning 3rd silicon chip back side is 50 ~ 100 microns to former second silicon wafer thickness at the back side, i.e. N+ district, thinning back;
8th step: adopt photoetching and etching, in the 3rd silicon chip back side cutting after thinning to P type transparent collecting zone;
9th step: depositing metal, filling groove to cover whole 3rd silicon chip back side be 2 ~ 4 microns to thickness;
Tenth step: the metal adopting chemico-mechanical polishing (CMP) planarization back side deposit, forms collector electrode;
Namely FS-IGBT is prepared into.
Further, in described 5th step, the thinning rear drift region thickness of the FS-IGBT device for 400V is 30 ~ 40 microns, and the thinning rear drift region thickness of the FS-IGBT device for 600V is 50 ~ 60 microns.
Further, in described 8th step, etching can adopt the method such as dry etching, directed wet etching, laser drilling, and the shape of the silicon groove formed, depth-to-width ratio and the distribution on silicon chip change according to the thickness in N+ district, back and lithographic method.
Further, in described 9th step, before filling collector electrode metal, first deposit layer of metal barrier layer (as titanium, titanium nitride, tantalum nitride etc.), diffuse in silicon to prevent metal, the metal filled can be layer of metal, and also can be the combination of multiple layer metal, the metal of filling can be tungsten, copper or aluminium etc.
Further, in described 6th step, Facad structure is planar gate structure or trench gate structure.
It should be noted that, in order to simplified characterization, above-mentioned preparation method illustrates for n raceway groove FS-IGBT device, but the present invention is equally applicable to the preparation of p raceway groove FS-IGBT device.And processing step in the preparation method of above-mentioned FS-IGBT and process conditions can carry out additions and deletions and adjustment according to actual needs;
The present invention prepares the FS-IGBT structure cell of gained as shown in Figure 5.When device forward conduction, grid 8 voltage is high potential, and device surface MOS structure raceway groove is opened, back N
+the PN junction J2 that district 11 and P type transparent collecting zone 1 are formed is reverse-biased, and the back collector electrode metal 7 short circuit N that cutting is filled
+district 11 and P type transparent collecting zone 8, therefore back N
+district 11 does not affect the forward conduction characteristic (comprising Carrier Profile during forward conduction) of FS-IGBT device, thus can not affect the turn-off characteristic of device yet.In addition, when forward conduction, electric current not only can pass through back N
+the collector electrode metal 7 that between district 11, cutting is filled flows, and all right diffuse transmission P type transparent collecting zone 1 of portions of electronics, through back N
+district 11 arrives the collector electrode metal 7 of side and below, avoids the problem of current convergence, and this phenomenon is thinner and more obvious when adulterating lower in FS-IGBT device P type transparent collecting zone 1.When device blocks, grid 8 current potential is electronegative potential, and collector electrode 7 is high potential, P type tagma, front 4 and N
-the PN junction J1 that drift region 3 is formed is reverse-biased, bears the withstand voltage of device, due to the existence of FS layer, and the N when device breakdown
-electric field in drift region 3 presents class trapezoidal profile.Due to back N
+the PN junction J2 that district 11 and P type transparent collecting zone 1 are formed is reverse-biased, and the back collector electrode metal 7 short circuit N that cutting is filled
+district 11 and P type transparent collecting zone 8, therefore back N
+district 11 does not affect the blocking characteristics of FS-IGBT device.
Beneficial effect of the present invention shows:
The present invention can adopt thick silicon chip preparation to have the mesolow FS-IGBT of thin drift region in whole chip fabrication process, and the described FS-IGBT device finally prepared also has thick silicon wafer thickness.The preparation method of a kind of FS-IGBT provided by the invention can solve in mesolow FS-IGBT preparation process, complicated process of preparation, difficulty that thin silicon wafer is brought are large, silicon warp, distortion, fragment, the size of silicon chip (wafer) is restricted, be difficult to use the advanced technologies corresponding with large scale wafer, yields is low, cost is high, be difficult to the problem realizing industrialization, and due to huge technological challenge that thin silicon wafer is brought in the scribing of subsequent wafer and the encapsulation of chip.The IGBT that the present invention is formed is FS type, does not need to adopt lifetime control techniques, has that the such as forward conduction voltage drop same with the FS-IGBT that conventional method obtains is low, turn-off power loss is little, conduction voltage drop is the advantages such as positive temperature coefficient.Therefore, preparation method of the present invention is applicable to the preparation of FS-IGBT device, particularly the preparation of mesolow FS-IGBT.
Accompanying drawing explanation
Fig. 1 is the T-shaped IGBT structure schematic diagram of conventional P; In Fig. 1: 1 is heavily doped P-type backing material, 2 is N-type resilient coating (buffer), and 3 is N
-drift region, 4 is P type body contact zone, and 5 is N-type body contact zone, and 6 is metal emitting, and 7 is metal collector, and 8 is grid, and 9 is gate medium, and 10 is spacer medium.
Fig. 2 is NPT type IGBT structure schematic diagram; In Fig. 2: 1 is P type transparent collecting zone, and 3 is N
-drift region, 4 is P type body contact zone, and 5 is N-type body contact zone, and 6 is metal emitting, and 7 is metal collector, and 8 is grid, and 9 is gate medium, and 10 is spacer medium.
Fig. 3 is FS type IGBT structure schematic diagram; In Fig. 3: 1 is P type transparent collecting zone, 2 is N-type field cutoff layer (FS), and 3 is N
-drift region, 4 is P type body contact zone, and 5 is N-type body contact zone, and 6 is metal emitting, and 7 is metal collector, and 8 is grid, and 9 is gate medium, and 10 is spacer medium.
Fig. 4 is the IGBT structure schematic diagram involved by Jun Zeng patent; In Fig. 4: 1 is heavily doped P-type backing material, 2 is N-type resilient coating (buffer), and 3 is N
-drift region, 4 is P type body contact zone, and 5 is N-type body contact zone, and 6 is metal emitting, and 7 is metal collector, and 8 is grid, and 9 is gate medium, and 10 is spacer medium.
Fig. 5 is FS-IGBT structural representation prepared by described preparation method provided by the invention; In Fig. 5: 1 is P type transparent collecting zone, 2 is N-type field cutoff layer (FS), and 3 is N
-drift region, 4 is P type body contact zone, and 5 is N-type body contact zone, and 6 is metal emitting, and 7 is metal collector, and 8 is grid, and 9 is gate medium, and 10 is spacer medium, and 11 is back side N
+district.
Fig. 6 is the schematic flow sheet of preparation method provided by the invention.
Fig. 7 to Figure 12 is the concrete technology schematic flow sheet of preparation method provided by the invention.
Figure 13 is the FS-IGBT that preparation method provided by the invention obtains, the IGBT that traditional F S-IGBT and Jun Zeng patent the relate to collector current simulation curve comparison diagram when turning off.
Embodiment
Below in conjunction with accompanying drawing, be described further principle and character of the present invention, example, only for explaining the present invention, is not intended to limit scope of the present invention.
As shown in Figure 6, the invention provides a kind of on thick silicon chip preparation there is the method for thin drift region FS-IGBT, comprising:
The first step: choose two panels n type single crystal silicon sheet as the first silicon chip and the second silicon chip, wherein the first silicon wafer thickness is 300 microns, adopts lightly doped FZ silicon, and doping content is 2.5*10
14individual/cm
3, be 300 microns in order to form drift region 3, second silicon wafer thickness of FS-IGBT described in Fig. 5, adopt heavily doped CZ silicon, doping content is 5*10
19individual/cm
3, in order to form the N+ district, back 11 of FS-IGBT described in Fig. 5, as Figure 7-8;
Second step: also annealed by ion implantation N-type impurity at the back side of the first silicon chip and prepare the N-type FS layer 2 of FS-IGBT described in Fig. 5, the thickness of the FS layer of formation is 2 microns, and typical ion implantation energy is 350keV, and implantation dosage is 1*10
13individual/cm
2, annealing temperature is 1200 DEG C, and annealing time is 60 minutes;
3rd step: also annealed by ion implantation p type impurity at the back side of the first silicon chip again and prepare the P type transparent collecting zone 1 of FS-IGBT described in Fig. 5, the thickness of the P type collector region of formation is 0.5 micron, and typical ion implantation energy is 40keV, and implantation dosage is 1*10
13individual/cm
2, annealing temperature is 1200 DEG C, and annealing time is 10 minutes, as shown in Figure 9;
4th step: adopt bonding techniques the first silicon chip back side and the second front side of silicon wafer to be bonded together formation the 3rd silicon chip, bonding temperature is 600 DEG C, first silicon chip side of the 3rd silicon chip formed by bonding techniques is front, second silicon chip side is the back side, namely the first front side of silicon wafer is the 3rd front side of silicon wafer, second silicon chip back side is the 3rd silicon chip back side, as shown in Figure 10;
5th step: thinning 3rd front side of silicon wafer is 340 microns to the 3rd silicon chip gross thickness, namely thinning 3rd front side of silicon wafer to former first silicon wafer thickness is 40 microns;
6th step: the Facad structure being prepared FS-IGBT at the 3rd front side of silicon wafer through the 5th step by techniques such as repeatedly photoetching, oxidation, ion implantation, annealing, deposits, comprise cellular MOS structure and terminal structure etc., the junction depth of typical MOS structure P type tagma and terminal field limiting ring is 2 microns, typical ion implantation energy is 60keV, and implantation dosage is 1*10
14individual/cm
2, annealing temperature is 1150 DEG C, and annealing time is 30 minutes, in this step, 1150 DEG C of annealing temperatures and 30 minutes annealing times can obtain two beneficial effects: 1) reduced the defects such as the cavity of bonded interface in the 4th step further by pyroprocess, improve the quality of bonded interface, 2) in pyroprocess due to the existence of concentration gradient, N-type FS layer 2, impurity in P type transparent collecting zone 1 and the 3rd silicon chip side, silicon chip Central Plains second high concentration N-type substrate 11 will distribute again, because the former second silicon chip side N-type substrate 11 middle and high concentration N-type impurity of large concentration gradient to be greater than in P type transparent collecting zone 1 p type impurity to the diffusion velocity of FS layer 2 side to the speed of former first silicon chip side diffusion, simultaneously in P type transparent collecting zone 1, p type impurity is greater than the diffusion velocity of FS layer 2 to drift region 3 to the diffusion velocity of FS layer 2 side, by the compensation of impurity, can obtain that to have typical thickness be 0.3 micron, peak concentration is 3*10
17individual/cm
3p type transparent collecting zone 1, and to obtain typical thickness be 2 microns, and peak concentration is 1*10
17individual/cm
3fS layer, as shown in figure 11,
7th step: thinning 3rd silicon chip back side is 140 microns to the 3rd silicon chip gross thickness, the typical thickness in the N+ district, back 11 after namely thinning is 100 microns;
8th step: photoetching and etching, in the 3rd silicon chip back side cutting to P type transparent collecting zone 1;
9th step: depositing metal, filling groove also covers 11 to 3 microns, N+ district, whole back, and the metal of deposit and P type transparent collecting zone 1 and N+ district, back 11 form ohmic contact respectively;
Tenth step: the metal of chemico-mechanical polishing (CMP) planarization backside deposition, forms collector electrode 7;
Namely the FS-IGBT of preparation is obtained, as shown in figure 12;
Figure 13 is the FS-IGBT that described preparation method provided by the invention obtains, the IGBT (Fig. 5 structure) that traditional F S-IGBT (Fig. 4 structure) and Jun Zeng patent the relate to collector current simulation curve contrast when turning off.Three kinds of structures adopt identical front MOS structure, identical drift region concentration, thickness and carrier lifetime.As can be seen from the figure, the FS-IGBT that preparation method of the present invention obtains has the fastest turn-off speed, and the turn-off speed of traditional F S-IGBT is slightly slow, and the IGBT that Jun Zeng patent relates to shows very long delay and hangover time, and turn-off speed is the slowest.The IGBT that the present invention is formed is FS type, does not need to adopt lifetime control techniques, can have that the such as forward conduction voltage drop same with the FS-IGBT that conventional method obtains is low, turn-off power loss is little, conduction voltage drop is the advantages such as positive temperature coefficient.Therefore, preparation method of the present invention is applicable to the preparation of FS-IGBT device, particularly the preparation of mesolow FS-IGBT.
The present invention can adopt thick silicon chip preparation to have the mesolow FS-IGBT of thin drift region in whole chip fabrication process, and the described FS-IGBT device finally prepared also has thick silicon wafer thickness.The preparation method of a kind of FS-IGBT provided by the invention can solve in mesolow FS-IGBT preparation process, complicated process of preparation, difficulty that thin silicon wafer is brought are large, silicon warp, distortion, fragment, the size of silicon chip (wafer) is restricted, be difficult to use the advanced technologies corresponding with large scale wafer, yields is low, cost is high, be difficult to the problem realizing commercially producing, and due to huge technological challenge that thin silicon wafer is brought in the scribing of subsequent wafer and the encapsulation of chip.
Claims (7)
1. a preparation method of FS-IGBT, comprises the following steps:
The first step: choose two panels n type single crystal silicon sheet as the first silicon chip and the second silicon chip, wherein the first silicon chip is the lightly doped FZ silicon of thickness 300 ~ 500 microns, and doping content is 10
13~ 10
14individual/cm
3, in order to form the drift region of FS-IGBT; Second silicon chip is heavily doped CZ silicon or the FZ silicon of thickness 300 ~ 500 microns, and doping content is 10
19~ 10
20individual/cm
3, in order to form the N+ district, back of FS-IGBT;
Second step: also annealed by ion implantation N-type impurity at the back side of the first silicon chip and make the N-type FS layer of FS-IGBT, the thickness of the FS layer of formation is 2 ~ 5 microns, and ion implantation energy is 40keV ~ 500keV, and implantation dosage is 10
13~ 10
14individual/cm
2, annealing temperature is 1150-1200 DEG C, and annealing time is 60 ~ 300 minutes;
3rd step: also annealed by ion implantation p type impurity at the back side of the first silicon chip again and make the P type transparent collecting zone of FS-IGBT, the thickness of the P type collector region of formation is 0.5 ~ 2 micron, and ion implantation energy is 30keV ~ 100keV, and implantation dosage is 10
13~ 10
14individual/cm
2, annealing temperature is 1150-1200 DEG C, and annealing time is 0 ~ 60 minute;
4th step: adopt bonding techniques the first silicon chip back side and the second front side of silicon wafer to be bonded together formation the 3rd silicon chip, bonding temperature is 300 ~ 600 DEG C, and the first silicon chip side of the 3rd silicon chip formed by bonding techniques is front, and the second silicon chip side is the back side;
5th step: thinning 3rd front side of silicon wafer to former first silicon wafer thickness is 30 ~ 80 microns, i.e. drift region thinned;
6th step: making the Facad structure of FS-IGBT through the 3rd thinning front side of silicon wafer by photoetching, oxidation, ion implantation, annealing, depositing technics, comprise cellular MOS structure and terminal structure, wherein, the junction depth of P type tagma and terminal field limiting ring is 2 ~ 3 microns, ion implantation energy is 40keV ~ 120keV, and implantation dosage is 10
13~ 10
14individual/cm
2, annealing temperature is 1100 ~ 1150C, and annealing time is 30 ~ 150 minutes;
7th step: thinning 3rd silicon chip back side to former second silicon wafer thickness is 50 ~ 100 microns, i.e. N+ district, thinning back;
8th step: adopt photoetching and etching, in the 3rd silicon chip back side cutting after thinning to P type transparent collecting zone;
9th step: depositing metal, filling groove to cover whole 3rd silicon chip back side be 2 ~ 4 microns to thickness;
Tenth step: the metal adopting chemico-mechanical polishing planarization back side deposit, forms collector electrode;
Namely FS-IGBT is prepared into.
2. by the preparation method of FS-IGBT described in claim 1, it is characterized in that, in described 5th step, the thinning rear drift region thickness of the FS-IGBT device for 400V is 30 ~ 40 microns, and the thinning rear drift region thickness of the FS-IGBT device for 600V is 50 ~ 60 microns.
3. by the preparation method of FS-IGBT described in claim 1, it is characterized in that, in described 8th step, etching adopts the method for dry etching, directed wet etching or laser drilling, and the shape of the silicon groove formed, depth-to-width ratio and the distribution on silicon chip are determined according to the thickness in N+ district, back and lithographic method.
4. by the preparation method of FS-IGBT described in claim 1, it is characterized in that, in described 9th step, before filling collector electrode metal, first deposit layer of metal barrier layer, diffuses in silicon to prevent metal.
5., by the preparation method of FS-IGBT described in claim 4, it is characterized in that, the metal material of described metal barrier is titanium, titanium nitride or tantalum nitride.
6., by the preparation method of FS-IGBT described in claim 1, it is characterized in that, in described 9th step, the metal of filling can be layer of metal, and also can be the combination of multiple layer metal, the metal of filling be tungsten, copper or aluminium.
7., by the preparation method of FS-IGBT described in claim 1, it is characterized in that, in described 6th step, Facad structure is planar gate structure or trench gate structure.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106898554A (en) * | 2017-03-17 | 2017-06-27 | 电子科技大学 | A kind of field cut-off type reverse-conducting insulated gate bipolar transistor npn npn preparation method |
| CN109473541A (en) * | 2018-12-25 | 2019-03-15 | 黑龙江大学 | A kind of hetero-junction silicon magnetic sensitive transistor and process for making |
| CN112951905A (en) * | 2021-01-25 | 2021-06-11 | 南瑞联研半导体有限责任公司 | SiC reverse conducting type insulated gate bipolar transistor device and manufacturing method thereof |
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| US5372954A (en) * | 1991-07-24 | 1994-12-13 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating an insulated gate bipolar transistor |
| JP2002261281A (en) * | 2001-03-01 | 2002-09-13 | Hitachi Ltd | Manufacturing method of insulated gate bipolar transistor |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106898554A (en) * | 2017-03-17 | 2017-06-27 | 电子科技大学 | A kind of field cut-off type reverse-conducting insulated gate bipolar transistor npn npn preparation method |
| CN109473541A (en) * | 2018-12-25 | 2019-03-15 | 黑龙江大学 | A kind of hetero-junction silicon magnetic sensitive transistor and process for making |
| CN112951905A (en) * | 2021-01-25 | 2021-06-11 | 南瑞联研半导体有限责任公司 | SiC reverse conducting type insulated gate bipolar transistor device and manufacturing method thereof |
| CN112951905B (en) * | 2021-01-25 | 2024-03-29 | 南瑞联研半导体有限责任公司 | SiC reverse-conduction type insulated gate bipolar transistor device and manufacturing method thereof |
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| CN104681434B (en) | 2017-05-10 |
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