CN103855206A - Insulated gate bipolar transistor and manufacturing method thereof - Google Patents
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- CN103855206A CN103855206A CN201410055323.0A CN201410055323A CN103855206A CN 103855206 A CN103855206 A CN 103855206A CN 201410055323 A CN201410055323 A CN 201410055323A CN 103855206 A CN103855206 A CN 103855206A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 30
- 238000002347 injection Methods 0.000 claims abstract description 19
- 239000007924 injection Substances 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 39
- 229910052710 silicon Inorganic materials 0.000 claims description 39
- 239000010703 silicon Substances 0.000 claims description 39
- 239000000758 substrate Substances 0.000 claims description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 238000002513 implantation Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 39
- 101100204059 Caenorhabditis elegans trap-2 gene Proteins 0.000 description 16
- 239000011229 interlayer Substances 0.000 description 5
- 230000001276 controlling effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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Abstract
The invention discloses an insulated gate bipolar transistor. A collector region is composed of a first P+ region and a second P- region. The doping concentration of the first P+ region is larger than that of the second P- region. The junction depth of the first P+ region is smaller than that of the second P- region. The second P- region makes direct contact with a drift region. The first P+ region makes contact with a metal layer on the reverse side of a collector electrode. The first P+ region makes contact with the metal layer on the reverse side to form ohmic contact so as to reduce contact resistance and breakover voltage drop. The second P- region is used for controlling the injection efficiency of the collector region. The lower the doping concentration of the second P- region is, the lower the injection efficiency of the collector region is, and the higher the switching speed of the insulated gate bipolar transistor is. The invention further discloses a manufacturing method of the insulated gate bipolar transistor. The insulated gate bipolar transistor is capable of increasing the switching speed of a device and reducing the breakover voltage drop of the device.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of igbt, the invention still further relates to a kind of manufacture method of igbt.
Background technology
Igbt (Insulated Gate Bipolar Transistor, IGBT) be the bipolar compound power device of a kind of voltage-controlled MOS/, this device has the major advantage of dipole power transistor and power MOSFET simultaneously: input impedance is high, input driving power is little, conducting resistance is little, current capacity is large, switching speed is fast etc., and IGBT device is generally applied as high-voltage switch gear.Conventionally according to electric field in drift region in-fighting condition heartily, be divided into punch (PT)-IGBT, non-punch (NPT)-IGBT and termination type (FS)-IGBT, the bottom of the drift region of PT-IGBT is formed with the resilient coating of YouN+ district composition, and the bottom of the drift region of NPT-IGBT does not arrange the resilient coating of YouN+ district composition; The bottom of the drift region of FS-IGBT is formed with the field suspension layer of YouN+ district composition, and FS-IGBT belongs to the one of PT-IGBT strictly speaking, but owing to having a long way to go with traditional PT-IGBT technique, general independent listing.
As shown in Figure 1, be the structural representation of existing NPT-IGBT; Existing NPT-IGBT comprises: drift region 101, and the silicon substrate being adulterated by N-type forms, and drift region 101 is high withstand voltage for realizing; P trap 102, is formed at the top of described drift region 101; Emitter region 103, forms by being formed at described P trap 102 top surface N+ districts, and described P trap 102 separates described emitter region 103 and described drift region 101.
Grid, P trap 102 described in cover part, described P trap 102 surfaces that covered by described grid are used to form raceway groove, and described raceway groove connects described drift region 101 and the described emitter region 103 of described P trap 102 both sides.Grid in Fig. 1 is trench gate, comprises groove, gate dielectric layer 104 and polysilicon gate 105, and gate dielectric layer is a thermal oxide layer conventionally; Described groove passes described P trap 102 and enters into described drift region 101 from the top surface of described silicon substrate, described gate dielectric layer 104 covers bottom and the sidewall surfaces of described groove, and described polysilicon gate 105 is positioned at described gate dielectric layer 104 surfaces and by described trench fill; Described grid covers described P trap 102 from the side.
Also be formed with interlayer film 106 and contact hole and front metal layer (not shown) in the front of silicon substrate, contact hole is respectively used to realize the connection of emitter region 103 and front metal layer and the connection of polysilicon gate 105 and front metal layer.
Collector region 107, the top that is formed at described silicon substrate bottom and described collector region 107 contacts with the bottom of described drift region 101.
Collector electrode 108, is made up of the metal layer on back that is formed at the described silicon substrate back side, and collector region 107 and described collector electrode contact.
In prior art, collector region 107 is conventionally just injected as boron (B) injects and is formed by P type, then activate by process annealing, form the p type island region of single layer structure, be that described collector region 107 is made up of the p type island region of single doped structure, between final collector region 107 and drift region 101, form P/N knot.
In existing IGBT preparation technology, be first positive technique, comprise that oxidation, Implantation, exposure, deposit and etching etc. form positive drift region 101, P trap 102, emitter region 103 and grid structure and interlayer film 106, contact hole and front metal.Then be the reduction process at the back side.According to the difference of the structure of device and the electric pressure of application, the thickness after final attenuate is also different.Carry out afterwards back side P type Implantation and annealing form collector region 107, between carry out back face metalization form collector electrode.
The conducting voltage of IGBT and turn-off time are its most important parameters, and optimum IGBT should have low conduction voltage drop and fast turn-off speed.The back side is used high concentration P type to inject also doping content when collector region 107 when higher, can improve the injection effect of both hole and electron, reduce surface contacted resistance simultaneously, thereby reduction conduction voltage drop, but in the time turn-offing, the recombination time of electron hole that remains in drift region 101 is long, thereby causes switching speed slack-off; Otherwise the back side is used low concentration P type to inject also doping content when collector region 107 when lower, can reduce the injection effect of both hole and electron, improve switching speed, but can cause both hole and electron injection effect lower, also can cause contact resistance to increase simultaneously, thereby cause conduction voltage drop to rise.Therefore there is conflicting relation in switching speed and conduction voltage drop, must between conduction voltage drop and switching speed, compromise.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of igbt, and the switching speed that can improve device also reduces the conduction voltage drop of device simultaneously; For this reason, the present invention also provides a kind of manufacture method of igbt.
For solving the problems of the technologies described above, igbt provided by the invention comprises:
Drift region, the silicon substrate being adulterated by N-type forms.
P trap, is formed at the top of described drift region.
Emitter region, forms by being formed at described P trap top surface N+ district, and described P trap separates described emitter region and described drift region.
Grid, P trap described in cover part, the described P trap surface being covered by described grid is used to form raceway groove, and described raceway groove connects described drift region and the described emitter region of described P trap both sides.
Collector region, is formed at described silicon substrate bottom and the top of described collector region and the bottom of described drift region and contacts; Described collector region is made up of Yi P+ district and Er P-district, and described Yi P+ district and described Er P-district are all the ion implanted regions of injecting from the described silicon substrate back side; The doping content in described Yi P+ district is greater than the doping content in described Er P-district, the junction depth in described Yi P+ district is less than the junction depth in described Er P-district, described Er P-district directly contacts with described drift region, and described Yi P+ district and described drift region are separated by a distance.
Collector electrode, is made up of the metal layer on back that is formed at the described silicon substrate back side, and described Yi P+ district and described collector electrode contact.
Thereby described Yi P+ district and described metal layer on back form ohmic contact for reducing contact resistance, reducing conduction voltage drop; Described Er P-district is for controlling the injection efficiency of described collector region, and doping content injection efficiency lower, described collector region the switching speed lower, igbt in described Er P-district is faster.
Further improve and be, described grid is trench gate, described grid comprises groove, gate dielectric layer and polysilicon gate, described groove passes described P trap and enters into described drift region from the top surface of described silicon substrate, described gate dielectric layer covers bottom and the sidewall surfaces of described groove, and described polysilicon gate is positioned at described gate dielectric layer surface and by described trench fill; Described grid covers described P trap from the side.
Further improve is that the Implantation Energy that the back side in described Yi P+ district is injected is 20Kev; The Implantation Energy that the back side in described Er P-district is injected is 300Kev.
For solving the problems of the technologies described above, the manufacture method of igbt provided by the invention comprises:
Step 1, provide a silicon substrate, described silicon substrate is carried out to N-type doping and form drift region.
Step 3, form grid, P trap described in described grid cover part, the described P trap surface being covered by described grid is used to form raceway groove.
Step 4, the emitter region forming in described P trap top surface formation YouN+ district, described P trap separates described emitter region and described drift region; Described raceway groove connects described drift region and the described emitter region of described P trap both sides.
Step 5, described silicon substrate is carried out thinning back side and carries out twice back side and inject and form the collector region being made up of Yi P+ district and Er P-district, the top of described collector region contacts with the bottom of described drift region; Inject by the back side for the first time the ion implanted region forming and form described Er P-district, inject by the back side for the second time the ion implanted region forming and form described Yi P+ district, the doping content in described Yi P+ district is greater than the doping content in described Er P-district, the junction depth in described Yi P+ district is less than the junction depth in described Er P-district, described Er P-district directly contacts with described drift region, and described Yi P+ district and described drift region are separated by a distance.
Thereby described Yi P+ district and described metal layer on back form ohmic contact for reducing contact resistance, reducing conduction voltage drop; Described Er P-district is for controlling the injection efficiency of described collector region, and doping content injection efficiency lower, described collector region the switching speed lower, igbt in described Er P-district is faster.
Step 6, form metal layer on back form collector electrode by this metal layer on back at the described silicon substrate back side, described Yi P+ district and described collector electrode contact.
Further improve and be, described grid in step 3 is trench gate, described grid comprises groove, gate dielectric layer and polysilicon gate, described groove passes described P trap and enters into described drift region from the top surface of described silicon substrate, described gate dielectric layer covers bottom and the sidewall surfaces of described groove, and described polysilicon gate is positioned at described gate dielectric layer surface and by described trench fill; Described grid covers described P trap from the side.
Further improve is that the Implantation Energy that the described back side is for the second time injected is 20Kev; The Implantation Energy that the described back side is for the first time injected is 300Kev.
Collector region of the present invention is set to two kinds of double-deckers that doping content is different with junction depth, finally between collector region and drift region, forms the structure of P+/P-/N knot; Wherein Yi P+ district can form good ohmic contact by back metal, can effectively reduce the contact resistance of collector region and collector electrode metal layer, thereby reduces conduction voltage drop; And the doping content in Er P-district is wherein lower and directly contact with drift region, by regulating the doping content in Er P-district can regulate the injection efficiency of collector region, doping content injection efficiency lower, collector region the switching speed lower, igbt in Er P-district is faster, so the present invention can also provide the switching speed of device in reducing conduction voltage drop.
Brief description of the drawings
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of existing NPT-IGBT;
Fig. 2 is the structural representation of embodiment of the present invention IGBT.
Embodiment
As shown in Figure 2, be the structural representation of embodiment of the present invention IGBT, embodiment of the present invention igbt comprises:
Drift region 1, the silicon substrate being adulterated by N-type forms.
Emitter region 3, forms by being formed at described P trap 2 top surface N+ districts, and described P trap 2 separates described emitter region 3 and described drift region 1.
Grid, P trap 2 described in cover part, described P trap 2 surfaces that covered by described grid are used to form raceway groove, and described raceway groove connects described drift region 1 and the described emitter region 3 of described P trap 2 both sides.Be preferably, described grid is trench gate, described grid comprises groove, gate dielectric layer 4 and polysilicon gate 5, described groove passes described P trap 2 and enters into described drift region 1 from the top surface of described silicon substrate, described gate dielectric layer 4 covers bottom and the sidewall surfaces of described groove, and described polysilicon gate 5 is positioned at described gate dielectric layer 4 surfaces and by described trench fill; Described grid covers described P trap 2 from the side.In other embodiments, described grid can be also planar gate, and at this moment grid is formed at the surface of described silicon substrate.
Also be formed with interlayer film 6 and contact hole and front metal layer (not shown) in the front of described silicon substrate, contact hole is respectively used to realize the connection of emitter region 3 and front metal layer and the connection of polysilicon gate 5 and front metal layer.
Collector region, the top that is formed at described silicon substrate bottom and described collector region contacts with the bottom of described drift region 1; Described collector region is made up of Yi P+ district 7a and Er P-district 7b, and described Yi P+ district 7a and described Er P-district 7b are the ion implanted regions of injecting from the described silicon substrate back side; The doping content of described Yi P+ district 7a is greater than the doping content of described Er P-district 7b, the junction depth of described Yi P+ district 7a is less than the junction depth of described Er P-district 7b, described Er P-district 7b directly contacts with described drift region 1, and described Yi P+ district 7a and described drift region 1 are separated by a distance.Be preferably, the Implantation Energy that the back side of described Yi P+ district 7a is injected is 20Kev; The Implantation Energy that the back side of described Er P-district 7b is injected is 300Kev.
Thereby described Yi P+ district 7a and described metal layer on back form good ohmic contact for reducing contact resistance, reducing conduction voltage drop; Described Er P-district 7b is for controlling the injection efficiency of described collector region, and doping content injection efficiency lower, described collector region the switching speed lower, igbt of described Er P-district 7b is faster.
The manufacture method of embodiment of the present invention igbt comprises:
Step 1, provide a silicon substrate, described silicon substrate is carried out to N-type doping and form drift region 1.
Step 3, form grid, P trap 2 described in described grid cover part, described P trap 2 surfaces that covered by described grid are used to form raceway groove.Be preferably, described grid is trench gate, described grid comprises groove, gate dielectric layer 4 and polysilicon gate 5, described groove passes described P trap 2 and enters into described drift region 1 from the top surface of described silicon substrate, described gate dielectric layer 4 covers bottom and the sidewall surfaces of described groove, and described polysilicon gate 5 is positioned at described gate dielectric layer 4 surfaces and by described trench fill; Described grid covers described P trap 2 from the side.In other embodiments, described grid can be also planar gate, and at this moment grid is formed at the surface of described silicon substrate.
Step 4, the emitter region 3 forming in described P trap 2 top surfaces formation YouN+ districts, described P trap 2 separates described emitter region 3 and described drift region 1; Described raceway groove connects described drift region 1 and the described emitter region 3 of described P trap 2 both sides.
Also form afterwards interlayer film 6 and contact hole and front metal layer (not shown) in the front of described silicon substrate, contact hole is rushed across described interlayer film 6 and is respectively used to realize the connection of emitter region 3 and front metal layer and the connection of polysilicon gate 5 and front metal layer.
Step 5, described silicon substrate is carried out thinning back side and carries out twice back side and inject and form the collector region being made up of Yi P+ district 7a and Er P-district 7b, the top of described collector region contacts with the bottom of described drift region 1; Inject by the back side for the first time the ion implanted region forming and form described Er P-district 7b, inject by the back side for the second time the ion implanted region forming and form described Yi P+ district 7a, the doping content of described Yi P+ district 7a is greater than the doping content of described Er P-district 7b, the junction depth of described Yi P+ district 7a is less than the junction depth of described Er P-district 7b, described Er P-district 7b directly contacts with described drift region 1, and described Yi P+ district 7a and described drift region 1 are separated by a distance.Be preferably, the Implantation Energy that the described back side is for the second time injected is 20Kev; The Implantation Energy that the described back side is for the first time injected is 300Kev.
Thereby described Yi P+ district 7a and described metal layer on back form good ohmic contact for reducing contact resistance, reducing conduction voltage drop; Described Er P-district 7b is for controlling the injection efficiency of described collector region, and doping content injection efficiency lower, described collector region the switching speed lower, igbt of described Er P-district 7b is faster.
Step 6, form metal layer on back form collector electrode 8 by this metal layer on back at the described silicon substrate back side, described Yi P+ district 7a and described collector electrode 8 contact.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (6)
1. an igbt, is characterized in that, comprising:
Drift region, the silicon substrate being adulterated by N-type forms;
P trap, is formed at the top of described drift region;
Emitter region, forms by being formed at described P trap top surface N+ district, and described P trap separates described emitter region and described drift region;
Grid, P trap described in cover part, the described P trap surface being covered by described grid is used to form raceway groove, and described raceway groove connects described drift region and the described emitter region of described P trap both sides;
Collector region, is formed at described silicon substrate bottom and the top of described collector region and the bottom of described drift region and contacts; Described collector region is made up of Yi P+ district and Er P-district, and described Yi P+ district and described Er P-district are all the ion implanted regions of injecting from the described silicon substrate back side; The doping content in described Yi P+ district is greater than the doping content in described Er P-district, the junction depth in described Yi P+ district is less than the junction depth in described Er P-district, described Er P-district directly contacts with described drift region, and described Yi P+ district and described drift region are separated by a distance;
Collector electrode, is made up of the metal layer on back that is formed at the described silicon substrate back side, and described Yi P+ district and described collector electrode contact;
Thereby described Yi P+ district and described metal layer on back form ohmic contact for reducing contact resistance, reducing conduction voltage drop; Described Er P-district is for controlling the injection efficiency of described collector region, and doping content injection efficiency lower, described collector region the switching speed lower, igbt in described Er P-district is faster.
2. igbt as claimed in claim 1, it is characterized in that: described grid is trench gate, described grid comprises groove, gate dielectric layer and polysilicon gate, described groove passes described P trap and enters into described drift region from the top surface of described silicon substrate, described gate dielectric layer covers bottom and the sidewall surfaces of described groove, and described polysilicon gate is positioned at described gate dielectric layer surface and by described trench fill; Described grid covers described P trap from the side.
3. igbt as claimed in claim 1, is characterized in that: the Implantation Energy that the back side in described Yi P+ district is injected is 20Kev; The Implantation Energy that the back side in described Er P-district is injected is 300Kev.
4. a manufacture method for igbt, is characterized in that, comprising:
Step 1, provide a silicon substrate, described silicon substrate is carried out to N-type doping and form drift region;
Step 2, form P trap at the top of described drift region;
Step 3, form grid, P trap described in described grid cover part, the described P trap surface being covered by described grid is used to form raceway groove;
Step 4, the emitter region forming in described P trap top surface formation YouN+ district, described P trap separates described emitter region and described drift region; Described raceway groove connects described drift region and the described emitter region of described P trap both sides;
Step 5, described silicon substrate is carried out thinning back side and carries out twice back side and inject and form the collector region being made up of Yi P+ district and Er P-district, the top of described collector region contacts with the bottom of described drift region; Inject by the back side for the first time the ion implanted region forming and form described Er P-district, inject by the back side for the second time the ion implanted region forming and form described Yi P+ district, the doping content in described Yi P+ district is greater than the doping content in described Er P-district, the junction depth in described Yi P+ district is less than the junction depth in described Er P-district, described Er P-district directly contacts with described drift region, and described Yi P+ district and described drift region are separated by a distance;
Thereby described Yi P+ district and described metal layer on back form ohmic contact for reducing contact resistance, reducing conduction voltage drop; Described Er P-district is for controlling the injection efficiency of described collector region, and doping content injection efficiency lower, described collector region the switching speed lower, igbt in described Er P-district is faster;
Step 6, form metal layer on back form collector electrode by this metal layer on back at the described silicon substrate back side, described Yi P+ district and described collector electrode contact.
5. method as claimed in claim 4, it is characterized in that: the described grid in step 3 is trench gate, described grid comprises groove, gate dielectric layer and polysilicon gate, described groove passes described P trap and enters into described drift region from the top surface of described silicon substrate, described gate dielectric layer covers bottom and the sidewall surfaces of described groove, and described polysilicon gate is positioned at described gate dielectric layer surface and by described trench fill; Described grid covers described P trap from the side.
6. method as claimed in claim 4, is characterized in that: the Implantation Energy that the described back side is for the second time injected is 20Kev; The Implantation Energy that the described back side is for the first time injected is 300Kev.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104992968A (en) * | 2015-06-01 | 2015-10-21 | 电子科技大学 | Insulated gate bipolar transistor and manufacture method thereof |
| CN106252402A (en) * | 2016-11-04 | 2016-12-21 | 株洲中车时代电气股份有限公司 | A kind of trench gate IGBT and preparation method thereof |
| CN107910367A (en) * | 2017-11-13 | 2018-04-13 | 广东美的制冷设备有限公司 | Igbt and preparation method thereof, IPM modules and air conditioner |
| CN107910368A (en) * | 2017-11-13 | 2018-04-13 | 广东美的制冷设备有限公司 | Igbt and preparation method thereof, IPM modules and air conditioner |
| CN109671772A (en) * | 2018-12-17 | 2019-04-23 | 成都森未科技有限公司 | A kind of manufacturing method of power semiconductor and its collecting zone |
| CN114464676A (en) * | 2022-01-25 | 2022-05-10 | 上海擎茂微电子科技有限公司 | Reverse conducting IGBT |
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| US20010026984A1 (en) * | 2000-04-04 | 2001-10-04 | Yun Chong Man | Insulated gate bipolar transistor having high breakdown voltage in reverse blocking mode, and method for fabricating the same |
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| CN107910367A (en) * | 2017-11-13 | 2018-04-13 | 广东美的制冷设备有限公司 | Igbt and preparation method thereof, IPM modules and air conditioner |
| CN107910368A (en) * | 2017-11-13 | 2018-04-13 | 广东美的制冷设备有限公司 | Igbt and preparation method thereof, IPM modules and air conditioner |
| CN109671772A (en) * | 2018-12-17 | 2019-04-23 | 成都森未科技有限公司 | A kind of manufacturing method of power semiconductor and its collecting zone |
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