CN109671772A - A kind of manufacturing method of power semiconductor and its collecting zone - Google Patents
A kind of manufacturing method of power semiconductor and its collecting zone Download PDFInfo
- Publication number
- CN109671772A CN109671772A CN201811541418.8A CN201811541418A CN109671772A CN 109671772 A CN109671772 A CN 109671772A CN 201811541418 A CN201811541418 A CN 201811541418A CN 109671772 A CN109671772 A CN 109671772A
- Authority
- CN
- China
- Prior art keywords
- collecting zone
- boron
- type
- semiconductor substrate
- aluminium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 229910052796 boron Inorganic materials 0.000 claims abstract description 64
- 239000007924 injection Substances 0.000 claims abstract description 57
- 238000002347 injection Methods 0.000 claims abstract description 57
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 51
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 47
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 45
- 239000004411 aluminium Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000000137 annealing Methods 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims description 27
- 238000002513 implantation Methods 0.000 claims description 19
- 239000004020 conductor Substances 0.000 claims description 12
- 230000004913 activation Effects 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000005224 laser annealing Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 19
- 229910052751 metal Inorganic materials 0.000 description 18
- 239000002184 metal Substances 0.000 description 18
- -1 boron ion Chemical class 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 11
- 150000002500 ions Chemical class 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention relates to field of manufacturing semiconductor devices, more particularly to the manufacturing method of a kind of power semiconductor and its collecting zone, it includes semiconductor substrate or the semiconductor substrate with the N-type buffer layer for being formed in semiconductor-based back, first p-type collecting zone and the second p-type collecting zone, first p-type collecting zone injects to be formed by the boron to semiconductor substrate back, second p-type collecting zone is to inject to be formed by the aluminium to semiconductor substrate back, it is counted from the back side of semiconductor substrate, the peak position of aluminium injection is more shallow than the peak position that the boron injects, the peak concentration of aluminium injection is higher than the peak concentration that the boron injects.The present invention is injected by boron to form the first p-type collecting zone and aluminium injects to form the second p-type collecting zone, in the case where being no more than annealing region, collecting zone carrier concentration can be effectively increased, to promote the hole injection efficiency and drift region conductivity modulation effect of IGBT device, lower conduction voltage drop and on-state loss are realized.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, and in particular to the system of a kind of power semiconductor and its collecting zone
Make method.
Background technique
For bipolar semiconductor, such as diode or insulated gate bipolar transistor (IGBT, insulated
Gate Bipolar transistor) in, by the formation of back side p-type collecting zone, realize few sub- hole from collecting zone to drift
The injection in area can form electron-hole plasma in conjunction with the electron injection of device front N-shaped emitter region in drift region,
To generate conductivity modulation effect, the conducting resistance of device can be greatly lowered, to reduce device under on-state state
Loss.
In the manufacturing process of semiconductor devices, usually inject to form p-type current collection using boron at the back side of semiconductor substrate
Area.But in actual process sequence, when carrying out the back process of semiconductor substrate, front metal electrode has been made
At.In this case, if carrying out activation processing to boron injection zone by the way of thermal annealing, it is desirable that temperature must control
At 500 DEG C hereinafter, because positive metal electrode is possible to react with semiconductor substrate at 450 DEG C or more or Xiang Jiti
Middle diffusion seriously affects the performance of device.For this temperature limiting for the annealing activation after boron injection, activity ratio will very
Hardly possible improves.Because activation of the boron in silicon is greatly influenced by temperature, in 500 DEG C or less and 600 DEG C or more of most of temperature model
In enclosing, temperature is higher, and activity ratio is higher.Such as boron ion inject in a silicon substrate after annealing activation, when implantation dosage is
When 1E13 cm-2, if to reach 90% activity ratio, annealing temperature needs to reach 800 DEG C, this temperature for device just
Face electrode structure is clearly that cannot bear.And to maintain the temperature at 500 DEG C of annealing below, then the activity ratio of boron ion will
Can be very low, also mean that p-type collecting zone is unable to reach higher carrier concentration, this will directly affect the performance of device.
Therefore, the carrier concentration for how improving p-type collecting zone becomes the pass for improving bipolar semiconductor conductivity modulation effect
One of key element.
Have related application in the prior art such as: patent publication No. is the patent of invention of CN102110721A, is disclosed
A kind of method for manufacturing solar battery forms the back electric field with gradient concentration distribution doping, work using boron aluminium codoping process
The technique for making to take sintering to be spread on process, the back electric field of formation, surface boron doping is shallower, concentration is higher, aluminium doping is relatively deep,
Concentration is lower.
Summary of the invention
When injecting to form p-type collecting zone using boron, since the activity ratio of boron is limited by annealing temperature, activity ratio is difficult
It improves, therefore collecting zone is difficult to form sufficiently high carrier concentration, so that the hole injection efficiency of device collecting zone and drift
Area's conductivity modulation effect is restricted, and device is caused to cannot achieve lower on-state loss.Simultaneously as hole injection efficiency is not
Foot, also can the integrity problems such as short-circuit capacity to device impact, to solve the above problems, the application spy proposes a kind of half
Conductor device and its manufacturing method.
In order to realize the above technical effect, the technical solution of the application is as follows:
A kind of power semiconductor, it is characterised in that: including semiconductor substrate or with the n for being formed in semiconductor-based back
The semiconductor substrate of type buffer layer, the first p-type collecting zone and the second p-type collecting zone, the first p-type collecting zone is by half-and-half leading
The boron at the structure base board back side injects to be formed, and the second p-type collecting zone is to inject to be formed by the aluminium to semiconductor substrate back, from
The back side of semiconductor substrate is counted, and the peak position of the aluminium injection is more shallow than the peak position that the boron injects, the aluminium injection
Peak concentration it is higher than the peak concentration that the boron injects.
The power semiconductor is diode or insulated gate bipolar transistor.
A kind of manufacturing method of half-power conductor device collecting zone, characterized by the following steps:
Step 1, the boron ion injection at the back side is carried out in semiconductor substrate;
Step 2, the semiconductor substrate after boron ion injection is made annealing treatment, forms the first p-type collecting zone;
Step 3, the Al ion implantation at the back side is carried out in semiconductor substrate;
Step 4, the semiconductor substrate after Al ion implantation is made annealing treatment, forms the second p-type collecting zone.
The Implantation Energy of the boron of the first p-type collecting zone is 10KeV ~ 400KeV.
The implantation dosage of the boron of the first p-type collecting zone is 1E13cm-2~5E15 cm-2。
Implement the annealing activation after the boron injection by the thermal annealing or laser annealing that are less than or equal to 500 DEG C.
The Implantation Energy of the aluminium of the second p-type collecting zone is 10KeV ~ 300KeV.
The implantation dosage of the aluminium of the second p-type collecting zone is 5E12cm-2~5E15 cm-2。
Implement the annealing activation after the aluminium injection by the thermal annealing less than or equal to 500 DEG C.
The first p-type collecting zone and the second p-type collecting zone pass through a thermal annealing after boron injection and aluminium injection
Processing is formed simultaneously, can also the annealing formation in two times after injecting twice.
The advantages of the application are as follows:
The present invention is injected by boron to form the first p-type collecting zone and aluminium injects to form the second p-type collecting zone, is being no more than annealing temperature
Spend range in the case where, collecting zone carrier concentration can be effectively increased, thus promoted IGBT device hole injection efficiency and
Drift region conductivity modulation effect realizes lower conduction voltage drop and on-state loss.Meanwhile the first p-type current collection in manufacturing method
The formation process of area and the second p-type collecting zone is compatible, guarantees the simple controllable of device integral processing.
Detailed description of the invention
Fig. 1 is the sectional view (1) of the feature model process of power semiconductor collecting zone of the invention.
Fig. 2 is the sectional view (2) of the feature model process of power semiconductor collecting zone of the invention.
Fig. 3 is the sectional view (3) of the feature model process of power semiconductor collecting zone of the invention.
Fig. 4 is the sectional view (4) of the feature model process of power semiconductor collecting zone of the invention.
Fig. 5 is the sectional view (5) of the feature model process of power semiconductor collecting zone of the invention.
Fig. 6 is the sectional view (6) of the feature model process of power semiconductor collecting zone of the invention.
Fig. 7 is the sectional view (7) of the feature model process of power semiconductor collecting zone of the invention.
Fig. 8 is the sectional view (8) of the feature model process of power semiconductor collecting zone of the invention.
Fig. 9 is the sectional view (9) of the feature model process of power semiconductor collecting zone of the invention.
Figure 10 is the sectional view (10) of the feature model process of power semiconductor collecting zone of the invention.
Figure 11 is the sectional view (11) of the feature model process of power semiconductor collecting zone of the invention.
Figure 12 is the sectional view (12) of the feature model process of power semiconductor collecting zone of the invention.
Figure 13 is that the collecting zone of power semiconductor collecting zone of the invention is infused using boron and aluminium injection with only with boron
The carrier concentration profile comparison diagram entered.
Specific embodiment
Specific embodiments of the present invention will be described in further detail with reference to the accompanying drawing.
Embodiment 1
A kind of power semiconductor include semiconductor substrate or with the N-type buffer layer for being formed in semiconductor-based back half
Conductor substrate, the first p-type collecting zone and the second p-type collecting zone, the first p-type collecting zone pass through to semiconductor substrate back
Boron injects to be formed, and the second p-type collecting zone is to inject to be formed by the aluminium to semiconductor substrate back, from semiconductor substrate
The back side is counted, and the peak position of the aluminium injection is more shallow than the peak position that the boron injects, the peak concentration ratio of the aluminium injection
The peak concentration of the boron injection is high.The power semiconductor is diode or insulated gate bipolar transistor.Semiconductor
Substrate or semiconductor substrate with the N-type buffer layer for being formed in semiconductor-based back specifically belong to semiconductor substrate, and one
Kind of situation is the N-type buffer layer comprising the back side, and a kind of situation does not include, actually in order to which the manufacturing method of surface collecting zone can
It, can also be rear with before N-type buffer layer is formed.The present invention injects to form the first p-type collecting zone and aluminium injection shape by boron
Collecting zone carrier concentration can be effectively increased in the case where being no more than annealing region at the second p-type collecting zone, from
And the hole injection efficiency and drift region conductivity modulation effect of IGBT device are promoted, realize lower conduction voltage drop and on-state damage
Consumption.Meanwhile the formation process of the first p-type collecting zone and the second p-type collecting zone is compatible in manufacturing method, guarantees that device integrally adds
Work technique it is simple controllable.
Embodiment 2
A kind of manufacturing method of half-power conductor device collecting zone, characterized by the following steps:
Step 1, the boron ion injection at the back side is carried out in semiconductor substrate;
Step 2, the semiconductor substrate after boron ion injection is made annealing treatment, forms the first p-type collecting zone;
Step 3, the Al ion implantation at the back side is carried out in semiconductor substrate;
Step 4, the semiconductor substrate after Al ion implantation is made annealing treatment, forms the second p-type collecting zone.
The Implantation Energy of the boron of the first p-type collecting zone is 10KeV ~ 400KeV.
The implantation dosage of the boron of the first p-type collecting zone is 1E13cm-2~5E15 cm-2。
Implement the annealing activation after the boron injection by the thermal annealing or laser annealing that are less than or equal to 500 DEG C.
The Implantation Energy of the aluminium of the second p-type collecting zone is 10KeV ~ 300KeV.
The implantation dosage of the aluminium of the second p-type collecting zone is 5E12cm-2~5E15 cm-2。
Implement the annealing activation after the aluminium injection by the thermal annealing less than or equal to 500 DEG C.
The first p-type collecting zone and the second p-type collecting zone pass through a thermal annealing after boron injection and aluminium injection
Processing is formed simultaneously, can also the annealing formation in two times after injecting twice.
The present invention is injected by boron to form the first p-type collecting zone and aluminium injects to form the second p-type collecting zone, moves back being no more than
In the case where fiery temperature range, collecting zone carrier concentration can be effectively increased, to promote the hole injection effect of IGBT device
Rate and drift region conductivity modulation effect, realize lower conduction voltage drop and on-state loss.Meanwhile the first p-type in manufacturing method
The formation process of collecting zone and the second p-type collecting zone is compatible, guarantees the simple controllable of device integral processing.
Embodiment 3
Fig. 1 to Fig. 7 shows one embodiment of the present invention.As shown in Figure 1, semiconductor devices is IGBT, semiconductor substrate
Facad structure and N-shaped drift region 101 including device IGBT.The Facad structure of formation includes N-shaped emitter region 102, p-type base area
103, trench-gate 104, grid oxygen 105, insulating layer 106 and front metal electrode 107.The manufacturing method of back side collecting zone is this
Where the technical characteristic of invention.Specific step is as follows:
Step 1. is as shown in Fig. 2, carry out the ion implanting of the first p-type of back side collecting zone, using boron (B) injection.The note of boron ion
Entering energy is 10KeV ~ 400KeV, such as is set as 20KeV ~ 50KeV.The implantation dosage of boron ion is 1E13cm-2~5E15 cm-2, such as it is set as 1E13cm-2~2E15 cm-2。
Step 2. is as shown in figure 3, make annealing treatment the semiconductor substrate after boron ion injection, the first p-type collection of formation
Electric area 121.Because the positive metal electrode of device has been formed, metal reacts with semiconductor substrate under high temperature in order to prevent
Or spread into matrix, the temperature of annealing is less than or equal to 500 DEG C, and the carrier that p-type collecting zone is formed after laser annealing is dense
Degree peak value is 1E18cm-3~1E20cm-3。
Step 3. is as shown in figure 4, carry out the ion implanting of the second p-type of back side collecting zone, using aluminium (Al) injection.Aluminium from
The Implantation Energy of son is 10KeV ~ 300KeV, such as is set as 30KeV ~ 80KeV.Aluminum ions implantation dosage is 5E12cm-2~
5E15 cm-2, such as it is set as 1E14cm-2~1E15 cm-2。
Step 4. is as shown in figure 5, make annealing treatment the semiconductor substrate after Al ion implantation, the second p-type collection of formation
Electric area 122.Because the positive metal electrode of device has been formed, metal reacts with semiconductor substrate under high temperature in order to prevent
Or spread into matrix, the temperature of annealing is less than or equal to 500 DEG C, and the carrier that p-type collecting zone is formed after laser annealing is dense
Degree peak value is 1E19cm-3~1E21cm-3.It is counted from device backside surface, the peak position ratio of the second p-type collecting zone aluminium injection
The peak position of first p-type collecting zone boron injection is shallow, and the peak concentration of the second p-type collecting zone aluminium injection is than the first p-type collecting zone
The peak concentration of boron injection is high.
Step 5. is as shown in fig. 6, form the first p-type collecting zone 121 and the second p-type collecting zone in semiconductor-based back
After 122, the n+ buffer layer 110 between the first p-type collecting zone 121 and N-shaped drift region 101 is formed.
Step 6. carries out the production of back metal electrode, back metal is deposited by way of sputtering or evaporating, such as logical
It crosses sputtering and is sequentially depositing Al-Ti-Ni-Ag metal layer, form back metal electrode, complete the device manufacture of semiconductor devices, shape
At device architecture 100, as shown in Figure 7.
1 ~ step 4 of above-mentioned steps is feature technology scheme of the invention, in the present embodiment, for the shape of collecting zone
At, be respectively adopted boron injection and aluminium inject to form the first p-type collecting zone and the second p-type collecting zone, inject to form the 2nd p by aluminium
The carrier concentration of type collecting zone increase collecting zone.The collecting zone and buffer layer carrier concentration profile that are thusly-formed with only with
Boron inject to be formed p-type collecting zone carrier concentration schematic diagram it is as shown in figure 13, n+ buffer layer takes same process condition in figure,
Carrier concentration profile is almost the same, injects to form the first p-type collecting zone and the second p-type collecting zone when using boron injection and aluminium
When, because collecting zone is p-type doping, there is more holoe carrier injections drift region, obtains higher hole injection effect
Rate can be greatly lowered conduction voltage drop, make the conduction loss of device so that drift region be made to realize higher conductivity modulation effect
It is greatly lowered.
Embodiment 4
Fig. 1 to Fig. 8 shows one embodiment of the present invention.As shown in Figure 1, semiconductor devices is IGBT, semiconductor substrate
Facad structure, N-shaped drift region 101 and n+ buffer layer 110 including device IGBT.The Facad structure of formation includes N-shaped emitter region
102, p-type base area 103, trench-gate 104, grid oxygen 105, insulating layer 106 and front metal electrode 107.Back side collecting zone
Manufacturing method is technical characteristic place of the invention.Specific step is as follows:
Step 1. is as shown in figure 9, carry out the ion implanting of the first p-type of back side collecting zone, using boron (B) injection.The note of boron ion
Entering energy is 10KeV ~ 400KeV, such as is set as 50KeV ~ 80KeV.The implantation dosage of boron ion is 1E13cm-2~5E15 cm-2, such as it is set as 1E15cm-2~3E15 cm-2。
Step 2. as shown in Figure 10, carries out the ion implanting of the second p-type of back side collecting zone, is injected using aluminium (Al).Aluminium from
The Implantation Energy of son is 10KeV ~ 300KeV, such as is set as 80KeV ~ 120KeV.Aluminum ions implantation dosage is 5E12cm-2~
5E15 cm-2, such as it is set as 1E15cm-2~2E15 cm-2。
Step 3. as shown in figure 11, makes annealing treatment the semiconductor substrate after boron injection and Al ion implantation, simultaneously
Form the first p-type collecting zone 121 and the second p-type collecting zone 122.Because the positive metal electrode of device has been formed, in order to anti-
Only metal reacts with semiconductor substrate or spreads into matrix under high temperature, and the temperature of annealing is less than or equal to 500 DEG C, moves back
The carrier concentration peak value that the first p-type collecting zone is formed after fire is 1E18cm-3~1E20cm-3, the first p-type collection is formed after annealing
The carrier concentration peak value in electric area is 1E19cm-3~1E21cm-3.It is counted from device backside surface, the second p-type collecting zone aluminium note
The peak position entered is more shallow than the peak position that the first p-type collecting zone boron injects, the peak concentration ratio of the second p-type collecting zone aluminium injection
The peak concentration of first p-type collecting zone boron injection is high.
Step 4. carries out the production of back metal electrode, back metal is deposited by way of sputtering or evaporating, such as logical
It crosses sputtering and is sequentially depositing aluminium-Ti-Ni-Ag metal layer, form back metal electrode, complete the device manufacture of semiconductor devices, shape
At device architecture 100, as shown in figure 12.
1 ~ step 3 of above-mentioned steps is feature technology scheme of the invention, in the present embodiment, for the shape of collecting zone
At, be respectively adopted boron injection and aluminium inject to form the first p-type collecting zone and the second p-type collecting zone, inject to form the 2nd p by aluminium
The carrier concentration of type collecting zone increase collecting zone.The collecting zone and buffer layer carrier concentration profile that are thusly-formed with only with
Boron inject to be formed p-type collecting zone carrier concentration schematic diagram it is as shown in figure 13, n+ buffer layer takes same process condition in figure,
Carrier concentration profile is almost the same, injects to form the first p-type collecting zone and the second p-type collecting zone when using boron injection and aluminium
When, because collecting zone is p-type doping, there is more holoe carrier injections drift region, obtains higher hole injection effect
Rate can be greatly lowered conduction voltage drop, make the conduction loss of device so that drift region be made to realize higher conductivity modulation effect
It is greatly lowered.
Claims (10)
1. a kind of power semiconductor, it is characterised in that: including semiconductor substrate or have be formed in semiconductor-based back
N-type buffer layer semiconductor substrate, the first p-type collecting zone and the second p-type collecting zone, the first p-type collecting zone by pair
The boron of semiconductor-based back injects to be formed, and the second p-type collecting zone is to inject shape by the aluminium to semiconductor substrate back
At being counted from the back side of semiconductor substrate, the peak position of aluminium injection is more shallow than the peak position that the boron injects, the aluminium
The peak concentration of injection is higher than the peak concentration that the boron injects.
2. a kind of power semiconductor according to claim 1, it is characterised in that: the power semiconductor is two
Pole pipe or insulated gate bipolar transistor.
3. a kind of manufacturing method of half-power conductor device collecting zone, it is characterised in that:
Include the following steps:
Step 1, the boron ion injection at the back side is carried out in semiconductor substrate;
Step 2, the semiconductor substrate after boron ion injection is made annealing treatment, forms the first p-type collecting zone;
Step 3, the Al ion implantation at the back side is carried out in semiconductor substrate;
Step 4, the semiconductor substrate after Al ion implantation is made annealing treatment, forms the second p-type collecting zone.
4. the manufacturing method of according to claim 3 kind of half-power conductor device collecting zone, it is characterised in that: the first p-type
The Implantation Energy of the boron of collecting zone is 10KeV ~ 400KeV.
5. the manufacturing method of according to claim 3 kind of half-power conductor device collecting zone, it is characterised in that: described
The implantation dosage of the boron of one p-type collecting zone is 1E13cm-2~5E15 cm-2。
6. the manufacturing method of according to claim 3 kind of half-power conductor device collecting zone, it is characterised in that: by being less than
Or the annealing activation after the boron injection is implemented in thermal annealing equal to 500 DEG C or laser annealing.
7. the manufacturing method of according to claim 3 kind of half-power conductor device collecting zone, it is characterised in that: described second
The Implantation Energy of the aluminium of p-type collecting zone is 10KeV ~ 300KeV.
8. the manufacturing method of according to claim 3 kind of half-power conductor device collecting zone, it is characterised in that: described
The implantation dosage of the aluminium of two p-type collecting zones is 5E12cm-2~5E15 cm-2。
9. the manufacturing method of according to claim 3 kind of half-power conductor device collecting zone, it is characterised in that: by being less than
Or the thermal annealing equal to 500 DEG C implements the annealing activation after the aluminium injection.
10. the manufacturing method of according to claim 3 kind of half-power conductor device collecting zone, it is characterised in that: described
A thermal anneal process after one p-type collecting zone and the second p-type collecting zone are injected by boron injection and aluminium is formed simultaneously.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811541418.8A CN109671772A (en) | 2018-12-17 | 2018-12-17 | A kind of manufacturing method of power semiconductor and its collecting zone |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201811541418.8A CN109671772A (en) | 2018-12-17 | 2018-12-17 | A kind of manufacturing method of power semiconductor and its collecting zone |
Publications (1)
Publication Number | Publication Date |
---|---|
CN109671772A true CN109671772A (en) | 2019-04-23 |
Family
ID=66145132
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811541418.8A Pending CN109671772A (en) | 2018-12-17 | 2018-12-17 | A kind of manufacturing method of power semiconductor and its collecting zone |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN109671772A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111354788A (en) * | 2020-03-24 | 2020-06-30 | 成都森未科技有限公司 | Deep trench insulated gate device and preparation method thereof |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101640172A (en) * | 2009-08-19 | 2010-02-03 | 株洲南车时代电气股份有限公司 | Aluminum diffusing method |
US20120313139A1 (en) * | 2011-06-07 | 2012-12-13 | Renesas Electronics Corporation | Igbt and diode |
US20130161619A1 (en) * | 2011-12-22 | 2013-06-27 | Sumitomo Electric Industries, Ltd. | Semiconductor device and method for manufacturing same |
CN103515418A (en) * | 2013-10-08 | 2014-01-15 | 程德明 | High inverse-voltage punch through type GPP rectification chip and process |
CN103855206A (en) * | 2014-02-18 | 2014-06-11 | 宁波达新半导体有限公司 | Insulated gate bipolar transistor and manufacturing method thereof |
CN103915489A (en) * | 2014-04-01 | 2014-07-09 | 绍兴文理学院 | Insulated gate bipolar transistor |
US20150087125A1 (en) * | 2013-09-20 | 2015-03-26 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
CN108598180A (en) * | 2018-04-11 | 2018-09-28 | 浙江世菱电力电子有限公司 | A kind of rectifier diode and preparation method thereof |
-
2018
- 2018-12-17 CN CN201811541418.8A patent/CN109671772A/en active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101640172A (en) * | 2009-08-19 | 2010-02-03 | 株洲南车时代电气股份有限公司 | Aluminum diffusing method |
US20120313139A1 (en) * | 2011-06-07 | 2012-12-13 | Renesas Electronics Corporation | Igbt and diode |
US20130161619A1 (en) * | 2011-12-22 | 2013-06-27 | Sumitomo Electric Industries, Ltd. | Semiconductor device and method for manufacturing same |
US20150087125A1 (en) * | 2013-09-20 | 2015-03-26 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
CN103515418A (en) * | 2013-10-08 | 2014-01-15 | 程德明 | High inverse-voltage punch through type GPP rectification chip and process |
CN103855206A (en) * | 2014-02-18 | 2014-06-11 | 宁波达新半导体有限公司 | Insulated gate bipolar transistor and manufacturing method thereof |
CN103915489A (en) * | 2014-04-01 | 2014-07-09 | 绍兴文理学院 | Insulated gate bipolar transistor |
CN108598180A (en) * | 2018-04-11 | 2018-09-28 | 浙江世菱电力电子有限公司 | A kind of rectifier diode and preparation method thereof |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111354788A (en) * | 2020-03-24 | 2020-06-30 | 成都森未科技有限公司 | Deep trench insulated gate device and preparation method thereof |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101789375B (en) | Technique for manufacturing back of non-through insulated-gate bipolar transistor chip | |
CN102034707B (en) | Method for manufacturing IGBT | |
CN110504310B (en) | RET IGBT with self-bias PMOS and manufacturing method thereof | |
CN103618006A (en) | A fast recovery diode and a manufacturing method thereof | |
CN109065607A (en) | A kind of bipolar-type power semiconductor device and preparation method thereof | |
CN113571415B (en) | IGBT device and manufacturing method thereof | |
CN108122971A (en) | A kind of RC-IGBT devices and preparation method thereof | |
CN107305909A (en) | A kind of inverse conductivity type IGBT back structure and preparation method thereof | |
CN103855206A (en) | Insulated gate bipolar transistor and manufacturing method thereof | |
CN103050401B (en) | Back process method of IGBT (insulated gate bipolar transistor) device | |
CN106683989A (en) | Groove IGBT device and manufacturing method thereof | |
JP4031209B2 (en) | Semiconductor device | |
CN103872108B (en) | IGBT structure and preparation method thereof | |
CN109671772A (en) | A kind of manufacturing method of power semiconductor and its collecting zone | |
CN104716039B (en) | Improve the back process preparation method of IGBT performances | |
CN103839990A (en) | IGBT (insulated Gate Bipolar transistor) buffer layer structure and manufacturing method thereof | |
CN103489776B (en) | A kind of realize a processing method for cut-off type insulated gate bipolar transistor npn npn | |
CN109712887A (en) | A kind of manufacturing method of semiconductor devices collecting zone | |
CN109904225A (en) | A kind of high reliability IGBT and its manufacturing method | |
CN111415984B (en) | Manufacturing method of reverse conducting IGBT device | |
CN105206516A (en) | Method for forming field cut-off layer in semiconductor device | |
CN109712885A (en) | A kind of semiconductor devices buffering layer manufacturing method | |
CN210272367U (en) | Fast recovery diode structure based on three-dimensional semiconductor wafer | |
CN103579323B (en) | A kind of wide cellular insulated gate bipolar transistor | |
CN113206013A (en) | IGBT device with back buffer layer structure and preparation method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190423 |
|
RJ01 | Rejection of invention patent application after publication |