CN109712885A - A kind of semiconductor devices buffering layer manufacturing method - Google Patents
A kind of semiconductor devices buffering layer manufacturing method Download PDFInfo
- Publication number
- CN109712885A CN109712885A CN201811540959.9A CN201811540959A CN109712885A CN 109712885 A CN109712885 A CN 109712885A CN 201811540959 A CN201811540959 A CN 201811540959A CN 109712885 A CN109712885 A CN 109712885A
- Authority
- CN
- China
- Prior art keywords
- buffer layer
- type buffer
- implantation
- injection
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 230000003139 buffering effect Effects 0.000 title claims description 8
- 239000000872 buffer Substances 0.000 claims abstract description 156
- 238000002513 implantation Methods 0.000 claims abstract description 68
- 238000002347 injection Methods 0.000 claims abstract description 53
- 239000007924 injection Substances 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 43
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 39
- 239000011574 phosphorus Substances 0.000 claims abstract description 39
- 239000011669 selenium Substances 0.000 claims abstract description 37
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052711 selenium Inorganic materials 0.000 claims abstract description 36
- 238000000137 annealing Methods 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims description 25
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- 238000005224 laser annealing Methods 0.000 claims description 11
- 230000004913 activation Effects 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 description 14
- 239000002184 metal Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- -1 phosphonium ion Chemical class 0.000 description 3
- YZCKVEUIGOORGS-IGMARMGPSA-N Protium Chemical compound [1H] YZCKVEUIGOORGS-IGMARMGPSA-N 0.000 description 2
- 241000720974 Protium Species 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Abstract
The present invention relates to field of manufacturing semiconductor devices, layer manufacturing method is buffered more particularly to a kind of semiconductor devices, it includes semiconductor substrate, and first N-type buffer layer and the second N-type buffer layer, first N-type buffer layer is formed by the annealing after the selenium injection to semiconductor substrate back and injection, second N-type buffer layer is by carrying out H+implantation or phosphorus injection or the combination of H+implantation and phosphorus injection to semiconductor substrate back, it is made annealing treatment after injection, the present invention by semiconductor-based back using being capable of forming n-type doping and the higher selenium element of diffusion coefficient is injected and to form the first N-type buffer layer, it injects to form the second N-type buffer layer by the lesser H+implantation of atomic mass or common phosphorus, under conditions of the injection of opposite low energy ion, pass through the ion implanting of above two element and the work of annealing activation Skill combination, increases the depth of N-type buffer layer, optimizes the carrier concentration profile of N-type buffer layer and the device performance of FS-IGBT.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, and in particular to kind semiconductor devices buffers layer manufacturing method.
Background technique
In the semiconductor devices such as diode, insulated gate bipolar transistor (IGBT), in order to reduce thickness of detector and damage
Consumption, while guaranteeing the voltage endurance capability and switch performance of device, it needs to carry out deep place to semiconductor substrate from the back side of device
Doping, formed carrier concentration be higher than substrate buffer layer.According to Bai Song equation, field decay gradient and concentration of electric charges are at just
Than, therefore the buffer layer of higher concentration can make electric field decay rapidly and end in this layer, prevent depletion region from extending to device
Back surface and lead to break-through, therefore the buffer layer is also referred to as " field end (Field Stop) layer ", the IGBT with buffer layer
Referred to as FS-IGBT.
Back surface due to field cutoff layer apart from semiconductor devices has certain depth, and semiconductor devices is manufacturing
The process flow of Facad structure is usually first completed in the process, then carries out back process, therefore the formation of field cutoff layer should reach
The requirement of carrier concentration and depth, while the structure formed to front also to be avoided to have an impact.Currently, in semiconductor
The method of field cutoff layer is formed in device to be realized by ion injecting process and annealing operation.Using in semiconductor technology
Common donor element ion, such as phosphonium ion, or the special ion of n-type doping can be formed in silicon substrate, such as proton, from half
Conductor device back surface carries out ion implanting, then forms N-type buffer layer by activation of annealing.However, there are two sides for above-mentioned technology
Face is insufficient: 1. are limited to the diffusivity of atomic mass or ion in the semiconductors, for above-mentioned common doped chemical,
Form deeper N-type buffer layer and the optimization biggish carrier concentration profile in space, by need the high energy of 500KeV or more from
Sub- implanter, and the price is very expensive for high energy implanters, this will increase considerably device in the mass production of device
The manufacturing cost of part.2. if select lower-cost low energy ion beam implantation, only with phosphorus injection or H+implantation
In the case of, interface decline of the carrier concentration profile often in N-type buffer layer and N-shaped drift region is too fast, is formed very steep dense
Degree distribution, this is adversely affected to by performances such as the switching characteristics of device.Therefore, how relatively low Implantation Energy is used
(e.g., less than or equal to 400KeV) carries out ion implanting, obtains the deeper N-type buffer layer of depth, and dense by adjusting carrier
Degree distribution, the switching characteristic and reliability of optimised devices are the key that manufacture high performance device simultaneously and reduce cost.
Summary of the invention
Common phosphonium ion is carried out using the low energy ion injection technology of low cost or H+implantation forms semiconductor device
When the N-type buffer layer of part, it is often unable to get the deeper N-type buffer layer of depth and ideal carrier concentration profile, from
And the optimization of device performance and the promotion of reliability are limited, to solve the above problems, the application spy proposes a kind of semiconductor device
Part buffers layer manufacturing method.
In order to realize the above technical effect, the technical solution of the application is as follows:
A kind of semiconductor devices buffering layer manufacturing method, in semiconductor substrate, or with the p-type for being formed in semiconductor-based back
The back side of the semiconductor substrate of collecting zone forms the N-type buffer layer including the first N-type buffer layer and the second N-type buffer layer, described
First N-type buffer layer is formed by the annealing after the selenium injection to semiconductor substrate back and injection, second N-shaped
Buffer layer is by carrying out H+implantation or phosphorus injection or the combination of H+implantation and phosphorus injection to semiconductor substrate back, after injection
It is made annealing treatment, is counted from the back side of the semiconductor substrate, the depth of first N-type buffer layer is than second N-shaped
The depth of buffer layer is deep, and the peak concentration of first N-type buffer layer is more shallow than the peak concentration of second N-type buffer layer.
Further, it after the second N-type buffer layer is by carrying out H+implantation to semiconductor substrate back, carries out at thermal annealing
Reason.
Further, it after the second N-type buffer layer is by carrying out phosphorus injection to semiconductor substrate back, carries out at laser annealing
Reason.
The semiconductor devices is insulated gate bipolar transistor or diode.
The selenium Implantation Energy of first N-type buffer layer is less than or equal to 400KeV.
The selenium implantation dosage of first N-type buffer layer is less than or equal to the H+implantation agent of second N-type buffer layer
Amount.
The formation of first N-type buffer layer is less than or equal to 500 DEG C thermal anneal process after injecting by selenium is completed.
Laser annealing after the formation of first N-type buffer layer is injected by selenium handles completion.
The H+implantation of second N-type buffer layer is a H+implantation or multiple H+implantation.
The H+implantation energy of second N-type buffer layer is less than or equal to 400KeV.
The H+implantation dosage of second N-type buffer layer is 1E13cm-2~1E15cm-2。
The formation of second N-type buffer layer passes through 320 DEG C ~ 470 DEG C after H+implantation of thermal anneal process completion.
The phosphorus of second N-type buffer layer is injected to a phosphorus injection or repeatedly phosphorus injection.
The phosphorus Implantation Energy of second N-type buffer layer is less than or equal to 400KeV.
Laser annealing after the formation of second N-type buffer layer is injected by phosphorus handles completion.
The advantages of the application are as follows:
The present invention is capable of forming n-type doping and the higher selenium element injection shape of diffusion coefficient by using in semiconductor-based back
At the first N-type buffer layer, it is slow that the second N-shaped is formed by the lesser proton of atomic mass (protium) or common phosphorus injection injection
Layer is rushed, under conditions of the injection of opposite low energy ion, passes through the ion implanting of above two element and the technique of annealing activation
Combination, increases the depth of N-type buffer layer, optimizes the carrier concentration profile of N-type buffer layer and the device performance of FS-IGBT.
Detailed description of the invention
Fig. 1 is the sectional view (1) of the feature model process the present invention relates to semiconductor devices buffer layer.
Fig. 2 is the sectional view (2) of the feature model process the present invention relates to semiconductor devices buffer layer.
Fig. 3 is the sectional view (3) of the feature model process the present invention relates to semiconductor devices buffer layer.
Fig. 4 is the sectional view (4) of the feature model process the present invention relates to semiconductor devices buffer layer.
Fig. 5 is the sectional view (5) of the feature model process the present invention relates to semiconductor devices buffer layer.
Fig. 6 is the sectional view (6) of the feature model process the present invention relates to semiconductor devices buffer layer.
Fig. 7 is the sectional view (7) of the feature model process the present invention relates to semiconductor devices buffer layer.
Fig. 8 is the sectional view (8) of the feature model process the present invention relates to semiconductor devices buffer layer.
Fig. 9 is the sectional view (9) of the feature model process the present invention relates to semiconductor devices buffer layer.
Figure 10 is the carrier concentration profile figure that (a) is injected only with H+implantation or phosphorus.
Figure 11 is semiconductor devices buffer layer (b) of the invention using selenium and H+implantation or phosphorus injection carrier concentration point
Butut.
Specific embodiment
Specific embodiments of the present invention will be described in further detail with reference to the accompanying drawing.
Embodiment 1
A kind of semiconductor devices buffering layer manufacturing method, in semiconductor substrate, or with the p-type for being formed in semiconductor-based back
The back side of the semiconductor substrate of collecting zone forms the N-type buffer layer including the first N-type buffer layer and the second N-type buffer layer, described
First N-type buffer layer is formed by the annealing after the selenium injection to semiconductor substrate back and injection, second N-shaped
Buffer layer is made annealing treatment, from the semiconductor substrate by carrying out H+implantation to semiconductor substrate back after injection
The back side is counted, and the depth of first N-type buffer layer is deeper than the depth of second N-type buffer layer, first N-type buffer layer
Peak concentration it is more shallow than the peak concentration of second N-type buffer layer.The present invention can by using in semiconductor-based back
It forms n-type doping and the higher selenium element of diffusion coefficient is injected to form the first N-type buffer layer, pass through the lesser proton of atomic mass
(protium) injection forms the second N-type buffer layer, under conditions of the injection of opposite low energy ion, passes through above two element
The process combination of ion implanting and annealing activation, increases the depth of N-type buffer layer, optimizes the carrier concentration point of N-type buffer layer
The device performance of cloth and FS-IGBT.
Embodiment 2
Semiconductor devices buffers layer manufacturing method, in semiconductor substrate, or with the p-type current collection for being formed in semiconductor-based back
The back side of the semiconductor substrate in area, N-type buffer layer of the formation including the first N-type buffer layer and the second N-type buffer layer, described first
N-type buffer layer is formed by the annealing after the selenium injection to semiconductor substrate back and injection, the second N-shaped buffering
Layer is carried out after injection by carrying out H+implantation or phosphorus injection or the combination of H+implantation and phosphorus injection to semiconductor substrate back
Annealing, is counted, the depth of first N-type buffer layer is buffered than second N-shaped from the back side of the semiconductor substrate
The depth of layer is deep, and the peak concentration of first N-type buffer layer is more shallow than the peak concentration of second N-type buffer layer.
Further, it after the second N-type buffer layer is by carrying out H+implantation to semiconductor substrate back, carries out at thermal annealing
Reason.
The semiconductor devices is insulated gate bipolar transistor or diode.
The selenium Implantation Energy of first N-type buffer layer is less than or equal to 400KeV.
The selenium implantation dosage of first N-type buffer layer is less than or equal to the H+implantation agent of second N-type buffer layer
Amount.
The formation of first N-type buffer layer is less than or equal to 500 DEG C thermal anneal process after injecting by selenium is completed.
Laser annealing after the formation of first N-type buffer layer is injected by selenium handles completion.
The H+implantation of second N-type buffer layer is a H+implantation or multiple H+implantation.
The H+implantation energy of second N-type buffer layer is less than or equal to 400KeV.
The H+implantation dosage of second N-type buffer layer is 1E13cm-2~1E15cm-2。
The formation of second N-type buffer layer passes through 320 DEG C ~ 470 DEG C after H+implantation of thermal anneal process completion.
Embodiment 3
Semiconductor devices buffers layer manufacturing method, in semiconductor substrate, or with the p-type current collection for being formed in semiconductor-based back
The back side of the semiconductor substrate in area, N-type buffer layer of the formation including the first N-type buffer layer and the second N-type buffer layer, described first
N-type buffer layer is formed by the annealing after the selenium injection to semiconductor substrate back and injection, the second N-shaped buffering
Layer is carried out after injection by carrying out H+implantation or phosphorus injection or the combination of H+implantation and phosphorus injection to semiconductor substrate back
Annealing, is counted, the depth of first N-type buffer layer is buffered than second N-shaped from the back side of the semiconductor substrate
The depth of layer is deep, and the peak concentration of first N-type buffer layer is more shallow than the peak concentration of second N-type buffer layer.
Further, it after the second N-type buffer layer is by carrying out phosphorus injection to semiconductor substrate back, carries out at laser annealing
Reason.
The semiconductor devices is insulated gate bipolar transistor or diode.
The selenium Implantation Energy of first N-type buffer layer is less than or equal to 400KeV.
The selenium implantation dosage of first N-type buffer layer is less than or equal to the H+implantation agent of second N-type buffer layer
Amount.
The formation of first N-type buffer layer is less than or equal to 500 DEG C thermal anneal process after injecting by selenium is completed.
Laser annealing after the formation of first N-type buffer layer is injected by selenium handles completion.
The phosphorus of second N-type buffer layer is injected to a phosphorus injection or repeatedly phosphorus injection.
The phosphorus Implantation Energy of second N-type buffer layer is less than or equal to 400KeV.
Laser annealing after the formation of second N-type buffer layer is injected by phosphorus handles completion.
Embodiment 4
As shown in Figure 1, semiconductor devices is IGBT, semiconductor substrate includes Facad structure and the N-shaped drift region of device IGBT
101.The Facad structure of formation include N-shaped emitter region 102, p-type base area 103, trench-gate 104, grid oxygen 105, insulating layer 106 with
And front metal electrode 107.The manufacturing method of back side N-type buffer layer is technical characteristic place of the invention.Specific step is as follows:
Step 1. is as shown in Fig. 2, carry out the ion implanting of the first N-type buffer layer of the back side, using selenium (Se) injection.Plasma selenium
Implantation Energy is such as to be set as 80KeV ~ 300KeV less than or equal to 400KeV.The implantation dosage of plasma selenium is less than or equal to
The H+implantation dosage of second N-type buffer layer.
For step 2. as shown in figure 3, making annealing treatment to the semiconductor substrate after plasma selenium injection, the first N-shaped of formation is slow
Rush layer.Because the positive metal electrode of device has been formed, in order to prevent under high temperature metal and semiconductor substrate react or
It is spread into matrix, the temperature of annealing is less than or equal to 500 DEG C, or is handled using laser annealing.
1 ~ step 2 through the above steps forms the first N-type buffer layer 121 at the device back side.
Step 3. is as shown in figure 4, carry out the ion implanting of the second N-type buffer layer of the back side, first using phosphorus injection.Proton
Implantation Energy be less than or equal to 400KeV, such as be set as 300KeV ~ 400KeV.The implantation dosage of phosphorus is 1E12cm-2~5E14
cm-2, such as it is set as 5E12cm-2~5E13 cm-2。
Step 4. is as shown in figure 5, carry out laser annealing processing to the semiconductor substrate after phosphorus injection.
Step 5. is as shown in fig. 6, carry out the ion implanting of the second N-type buffer layer of the back side, using H+implantation.Proton
Implantation Energy is less than or equal to 400KeV, such as is set as 120KeV ~ 350KeV.The implantation dosage of proton is 1E13cm-2~1E15
cm-2, such as it is set as 5E13cm-2~5E14 cm-2。
Step 6. is as shown in fig. 7, make annealing treatment the semiconductor substrate after H+implantation, the temperature of annealing
It is 320 DEG C ~ 470 DEG C, such as is set as 350 DEG C ~ 390 DEG C.
3 ~ step 6 through the above steps forms the second N-type buffer layer 122 at the device back side.
It is counted from device backside surface, the peak position of the second N-type buffer layer H+implantation is infused than the first N-type buffer layer selenium
The peak position entered is shallow, and the peak concentration of the second N-type buffer layer H+implantation is than the peak concentration that the first N-type buffer layer selenium injects
It is high.
Step 7. is as shown in figure 8, form the first N-type buffer layer 121 and the second N-type buffer layer in semiconductor-based back
After 122, the p+ collecting zone 130 for being located at semiconductor substrate backside surface is formed.
Step 8. carries out the production of back metal electrode, back metal is deposited by way of sputtering or evaporating, such as logical
It crosses sputtering and is sequentially depositing Al-Ti-Ni-Ag metal layer, form back metal electrode 108, complete the device manufacture of semiconductor devices,
Device architecture 100 is formed, as shown in Figure 9.
1 ~ step 6 of above-mentioned steps is feature technology scheme of the invention, in the present embodiment, for the shape of buffer layer
At selenium be respectively adopted injecting and to form the first N-type buffer layer, form the second N-shaped using the combination that H+implantation and phosphorus inject
Buffer layer is injected the depth for increasing N-type buffer layer by selenium, and optimizes carrier concentration profile, so that N-type buffer layer is close
The attachment carrier concentration profile of N-shaped drift region is gentler, is conducive to the switch performance of optimised devices and promotes reliability.It adopts
It the N-type buffer layer carrier concentration profile that is formed in aforementioned manners and injects to form N-type buffer layer only with H+implantation and phosphorus
Carrier concentration schematic diagram as shown in figs. 10-11, in figure the H+implantation of the 2nd n+ buffer layer and phosphorus injection take identical work
Skill condition, being capable of shape since diffusion coefficient of the selenium in silicon is larger when injecting to form the first N-type buffer layer using selenium
At deeper second N-type buffer layer of depth, and optimize carrier concentration profile, the attachment carrier concentration close to N-shaped drift region
Distribution is gentler, is conducive to the switch performance of optimised devices, and promote the reliability of device.
Claims (8)
1. a kind of semiconductor devices buffers layer manufacturing method, it is characterised in that: in semiconductor substrate or have and be formed in semiconductor
The semiconductor-based back of the p-type collecting zone of substrate back forms the N-shaped including the first N-type buffer layer and the second N-type buffer layer
Buffer layer, first N-type buffer layer are formed by the annealing after the selenium injection to semiconductor substrate back and injection,
Second N-type buffer layer by semiconductor substrate back carry out H+implantation or phosphorus injection or H+implantation and phosphorus injection
Combination, is made annealing treatment after injection, is counted from the back side of the semiconductor substrate, the depth ratio of first N-type buffer layer
The depth of second N-type buffer layer is deep, the peak of the peak concentration of first N-type buffer layer than second N-type buffer layer
It is shallow to be worth concentration.
2. a kind of semiconductor devices according to claim 1 buffers layer manufacturing method, it is characterised in that: the second N-shaped buffering
After layer is by carrying out H+implantation to semiconductor substrate back, thermal anneal process is carried out.
3. a kind of semiconductor devices according to claim 1 buffers layer manufacturing method, it is characterised in that: the second N-shaped buffering
After layer is by carrying out phosphorus injection to semiconductor substrate back, laser annealing processing is carried out.
4. a kind of semiconductor devices according to claim 1 buffers layer manufacturing method, it is characterised in that: first N-shaped
The selenium Implantation Energy of buffer layer is less than or equal to 400KeV；The selenium implantation dosage of first N-type buffer layer is less than or equal to institute
State the H+implantation dosage of the second N-type buffer layer；The formation of first N-type buffer layer is less than or equal to after being injected by selenium
500 DEG C of thermal anneal process is completed；Laser annealing after the formation of first N-type buffer layer is injected by selenium handles completion.
5. a kind of semiconductor devices according to claim 1 buffers layer manufacturing method, it is characterised in that: second N-shaped
The H+implantation of buffer layer is a H+implantation or multiple H+implantation.
6. a kind of semiconductor devices according to claim 1 buffers layer manufacturing method, it is characterised in that: second N-shaped
The H+implantation energy of buffer layer is less than or equal to 400KeV；The H+implantation dosage of second N-type buffer layer is 1E13cm-2
~1E15cm-2；The formation of second N-type buffer layer passes through 320 DEG C ~ 470 DEG C after H+implantation of thermal anneal process completion.
7. a kind of semiconductor devices according to claim 1 buffers layer manufacturing method, it is characterised in that: second N-shaped
The phosphorus of buffer layer is injected to a phosphorus injection or repeatedly phosphorus injection.
8. a kind of semiconductor devices according to claim 1 buffers layer manufacturing method, it is characterised in that: second N-shaped
The phosphorus Implantation Energy of buffer layer is less than or equal to 400KeV；The formation of second N-type buffer layer passes through the laser after phosphorus injection
Annealing is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811540959.9A CN109712885A (en) | 2018-12-17 | 2018-12-17 | A kind of semiconductor devices buffering layer manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811540959.9A CN109712885A (en) | 2018-12-17 | 2018-12-17 | A kind of semiconductor devices buffering layer manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109712885A true CN109712885A (en) | 2019-05-03 |
Family
ID=66256776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811540959.9A Pending CN109712885A (en) | 2018-12-17 | 2018-12-17 | A kind of semiconductor devices buffering layer manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109712885A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111370473A (en) * | 2020-03-24 | 2020-07-03 | 成都森未科技有限公司 | Groove type device and preparation method thereof |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002261282A (en) * | 2001-02-28 | 2002-09-13 | Toshiba Corp | Semiconductor device and its manufacturing method |
| US20080054369A1 (en) * | 2006-08-31 | 2008-03-06 | Infineon Technologies | Semiconductor device with a field stop zone and process of producing the same |
| US20090184340A1 (en) * | 2008-01-23 | 2009-07-23 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device and method of producing the same |
| CN102737967A (en) * | 2011-03-30 | 2012-10-17 | 英飞凌科技股份有限公司 | Semiconductor device and substrate with chalcogen doped region |
| CN103199018A (en) * | 2012-01-06 | 2013-07-10 | 上海华虹Nec电子有限公司 | Manufacturing method of field blocking type semiconductor device and device structure |
| CN103489776A (en) * | 2013-09-18 | 2014-01-01 | 中国东方电气集团有限公司 | Method for achieving process of field-stop type insulated gate bipolar transistor |
| CN104620391A (en) * | 2012-10-23 | 2015-05-13 | 富士电机株式会社 | Semiconductor device and method for manufacturing same |
| CN105206516A (en) * | 2015-08-21 | 2015-12-30 | 中国东方电气集团有限公司 | Method for forming field cut-off layer in semiconductor device |
| CN105609419A (en) * | 2016-02-25 | 2016-05-25 | 杭州士兰集成电路有限公司 | Semiconductor device and manufacturing method thereof |
| CN105793991A (en) * | 2014-06-12 | 2016-07-20 | 富士电机株式会社 | Semiconductor device |
| CN106128946A (en) * | 2011-05-18 | 2016-11-16 | 富士电机株式会社 | Semiconductor device and the manufacture method of semiconductor device |
-
2018
- 2018-12-17 CN CN201811540959.9A patent/CN109712885A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002261282A (en) * | 2001-02-28 | 2002-09-13 | Toshiba Corp | Semiconductor device and its manufacturing method |
| US20080054369A1 (en) * | 2006-08-31 | 2008-03-06 | Infineon Technologies | Semiconductor device with a field stop zone and process of producing the same |
| US20090184340A1 (en) * | 2008-01-23 | 2009-07-23 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device and method of producing the same |
| CN102737967A (en) * | 2011-03-30 | 2012-10-17 | 英飞凌科技股份有限公司 | Semiconductor device and substrate with chalcogen doped region |
| CN106128946A (en) * | 2011-05-18 | 2016-11-16 | 富士电机株式会社 | Semiconductor device and the manufacture method of semiconductor device |
| CN103199018A (en) * | 2012-01-06 | 2013-07-10 | 上海华虹Nec电子有限公司 | Manufacturing method of field blocking type semiconductor device and device structure |
| CN104620391A (en) * | 2012-10-23 | 2015-05-13 | 富士电机株式会社 | Semiconductor device and method for manufacturing same |
| CN103489776A (en) * | 2013-09-18 | 2014-01-01 | 中国东方电气集团有限公司 | Method for achieving process of field-stop type insulated gate bipolar transistor |
| CN105793991A (en) * | 2014-06-12 | 2016-07-20 | 富士电机株式会社 | Semiconductor device |
| CN105206516A (en) * | 2015-08-21 | 2015-12-30 | 中国东方电气集团有限公司 | Method for forming field cut-off layer in semiconductor device |
| CN105609419A (en) * | 2016-02-25 | 2016-05-25 | 杭州士兰集成电路有限公司 | Semiconductor device and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111370473A (en) * | 2020-03-24 | 2020-07-03 | 成都森未科技有限公司 | Groove type device and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4128777B2 (en) | Insulated gate bipolar transistor (IGBT) and manufacturing method thereof | |
| CN105185825A (en) | Injection Control In Semiconductor Power Devices | |
| CN108122971A (en) | A kind of RC-IGBT devices and preparation method thereof | |
| CN110459598A (en) | A kind of superjunction MOS type power semiconductor and preparation method thereof | |
| CN104332495A (en) | Insulated-gate bipolar transistor and manufacturing method thereof | |
| CN102916042A (en) | Reverse IGBT (insulated gate bipolar transistor) device structure and manufacturing method therefor | |
| CN110429077B (en) | Single-particle burnout resistant structure suitable for power semiconductor device | |
| CN109461768A (en) | A kind of SiC junction barrel Schottky diode and its manufacturing method | |
| CN107305909A (en) | A kind of inverse conductivity type IGBT back structure and preparation method thereof | |
| CN103560086B (en) | The preparation method of the super-junction semiconductor device of avalanche capacity can be improved | |
| CN103681817B (en) | IGBT device and preparation method thereof | |
| CN103872108B (en) | A kind of IGBT structure and preparation method thereof | |
| CN109712885A (en) | A kind of semiconductor devices buffering layer manufacturing method | |
| CN105206516B (en) | A kind of method for forming field cutoff layer in the semiconductor device | |
| CN103489776B (en) | A kind of realize a processing method for cut-off type insulated gate bipolar transistor npn npn | |
| CN103943671A (en) | Power semiconductor device and forming method thereof | |
| CN104716039B (en) | Improve the back process preparation method of IGBT performances | |
| CN113964197B (en) | IGBT device with low leakage current and preparation method thereof | |
| CN205282480U (en) | FS type IGBT device with double buffering layer | |
| CN103165443B (en) | A kind of gated transistor device and method of manufacturing technology thereof | |
| CN111415984B (en) | Manufacturing method of reverse conducting IGBT device | |
| CN113206013A (en) | IGBT device with back buffer layer structure and preparation method thereof | |
| CN109671772A (en) | A kind of manufacturing method of power semiconductor and its collecting zone | |
| CN103855204B (en) | Inverse conductivity type IGBT collector structure and preparation method thereof | |
| CN102931228B (en) | Reverse conducting IGBT (Insulated Gate Bipolar Translator) device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190503 |