CN205282480U

CN205282480U - FS type IGBT device with double buffering layer

Info

Publication number: CN205282480U
Application number: CN201520871004.7U
Authority: CN
Inventors: 汤艺; 徐泓; 王良元; 永福
Original assignee: Shanghai Daozhi Technology Co Ltd
Current assignee: Shanghai Daozhi Technology Co Ltd
Priority date: 2015-11-04
Filing date: 2015-11-04
Publication date: 2016-06-01
Anticipated expiration: 2025-11-04

Abstract

The utility model provides a FS type IGBT device with double buffering layer, includes collecting electrode 1, second buffer layer 2, first buffer layer 3, N - drift region 4, N+ charge storage layer 5, P type trap 6, N type source region 7, projecting pole 8 and grid 9, first buffer layer with second buffer layer 2 is parallel to each other, is located 4 draws of N - drift region between the collecting electrode 1, just first buffer layer 3 is close to N - drift region 4, and second buffer layer 2 is close to collecting electrode 1, and the biggest concentration of impurity of first layer buffer layer 3 is less than the biggest concentration of impurity of second buffer layer 2, it has can reduce on -state voltage, improves the switching characteristic, thereby strengthen the electricity performance of IGBT device effectively.

Description

A kind of FS type IGBT device with double-buffering layer

Technical field

The utility model relates to field of semiconductor manufacture, particularly relates to a kind of FS type IGBT device with double-buffering layer.

Background technology

The making structure of IGBT popular at present mainly contains non-punch (NPT) IGBT structure and field termination type FSIGBT structure etc., the former is symmetrical IGBT structure, forward blocking voltage is all born by N-type drift region, therefore N-type drift region is thicker, it is thicker to be embodied on chip thickness, forward conduction voltage is relatively big, and switching speed is slower; The latter is asymmetric IGBT structure, has one layer of N-type buffer layer, on the spot stop layer, and forward conduction voltage is less, and forward blocking voltage is supported by N-type drift region and N-type buffer zone.

Summary of the invention

In order to reduce device conduction loss, the switch characteristic of optimised devices, it is necessary to optimised devices structure realizes further. The utility model patent has set forth a kind of FS type IGBT device with double-buffering layer, and it comprises collector electrode, the 2nd buffer layer, the first buffer layer, N-drift region, N+ charge storage layer, P type trap, N-type source region, emtting electrode and grid; Described first buffer layer and described 2nd buffer layer are parallel to each other, between described N-drift region and described collector electrode, and first buffer layer near N-drift region, the 2nd buffer layer is less than the impurity peak concentration of the 2nd buffer layer near collector electrode, the impurity peak concentration of the first layer buffer layer.

Described the first layer buffer layer is formed from silicon chip back side by the donor impurity hydrogen ion that ion implantation atomic mass is lighter, adopts low-temperature annealing;

Described second layer buffer layer is formed from silicon chip back side by ion implantation N-type phosphonium ion, adopts laser annealing.

A kind of FS type IGBT device with double-buffering layer described in the utility model is applicable to the IGBT device of trench gate and planar gate.

A kind of by forming two layers of N-type buffer layer being parallel to each other between N-drift region and collector electrode as field stop layer in the method for IGBT silicon chip back side twice doped type N impurity, wherein the first buffer layer is used for the switch characteristic of optimised devices, 2nd buffer layer is used for the electric field terminated under forward blocking pattern, adjustment back side injection efficiency, suppresses the further diffusion of collector electrode P+ impurity.

The forming process of two buffer layer first uses the mode of hydrogen ion ion implantation from the dark dopant implant of silicon chip back side and low-temperature annealing, forms the first layer buffer layer between N-drift region and collector electrode; Re-use phosphonium ion from chip back doping also laser annealing in the way of ion implantation, formation second layer buffer layer; Wherein the impurity peak concentration of the first buffer layer is less than the impurity peak concentration of the 2nd buffer layer. The degree of depth that can reach due to laser annealing is subject to the characteristic restriction of instrument, often can not utilize the buffer layer of laser annealing formation deep layer itself; Although and hydrogen ion can form dark buffer layer, but the peak concentration that can reach receives again the restriction of activity ratio, so utilizing double-layer bumper layer in conjunction with the superiority of two kinds of buffer layers, the electrology characteristic of Static and dynamic can well be optimized respectively.

Accompanying drawing explanation

Fig. 1 is the FS type trench gate IGBT structure figure with double-layer bumper layer.

Fig. 2 is the FS type planar gate IGBT structure figure with double-layer bumper layer.

Fig. 3 is the FS type IGBT silicon chip back side Impurity Distribution schematic diagram with double-layer bumper layer.

Embodiment:

IGBT device making method of the present utility model and other conventional IGBT device manufacturing process are compatible, but add and formed two layers of N-type buffer layer being parallel to each other by the mode of ion implantation from silicon chip back side doping before backside collector is formed. As shown in Figure 1 or 2, a kind of double-layer bumper layer FS type trench gate (or planar gate) IGBT, comprises collector electrode 1, the 2nd buffer layer 2, first buffer layer 3, N-drift region 4, N+ charge storage layer 5, P type trap 6, N-type source region 7, emtting electrode 8 and grid 9 from top to bottom. Wherein the first buffer layer and described 2nd buffer layer 2 are parallel to each other, between N-drift region 4 and collector electrode 1, and the first buffer layer 3 near N-drift region the 4, two buffer layer 2 near collector electrode 1. The impurity peak concentration of the first layer buffer layer 3 is less than the impurity peak concentration of the 2nd buffer layer 2.

Specific embodiment 1: make double-layer bumper layer FS type trench gate IGBT.

A. the N-type wafer sheet of regulation resistance is prepared; B. adopting selective oxidation (LOCOS) or field oxide to do isolation technology, be manufactured with source region c. photoetching P-ring figure, implanting p-type impurity forms P-ring, then N-type impurity ion implantation, is formed with source region N-type charge storage layer; D. photoetching groove figure, dry etching silicon substrate, growth grid oxic horizon, the polycrystalline silicon material filling groove that deposit is in-situ doped; E. photoetching gate patterns, etch polysilicon forms the grid of top layer MOS structure; F. implanting p-type impurity, forms P-channel; G. N-type impurity is injected in photoetching N-type source region; H. the insulating material such as deposited oxide layer or silicon nitride densification of annealing, lithography contact hole, the p-well region of all unit born of the same parents that etching insulation layer is formed before exposing and N-type source region silicon face, implanting p-type impurity; I. deposited top layer metal, chemical wet etching top-level metallic, deposit passivation layer, chemical wet etching passivation layer, final alloy completes the making of top level structure; J. silicon chip back side is thinned to specific thickness, and back side ion implantation hydrogen ion, forms the first buffer layer, low-temperature annealing; K. N-type impurity phosphorus is injected at the back side, forms the 2nd buffer layer, surface laser anneal; L. inject P+ ion at silicon chip back side and form collector electrode, carry out low-temperature annealing or surface laser annealing; M. back side depositing metal completes the making processes of whole IGBT device.

Specific embodiment 2: make double-layer bumper layer FS type planar gate IGBT.

A. the N-type wafer sheet of regulation resistance is prepared; B. adopt selective oxidation (LOCOS) or field oxide to do isolation technology, it is manufactured with source region; C. photoetching P-ring figure, implanting p-type impurity forms P-ring, then N-type impurity ion implantation, is formed with source region N-type charge storage layer; D. grid oxic horizon is grown in surface of silicon, the polycrystalline silicon material that deposit is in-situ doped; E. photoetching gate patterns, etch polysilicon forms the grid of top layer MOS structure; F. implanting p-type impurity, forms P-channel; G. N-type impurity is injected in photoetching N-type source region; H. the insulating material such as deposited oxide layer or silicon nitride densification of annealing, lithography contact hole, implanting p-type impurity; I. deposited top layer metal, chemical wet etching top-level metallic, deposit passivation layer, chemical wet etching passivation layer, final alloy completes the making of top level structure; J. silicon chip back side is thinned to specific thickness, and back side ion implantation hydrogen ion, forms the first buffer layer, low-temperature annealing; K. the back side is injected or High temperature diffusion N-type impurity phosphorus, forms the 2nd buffer layer, surface laser anneal; L. inject P+ ion at silicon chip back side and form collector electrode, carry out low-temperature annealing or surface laser annealing; M. back side depositing metal completes the making processes of whole IGBT device.

Above the utility model is explained in detail, can not think that protection domain of the present utility model is only confined to above-mentioned enforcement mode. If not producing difference in essence with the technical scheme of the utility model claim, the deduction or replace of above-mentioned enforcement mode are still regarded as within protection domain of the present utility model.

Claims

1. a FS type IGBT device with double-buffering layer, comprises collector electrode (1), the 2nd buffer layer (2), the first buffer layer (3), N-drift region (4), N+ charge storage layer (5), P type trap (6), N-type source region (7), emtting electrode (8) and grid (9);

It is characterized in that: described first buffer layer and described 2nd buffer layer (2) are parallel to each other, it is positioned between described N-drift region (4) and described collector electrode (1), and first buffer layer (3) near N-drift region (4), 2nd buffer layer (2) is near collector electrode (1), and the impurity peak concentration of the first layer buffer layer (3) is less than the impurity peak concentration of the 2nd buffer layer (2).

2. a kind of FS type IGBT device with double-buffering layer according to claim 1, it is characterised in that the first layer buffer layer (3) is formed from silicon chip back side (10) by the donor impurity hydrogen ion that ion implantation atomic mass is lighter, adopts low-temperature annealing.

3. a kind of FS type IGBT device with double-buffering layer according to claim 1, it is characterised in that second layer buffer layer (2) is formed from silicon chip back side (10) by ion implantation N-type phosphonium ion, adopts laser annealing.

4. a kind of FS type IGBT device with double-buffering layer according to claim 1, it is characterised in that be applicable to the IGBT device of trench gate and planar gate.