CN103855204B - Inverse conductivity type IGBT collector structure and preparation method thereof - Google Patents
Inverse conductivity type IGBT collector structure and preparation method thereof Download PDFInfo
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- CN103855204B CN103855204B CN201210524694.XA CN201210524694A CN103855204B CN 103855204 B CN103855204 B CN 103855204B CN 201210524694 A CN201210524694 A CN 201210524694A CN 103855204 B CN103855204 B CN 103855204B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 20
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 256
- 230000007547 defect Effects 0.000 claims abstract description 112
- 239000012535 impurity Substances 0.000 claims abstract description 45
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 34
- 229910052710 silicon Inorganic materials 0.000 claims description 34
- 239000010703 silicon Substances 0.000 claims description 34
- 238000002347 injection Methods 0.000 claims description 20
- 239000007924 injection Substances 0.000 claims description 20
- 238000000137 annealing Methods 0.000 claims description 16
- 238000001259 photo etching Methods 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 6
- 238000001465 metallisation Methods 0.000 claims description 5
- 230000003139 buffering effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 13
- 239000000463 material Substances 0.000 abstract description 9
- 239000002210 silicon-based material Substances 0.000 abstract description 6
- 230000004913 activation Effects 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract description 3
- VGRFVJMYCCLWPQ-UHFFFAOYSA-N germanium Chemical compound [Ge].[Ge] VGRFVJMYCCLWPQ-UHFFFAOYSA-N 0.000 description 147
- 150000002500 ions Chemical class 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 6
- 238000013461 design Methods 0.000 description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000001376 precipitating effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention discloses a kind of inverse conductivity type IGBT collector structure, including：Base, N‑Germanium defect layer, P+Germanium collector area, N+Germanium shorting region and collector electrode metal layer；The N‑Germanium defect layer is arranged on base bottom surface；The P+Germanium collector area and N+Germanium shorting region is disposed in parallel in the N‑Between germanium defect layer bottom surface and the collector electrode metal layer.The invention also discloses a kind of preparation method of inverse conductivity type IGBT collector structure.A kind of inverse conductivity type IGBT provided by the invention collector structure and preparation method thereof, collector emitter voltage when rebound phenomenon occurs, emitter current density can be greatly reduced by doing inverse conductivity type IGBT backside collectors using germanium material or germanium silicon material, so as to inhibit the rebound phenomenon of device, higher impurity activation rate can also be obtained at low temperature, the ion implantation process of costliness is avoided that, reduces conducting voltage and turn-off time.
Description
Technical field
The present invention relates to power semiconductor device technology field, the more particularly to collector structure and its system against conductivity type IGBT
Preparation Method.
Background technology
It is positive technique first in the IGBT preparation technologies of routine, including oxidation, ion implanting, exposure, deposit and quarter
Erosion etc. forms positive PN junction, gate electrode and emitter pattern.Followed by the reduction process at the back side.According to device structure and should
The difference of voltage class, the thickness after being finally thinned are also different.For punch (also known as electric field blocking-up type)
Device, N-type ion implanting (such as P ion) and anneal to form one layer of N first after thinning+Cushion.Followed by p-type from
Son, which injects (such as B ions) and annealed, forms collector layer.Do not have to then form N for non-punch device+Cushion, only need shape
Into collector layer.In this approach, collector material can be born using silicon back side annealing temperature by front metal Al electrodes
The limitation of maximum temperature, General N+The highest annealing temperature of cushion and collector layer is less than 500 DEG C.This method back side impurity
Activity ratio it is relatively low, generally less than 10%.Laser annealing can avoid this limitation from obtaining high impurity activation rate, but need high
Expensive equipment.
Inverse conductivity type IGBT most of structure is similar to traditional IGBT structure.Maximum difference is, against conductivity type IGBT's
Colelctor electrode is not continuous P+Area, but discontinuously introduce some N+Shorting region.Inverse conductivity type IGBT P-Base, N-Drift region, N+
Cushion and N+Shorting region constitutes a PIN diode.Inverse conductivity type IGBT is equivalent to an IGBT and a PIN diode is anti-
Parallel connection, only realize on the same chip.When IGBT is bearing back-pressure, the conducting of this PIN diode, this is also exactly to claim
The reason for it is inverse conductivity type IGBT.During shut-off, inverse conductivity type IGBT provides one effectively for drift region excess carriers
Take passage away, substantially reduce inverse conductivity type IGBT turn-off time.
Inverse conductivity type IGBT thought saves chip area, encapsulation, testing expense, reduces device cost.In addition, it is also
With it is low be lost, good SOA (safety operation area) characteristic, positive temperature coefficient, and good soft switching characteristic, short circuit
Characteristic and good power cycle characteristic.
However, inverse conductivity type IGBT also brings a little problems while plurality of advantages is possessed.Work as N+Shorting region is by N+Buffering
Layer is pulled upward to the level close with current collection electrode potential, and this causes collector junction to be difficult positively biased.This aspect produces rebound phenomenon, another
Aspect causes the hole injection efficiency of collector junction to reduce, so as to cause conduction voltage drop bigger.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of inverse conductivity type IGBT of energy suppression device rebound phenomenon collection
Electrode structure and preparation method thereof.
In order to solve the above technical problems, one aspect of the present invention provides a kind of inverse conductivity type IGBT collector structure,
Including：N-Germanium defect layer, P+Germanium collector area, N+Germanium shorting region and collector electrode metal layer；
The N-Germanium defect layer is arranged on base bottom surface；
The P+Germanium collector area and N+Germanium shorting region is disposed in parallel in the N-Germanium defect layer bottom surface and colelctor electrode gold
Between category layer.
Further, described inverse conductivity type IGBT collector structure, in addition to：
Cushion, the cushion are arranged on the N-Between germanium defect layer and the base；
The cushion includes N+Silicon layer or N+Germanium-silicon layer.
Further, described inverse conductivity type IGBT collector structure, in addition to：
N-Germanium layer, the N-Germanium layer is arranged on the N-Germanium defect layer and the P+Germanium collector area and N+Germanium shorting region it
Between.
Further, described inverse conductivity type IGBT collector structure, in addition to：
N+Germanium defect layer and P+Germanium defect layer；
The N+Germanium defect layer is arranged on the N-Germanium defect layer and N+Between germanium shorting region；
The P+Germanium defect layer is arranged on the N-Germanium defect layer and the P+Between germanium collector area.
Another aspect of the present invention provides a kind of preparation method of inverse conductivity type IGBT collector structure, including：
After chip back is thinned, in base bottom surface epitaxial germanium layer, N is formed-Germanium defect layer and N-Germanium layer, the N-Germanium layer
It is arranged on the N-Germanium defect layer bottom surface；
In the N-Germanium layer bottom surface is while by photoetching, then carries out p type impurity injection after annealing, forms P+Germanium collector area；
In the N-Germanium layer bottom surface another side is by photoetching, then carries out N-type impurity injection after annealing, forms N+Germanium shorting region；
By the P+ germanium collector area and N+Germanium shorting region bottom-side metalization forms collector electrode metal layer.
Further, the preparation method of described inverse conductivity type IGBT collector structure, in addition to：
Forming N-Germanium defect layer and N-Before germanium layer, in base, underrun ion implanting, which is annealed, to form cushion, described
Cushion includes N+Silicon layer or N+Germanium-silicon layer.
Further, it is described to form P+During germanium collector area, when p type impurity is diffused into the N-Germanium defect layer bottom surface side
During boundary, the P+Germanium collector area and the N-Germanium defect layer bottom surface is connected.
Further, it is described to form N+During germanium shorting region, when N-type impurity is diffused into the N- germanium defect layer bottom surface border
When, the N+Germanium shorting region and the N-Germanium defect layer bottom surface is connected.
Further, it is described to form P+During germanium collector area, when p type impurity is diffused into the N-When inside germanium defect layer,
P type impurity diffusion region and the P+Germanium defect layer overlapping region forms P+Germanium defect layer.
Further, it is described to form N+During germanium shorting region, when N-type impurity is diffused into the N-When inside germanium defect layer, N
Type impurity diffusion zone and the N-Germanium defect layer overlapping region forms N+Germanium defect layer.
A kind of inverse conductivity type IGBT provided by the invention collector structure and preparation method thereof, using germanium material or germanium silicon
Material, which does inverse conductivity type IGBT backside collectors, can be greatly reduced collector emitter voltage when rebound phenomenon occurs, transmitting
Electrode current density, so as to inhibit the rebound phenomenon of device.By using germanium material or germanium silicon material as back side cushion
And collector material, higher impurity activation rate can be obtained at low temperature.In addition, due to being deposited in the interface of germanium and silicon
In the very high region of defect concentration, the region can automatically form p-type doping, avoid the ion implantation process of costliness.It is this
Method can also reduce conducting voltage and turn-off time.
Brief description of the drawings
Fig. 1 is a kind of structural representation of the collector structure for inverse conductivity type IGBT that the embodiment of the present invention one provides.
Fig. 2 is to prepare N in structure shown in Fig. 1-Germanium defect layer and N-The structural representation of germanium layer；
Fig. 3 is in N when preparing structure shown in Fig. 1-Germanium layer bottom surface another side is by photoetching, then carries out N-type impurity injection
Schematic diagram；
Fig. 4 is to prepare N in structure shown in Fig. 1+The structural representation of germanium shorting region；
Fig. 5 is in N when preparing structure shown in Fig. 1-Germanium layer bottom surface another side is by photoetching, then carries out p type impurity injection
Schematic diagram；
Fig. 6 is to prepare P in structure shown in Fig. 1+The structural representation of germanium collector area；
Fig. 7 is a kind of structural representation of the collector structure for inverse conductivity type IGBT that the embodiment of the present invention two provides；
Fig. 8 is a kind of structural representation of the collector structure for inverse conductivity type IGBT that the embodiment of the present invention three provides；
Fig. 9 is a kind of structural representation of the collector structure for inverse conductivity type IGBT that the embodiment of the present invention four provides；
Figure 10 is a kind of structural representation of the collector structure for inverse conductivity type IGBT that the embodiment of the present invention five provides；
Figure 11 is a kind of structural representation of the collector structure for inverse conductivity type IGBT that the embodiment of the present invention six provides.
Embodiment
Embodiment one：
Referring to Fig. 1, a kind of inverse conductivity type IGBT collector structure provided in an embodiment of the present invention includes：
N-Germanium defect layer 101, N-Germanium layer 102, P+Germanium collector area 103, N+Germanium shorting region 104 and collector electrode metal layer
105。N-Germanium defect layer 101 is arranged on the bottom surface of base 100.N-Germanium layer 102 is arranged on the N-The germanium defect layer 101 and P+Germanium
Collector area 103 and N+Between germanium shorting region 104.P+Germanium collector area 103 and N+Germanium shorting region 104 is disposed in parallel in the N-
Between the bottom surface of germanium defect layer 101 and the collector electrode metal layer 105.
A kind of method of collector structure for preparing above-mentioned inverse conductivity type IGBT provided by the invention, including：
Step S1：Referring to Fig. 2, after chip back is thinned, in the bottom surface epitaxial germanium layer of base 100, N is formed-Germanium defect layer
101 and N-Germanium layer 102.After the completion of prepared by the Facad structure of chip, required thickness when chip back being thinned into design first
Degree.Then in the certain thickness germanium of bottom surface extension of base 100 under conditions of 400~500 DEG C.Because silicon Germanium lattice constant has difference
Not, therefore between silicon and germanium the higher N of a layer defects concentration can be formed-Germanium defect layer 101.The germanium of extension is low doping concentration
N-type doping semiconductor.After the defects of grown certain thickness germanium, the germanium layer of low defect density, i.e. N can be grown-Germanium layer
102。
Step S2：Referring to Fig. 5, Fig. 6 in the N-The bottom surface of germanium layer 102 is while by photoetching, then after carrying out p type impurity injection
Annealing, form P+Germanium collector area 103；
Step S3：Referring to Fig. 3, Fig. 4 in the N-The bottom surface another side of germanium layer 102 is by photoetching, then carries out N-type impurity injection
After annealing, form N+Germanium shorting region 104；
Step S4：By the P+Germanium collector area 103 and N+The bottom-side metalization of germanium shorting region 104 forms collector electrode metal layer.
The preparation order of wherein step 2 and step 3 can exchange, when carrying out p type impurity injection and N-type impurity injection, hydrogen
The energy of ion is 20-100KeV, implantation dosage 1012–1016/cm2, hydrogen ion activationary temperature is 300 DEG C -500 DEG C, preferably
Ground is 400 DEG C, and annealing time is 10 seconds to 120 minutes, it is therefore preferable to 10 minutes to 30 minutes.
Embodiment two：
Referring to Fig. 7, a kind of inverse conductivity type IGBT collector structure provided in an embodiment of the present invention includes：
N-Germanium defect layer 201, P+Germanium collector area 203, N+Germanium shorting region 204 and collector electrode metal layer.N-Germanium defect layer
201 are arranged on the bottom surface of base 200.P+Germanium collector area 203 and N+Germanium shorting region 204 is disposed in parallel in the N-Germanium defect layer 201
Between bottom surface and the collector electrode metal layer.
A kind of method of collector structure for preparing above-mentioned inverse conductivity type IGBT provided by the invention, including：
Step S1：Referring to Fig. 7, after chip back is thinned, in the bottom surface epitaxial germanium layer of base 200, N is formed-Germanium defect layer
201 and N-Germanium layer.After the completion of prepared by the Facad structure of chip, required thickness when chip back being thinned into design first.
Then in the certain thickness germanium of bottom surface extension of base 200 under conditions of 400~500 DEG C.Because silicon Germanium lattice constant has difference,
Therefore the higher N of a layer defects concentration can be formed between silicon and germanium-Germanium defect layer 201.The germanium of extension is the N-type of low doping concentration
Doped semiconductor.After the defects of grown certain thickness germanium, the germanium layer of low defect density, i.e. N can be grown-Germanium layer.
Step S2：In the N-The bottom surface of germanium layer 202 is while by photoetching, then carries out p type impurity injection after annealing, forms P+
Germanium collector area 203；It is described to form P+During germanium collector area 203, when p type impurity is diffused into the N-The bottom surface of germanium defect layer 201
During border, the P+The germanium collector area 203 and N-The bottom surface of germanium defect layer 201 is connected.
Step S3：In the N-The bottom surface another side of germanium layer 202 is by photoetching, then carries out N-type impurity injection after annealing, is formed
N+Germanium shorting region 204；It is described to form N+During germanium shorting region 204, when N-type impurity is diffused into the N-The bottom surface side of germanium defect layer 201
During boundary, the N+The germanium shorting region 204 and N-The bottom surface of germanium defect layer 201 is connected.
Step S4：By the P+Germanium collector area 103 and N+The bottom-side metalization of germanium shorting region 104 forms collector electrode metal layer.
The preparation order of wherein step 2 and step 3 can exchange, when carrying out p type impurity injection and N-type impurity injection, hydrogen
The energy of ion is 20-100KeV, implantation dosage 1012–1016/cm2, hydrogen ion activationary temperature is 300 DEG C -500 DEG C, preferably
Ground is 400 DEG C, and annealing time is 10 seconds to 120 minutes, it is therefore preferable to 10 minutes to 30 minutes.
Embodiment three：
Referring to Fig. 8, inverse conductivity type IGBT provided in an embodiment of the present invention collector structure includes：N-Germanium defect layer 301, N+
Germanium defect layer 306, P+Germanium defect layer 305, P+Germanium collector area 303, N+Germanium shorting region 304 and collector electrode metal layer 309.N-Germanium
Defect layer 301 is arranged on the bottom surface of base 300.P+Germanium collector area 303 and N+Germanium shorting region 304 is disposed in parallel in the N-Germanium lacks
Fall between the bottom surface of layer 301 and the collector electrode metal layer 309.N+Germanium defect layer 306 is arranged on the N-Germanium defect layer 301 and N+
Between germanium shorting region 304；The P+Germanium defect layer 305 is arranged on the N-The germanium defect layer 301 and P+Germanium collector area 303
Between.
The method for the collector structure for preparing above-mentioned inverse conductivity type IGBT that the present embodiment provides includes：
Step S1：Referring to Fig. 8, after chip back is thinned, in the bottom surface epitaxial germanium layer of base 300, N is formed-Germanium defect layer
301 and N-Germanium layer, after the completion of prepared by the Facad structure of chip, required thickness when chip back being thinned into design first.
Then in the certain thickness germanium of bottom surface extension of base 300 under conditions of 400~500 DEG C.Because silicon Germanium lattice constant has difference,
Therefore the higher N of a layer defects concentration can be formed between silicon and germanium-Germanium defect layer 301.The germanium of extension is the N-type of low doping concentration
Doped semiconductor.After the defects of grown certain thickness germanium, the germanium layer of low defect density, i.e. N can be grown-Germanium layer.
Step S2：In the N- germanium layers bottom surface while by photoetching, then p type impurity injection after annealing is carried out, form P+Germanium
Collector area 303；Forming P+During germanium collector area 303, when p type impurity is diffused into the N-During germanium 301 inside of defect layer, p-type
Impurity diffusion zone and the P+The overlapping region of germanium defect layer 301 forms P+Germanium defect layer 305.
Step S3：In the N-Germanium layer bottom surface another side is by photoetching, then carries out N-type impurity injection after annealing, forms N+Germanium
Shorting region 304；Forming N+During germanium shorting region 304, when N-type impurity is diffused into the N-During germanium 301 inside of defect layer, N-type impurity
Diffusion region and the N-The overlapping region of germanium defect layer 301 forms N+Germanium defect layer 306.Step S4：By the P+Germanium collector area
103 and N+The bottom-side metalization of germanium shorting region 104 forms collector electrode metal layer 309.
The preparation order of wherein step 2 and step 3 can exchange, when carrying out p type impurity injection and N-type impurity injection, hydrogen
The energy of ion is 20-100KeV, implantation dosage 1012–1016/cm2, hydrogen ion activationary temperature is 300 DEG C -500 DEG C, preferably
Ground is 400 DEG C, and annealing time is 10 seconds to 120 minutes, it is therefore preferable to 10 minutes to 30 minutes.
Example IV：
Referring to Fig. 9, the present embodiment and the difference of embodiment one are, a kind of inverse conductivity type provided in an embodiment of the present invention
IGBT collector structure also includes cushion, and cushion includes N+ silicon layers, N+Germanium layer or N+Germanium-silicon layer.What the present embodiment used
It is N+Silicon layer 407.N+Silicon layer 407 is arranged on the N-Between germanium defect layer 101 and the base 100.
The method for the collector structure for preparing above-mentioned inverse conductivity type IGBT that the present embodiment provides, step S1 are by chip back
After being thinned, first pass through ion implanting and anneal to form N+Silicon layer 407 is used as cushion, then in N+The bottom surface epitaxial Germanium of silicon layer 407
Layer, form N-Germanium defect layer 101 and N-Germanium layer 102.After the completion of prepared by the Facad structure of chip, chip back is thinned first
To thickness required during design.Then in N under conditions of 400~500 DEG C+The certain thickness germanium of bottom surface extension of silicon layer 407.By
There is difference in silicon Germanium lattice constant, therefore the higher N of a layer defects concentration can be formed between silicon and germanium-Germanium defect layer 101.Extension
Germanium be low doping concentration n-type doping semiconductor.After the defects of grown certain thickness germanium, low defect density can be grown
Germanium layer, i.e. N-Germanium layer 102.Wherein, the N as cushion+Silicon layer 407 can form N by depositing germanium silicon+Germanium-silicon layer is carried out
Replace, N can also be formed by precipitating germanium+Germanium layer is replaced.
It is completely the same with embodiment one elsewhere.
Embodiment five：
Referring to Figure 10, the present embodiment and the difference of embodiment two are, one kind provided in an embodiment of the present invention is inverse to be led
Type IGBT collector structure also includes cushion, and cushion includes N+Silicon layer, N+Germanium layer or N+Germanium-silicon layer.The present embodiment uses
Be N+Silicon layer 507.N+Silicon layer 507 is arranged on the N-Between germanium defect layer 201 and the base 200.
The method for the collector structure for preparing above-mentioned inverse conductivity type IGBT that the present embodiment provides, step S1 are by chip back
After being thinned, first pass through ion implanting and anneal to form N+Silicon layer 507 is used as cushion, then in N+The bottom surface epitaxial Germanium of silicon layer 507
Layer, form N-Germanium defect layer 201 and N-Germanium layer 202.After the completion of prepared by the Facad structure of chip, chip back is thinned first
To thickness required during design.Then in N under conditions of 400~500 DEG C+The certain thickness germanium of bottom surface extension of silicon layer 507.By
There is difference in silicon Germanium lattice constant, therefore the higher N of a layer defects concentration can be formed between silicon and germanium-Germanium defect layer 201.Extension
Germanium be low doping concentration n-type doping semiconductor.After the defects of grown certain thickness germanium, low defect density can be grown
Germanium layer, i.e. N-Germanium layer 202.Wherein, the N as cushion+Silicon layer 507 can form N by depositing germanium silicon+Germanium-silicon layer is carried out
Replace, N can also be formed by precipitating germanium+Germanium layer is replaced.
It is completely the same with embodiment two elsewhere.
Embodiment six：
The present embodiment and the difference of embodiment three be, a kind of inverse conductivity type IGBT collection provided in an embodiment of the present invention
Electrode structure also includes cushion, and cushion includes N+Silicon layer, N+Germanium layer or N+Germanium-silicon layer.The present embodiment is using N+Silicon layer
607。N+Silicon layer 607 is arranged on the N-Between germanium defect layer 301 and the base 300.
The method for the collector structure for preparing above-mentioned inverse conductivity type IGBT that the present embodiment provides, step S1 are by chip back
After being thinned, first pass through ion implanting and anneal to form N+Silicon layer 607 is used as cushion, then in N+The bottom surface epitaxial Germanium of silicon layer 607
Layer, form N-Germanium defect layer 301 and N-Germanium layer 302.After the completion of prepared by the Facad structure of chip, chip back is thinned first
To thickness required during design.Then in N under conditions of 400~500 DEG C+The certain thickness germanium of bottom surface extension of silicon layer 607.By
There is difference in silicon Germanium lattice constant, therefore the higher N of a layer defects concentration can be formed between silicon and germanium-Germanium defect layer 301.Extension
Germanium be low doping concentration n-type doping semiconductor.After the defects of grown certain thickness germanium, low defect density can be grown
Germanium layer, i.e. N-Germanium layer 302.Wherein, the N as cushion+Silicon layer 307 can form N by depositing germanium silicon+Germanium-silicon layer is carried out
Replace, N can also be formed by precipitating germanium+Germanium layer is replaced.
It is completely the same with embodiment three elsewhere.
Because the PN junction cut-in voltage of silicon materials is 0.70V, and the PN junction cut-in voltage of germanium material is 0.32V, the present invention
Inverse conductivity type IGBT collector structure provided and preparation method thereof, the inverse conductivity type IGBT back ofs the body are done using germanium material or germanium silicon material
Face colelctor electrode can be greatly reduced occur rebound phenomenon when collector emitter voltage, emitter current density, so as to suppress
The rebound phenomenon of device.By using germanium material or germanium silicon material as back side cushion and collector material, Ke Yi
Higher impurity activation rate is obtained under low temperature.In addition, due to the very high area of the interface existing defects density in germanium and silicon
Domain, the region can automatically form p-type doping, avoid the ion implantation process of costliness.This method can also reduce conducting
Voltage and turn-off time.Specifically bring following beneficial effect：
(1) be greatly reduced occur rebound phenomenon when collector emitter voltage, emitter current density, so as to suppress
The rebound phenomenon of device；
(2) ion implanting is used, there is the control of accurate impurity concentration；
(3) impurity activation of low temperature, impurity can activate completely at 400 DEG C；
(4)P+Germanium has higher carrier mobility, and P+Germanium has lower contact berrier, therefore IGBT has
Lower conduction voltage drop；
(5) control of colelctor electrode transparency, germanium has smaller minority carrier lifetime, overleaf during PN junction positively biased, from
N-Base is injected into P+Carrier in germanium can be compound faster, therefore IGBT has faster turn-off speed.
It should be noted last that above embodiment is merely illustrative of the technical solution of the present invention and unrestricted,
Although the present invention is described in detail with reference to example, it will be understood by those within the art that, can be to the present invention
Technical scheme modify or equivalent substitution, without departing from the spirit and scope of technical solution of the present invention, it all should cover
Among scope of the presently claimed invention.
Claims (10)
- A kind of 1. inverse conductivity type IGBT collector structure, it is characterised in that including：N-Germanium defect layer, P+Germanium collector area, N+Germanium shorting region and collector electrode metal layer；The N-Germanium defect layer is arranged on base bottom surface；The P+Germanium collector area and N+Germanium shorting region is disposed in parallel in the N-Germanium defect layer bottom surface and the collector electrode metal layer Between.
- 2. inverse conductivity type IGBT as claimed in claim 1 collector structure, it is characterised in that also include：Cushion, the cushion are arranged on the N-Between germanium defect layer and the base；The cushion includes N+Silicon layer or N+Germanium-silicon layer.
- 3. inverse conductivity type IGBT as claimed in claim 1 or 2 collector structure, it is characterised in that also include：N-Germanium layer, the N-Germanium layer is arranged on the N-Germanium defect layer and the P+Germanium collector area and N+Between germanium shorting region.
- 4. inverse conductivity type IGBT as claimed in claim 1 or 2 collector structure, it is characterised in that also include：N+Germanium defect layer and P+Germanium defect layer；The N+Germanium defect layer is arranged on the N-Germanium defect layer and N+Between germanium shorting region；The P+Germanium defect layer is arranged on the N-Germanium defect layer and the P+Between germanium collector area.
- A kind of 5. preparation method of inverse conductivity type IGBT collector structure, it is characterised in that including：After chip back is thinned, in base bottom surface epitaxial germanium layer, N is formed-Germanium defect layer and N-Germanium layer, the N-Germanium layer is set In the N-Germanium defect layer bottom surface；In the N-Germanium layer bottom surface is while by photoetching, then carries out p type impurity injection after annealing, forms P+Germanium collector area；In the N-Germanium layer bottom surface another side is by photoetching, then carries out N-type impurity injection after annealing, forms N+Germanium shorting region；By the P+Germanium collector area and N+Germanium shorting region bottom-side metalization forms collector electrode metal layer.
- 6. the preparation method of inverse conductivity type IGBT as claimed in claim 5 collector structure, it is characterised in that also include：Forming N-Germanium defect layer and N-Before germanium layer, in base, underrun ion implanting, which is annealed, to form cushion, the buffering Layer includes N+Silicon layer or N+Germanium-silicon layer.
- 7. the preparation method of the collector structure of the inverse conductivity type IGBT as described in claim 5 or 6, it is characterised in that：It is described to form P+During germanium collector area, when p type impurity is diffused into the N-During germanium defect layer bottom surface border, the P+Germanium Collector area and the N-Germanium defect layer bottom surface is connected.
- 8. the preparation method of the collector structure of the inverse conductivity type IGBT as described in claim 5 or 6, it is characterised in that：It is described to form N+During germanium shorting region, when N-type impurity is diffused into the N-During germanium defect layer bottom surface border, the N+Germanium is short Road area and the N-Germanium defect layer bottom surface is connected.
- 9. the preparation method of the collector structure of the inverse conductivity type IGBT as described in claim 5 or 6, it is characterised in that it is described again P type impurity injection after annealing is carried out, forms P+Germanium collector area includes：It is described to form P+During germanium collector area, when p type impurity is diffused into the N-When inside germanium defect layer, p type impurity diffusion region With the P+Germanium defect layer overlapping region forms P+Germanium defect layer.
- 10. the preparation method of the collector structure of the inverse conductivity type IGBT as described in claim 5 or 6, it is characterised in that：It is described to form N+During germanium shorting region, when N-type impurity is diffused into the N-When inside germanium defect layer, N-type impurity diffusion region with The N-Germanium defect layer overlapping region forms N+Germanium defect layer.
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| CN106816377B (en) * | 2015-11-30 | 2019-11-22 | 株洲中车时代电气股份有限公司 | The back side IGBT production method and IGBT |
| CN112750901B (en) * | 2019-10-30 | 2023-06-16 | 广东美的白色家电技术创新中心有限公司 | Reverse-conduction IGBT device and intelligent power module |
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