CN115458583B - Gold-platinum double doping method of fast recovery diode - Google Patents
Gold-platinum double doping method of fast recovery diode Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000011084 recovery Methods 0.000 title claims abstract description 23
- JUWSSMXCCAMYGX-UHFFFAOYSA-N gold platinum Chemical compound [Pt].[Au] JUWSSMXCCAMYGX-UHFFFAOYSA-N 0.000 title claims abstract description 15
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 67
- 238000000137 annealing Methods 0.000 claims abstract description 32
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000004544 sputter deposition Methods 0.000 claims abstract description 17
- 229910052737 gold Inorganic materials 0.000 claims abstract description 15
- 239000010931 gold Substances 0.000 claims abstract description 15
- 238000001704 evaporation Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000001259 photo etching Methods 0.000 claims abstract description 11
- -1 boron ions Chemical class 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 229910052796 boron Inorganic materials 0.000 claims abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
- 230000007547 defect Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 6
- 230000008020 evaporation Effects 0.000 claims description 4
- 230000008595 infiltration Effects 0.000 claims description 4
- 238000001764 infiltration Methods 0.000 claims description 4
- 238000009740 moulding (composite fabrication) Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims 2
- 230000003213 activating effect Effects 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000012299 nitrogen atmosphere Substances 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 125000000623 heterocyclic group Chemical group 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/6609—Diodes
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The application discloses a gold-platinum double doping method of a fast recovery diode in the field of fast recovery diodes, which comprises the following steps: s1, growing an N-type epitaxial layer on an N-type silicon substrate, and growing an oxide layer on the N-type epitaxial layer; s2, opening a ring region and a cell region on the oxide layer through photoetching, injecting a small amount of boron ions, and forming a P-type lightly doped region through annealing treatment; s3, growing polysilicon on the product obtained in the step S2 to form a polysilicon layer, heavily doping the polysilicon layer, and removing the polysilicon on the ring area and the cell area through photoetching; s4, sputtering or evaporating a layer of platinum on the back surface of the N-type silicon substrate, and performing high-temperature annealing; s5, sputtering or evaporating a layer of gold on the front surface of the product obtained in the step S4, and performing secondary high-temperature annealing. The uniformity of VF in the fast recovery diode can be optimized in the doping method; obtaining a better VF-Trr curve; and the PN junction breakdown voltage of the fast recovery diode is improved.
Description
Technical Field
The application relates to the technical field of fast recovery diodes, in particular to a gold-platinum double doping method of a fast recovery diode.
Background
Compared with the common diode, the biggest characteristic of the recovery diode is the ultra-fast reverse recovery characteristic (the reverse recovery time range is 10-150 nanoseconds). The reverse recovery time is mainly determined by the minority carrier lifetime of the base region, so the change of the minority carrier lifetime and the control method of the minority carrier lifetime are particularly important in the research of the ultrafast recovery diode. The principle of the life control technology is to introduce a compound center with proper spatial distribution into the device so as to effectively reduce the sub-life and improve the switching speed of the device. The research on the recombination center mainly focuses on the energy level position E of the recombination center, the electron trapping coefficient, the hole trapping coefficient, the annealing temperature and the like. The adopted life control technology comprises methods of gold doping, platinum doping, electron irradiation and the like.
At present, the mainstream at home and abroad is to control minority carrier lifetime by using doped platinum, but the doped platinum product is easily influenced by substrate material defects, impurity penetration of a clamp in the epitaxial processing process and the like, so that the uniformity of VF in a product chip is poor, and the VF-Trr curve is poor.
Disclosure of Invention
The application provides a gold-platinum double-doping method of a fast recovery diode, which solves the problems that in the prior art, a platinum-doped product is easy to have poor in-chip VF uniformity and a VF-Trr curve is poor, and obtains a better VF-Trr curve.
The embodiment of the application provides a gold-platinum double doping method of a fast recovery diode, which comprises the following steps:
s1, growing an N-type epitaxial layer on an N-type silicon substrate, and growing an oxide layer on the N-type epitaxial layer;
s2, opening a ring region and a cell region on the oxide layer through photoetching, injecting a small amount of boron ions, and forming a P-type lightly doped region through annealing treatment;
s3, growing polysilicon on the product obtained in the step S2 to form a polysilicon layer, heavily doping the polysilicon layer, and removing the polysilicon on the ring area and the cell area through photoetching;
s4, sputtering or evaporating a layer of platinum on the back surface of the N-type silicon substrate, and performing high-temperature annealing;
and S5, sputtering or evaporating a layer of gold on the front surface of the product obtained in the step S4, and performing secondary high-temperature annealing.
The beneficial effects of the above embodiment are that: the reverse sputtering platinum on the back reduces the inversion probability caused by high-temperature platinum expansion, is convenient for increasing the platinum expansion temperature, and the produced chip has shorter turn-off time and reverse overshoot current, and simultaneously ensures that reverse recovery is more gentle and larger softness is obtained; the heavily doped polysilicon can attract platinum impurities on the back surface to carry out a large amount of enrichment, so that the defects of the substrate material and the influence caused by impurity infiltration in the processing process are reduced, and the uniformity of VF in the chip is optimized; the overall defect concentration of platinum impurities in the terminal area of the chip is reduced by doping gold on the front surface, the distribution of the compound center is optimized, and the advantage of gold atomic energy level is utilized to finally obtain a better VF-Trr curve; meanwhile, the heavily doped polysilicon of the ring region can eliminate the influence of junction bending effect, weaken the surface electric field intensity and improve the PN junction breakdown voltage of the power quick recovery device.
On the basis of the above embodiments, the present application can be further improved, and specifically, the following steps are provided:
in one embodiment of the present application, in the step S2, the boron ion doping concentration is 1E12-9E14, the annealing temperature is 1000-1300 ℃, and during the annealing, 1-10slm of nitrogen is introduced. And finally forming a lightly doped heterocyclic zone and a cellular zone with the junction depth of 1-15 um.
In one embodiment of the present application, the polysilicon layer is doped with phosphorus ions in the step S3, and the doping concentration is 1E20-9E22.
In one embodiment of the present application, in the step S4, the annealing temperature of the platinum is 930-950 ℃, and during annealing, 1-10slm of nitrogen is introduced. The platinum annealing temperature is increased, and meanwhile, the metal platinum is activated in the nitrogen atmosphere of 1-10slm to form a deep energy level recombination center to control the minority carrier lifetime.
In one embodiment of the present application, in the step S5, the temperature of Jin Tuihuo is 500-900 ℃, and during the annealing, 1-10slm of nitrogen is introduced. Annealing the gold atoms in a nitrogen atmosphere of 1-10slm, further optimizing the formed composite center by introducing the gold atoms, reducing the concentration of the composite center formed by the platinum atoms, reducing the influence of uneven concentration of platinum impurities on VF, and finally obtaining a better VF-Trr curve.
In one embodiment of the present application, the method further comprises the steps of:
s6, plating a metal layer on the front surface through sputtering or evaporation, and forming a front electrode through photoetching; and plating a metal layer on the back surface by sputtering or evaporating to form a back electrode. Finally, the fast recovery diode with reliable performance and better VF-Trr curve is obtained.
One or more technical solutions provided in the embodiments of the present application at least have the following technical effects or advantages:
1. according to the doping method, the back side is sputtered with platinum, the front side is provided with heavily doped polycrystalline silicon, so that the defects of a substrate material and the influence caused by impurity infiltration in the processing process are reduced, and the uniformity of VF in a chip is optimized;
2. in the doping method, the composite center distribution is optimized by sputtering platinum on the back and doping gold on the front, and the advantage of gold atomic energy level is utilized to finally obtain a better VF-Trr curve;
3. the heavily doped polysilicon of the ring region in the doping method can eliminate the influence of the bending effect of the junction surface, weaken the intensity of the surface electric field and improve the PN junction breakdown voltage of the power quick recovery device.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. Like elements or portions are generally identified by like reference numerals throughout the several figures. In the drawings, elements or portions thereof are not necessarily drawn to scale.
FIG. 1 is a schematic diagram of a process of a dual-doping method of Au-Pt in an embodiment;
FIG. 2 is a second schematic diagram of a process of the Au-Pt double doping method in the embodiment;
FIG. 3 is a process diagram of a gold-platinum double doping method according to an embodiment;
FIG. 4 is a schematic diagram of a process of a dual-doping method of gold and platinum in an embodiment;
FIG. 5 is a schematic diagram showing a process of a dual-doping method of gold and platinum in an embodiment;
FIG. 6 is a process diagram of a dual-doping method of gold and platinum in an embodiment.
The semiconductor device comprises a 1.N type silicon substrate, a 2. N-type epitaxial layer, a 3. Oxide layer, a 4.P-type lightly doped region, a 5. Polycrystalline silicon layer, 6. Platinum, 7. Gold, 8. Front electrode and 9. Back electrode.
Detailed Description
The present application is further illustrated below in conjunction with the specific embodiments, it being understood that these embodiments are meant to be illustrative of the application only and not limiting the scope of the application, and that modifications of the application, which are equivalent to those skilled in the art to which the application pertains, will fall within the scope of the application as defined in the appended claims.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present application, it should be noted that the azimuth or positional relationship indicated by the terms "vertical", "peripheral surface", etc. are based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship that the inventive product is conventionally put in use, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application.
In the description of the present application, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the various embodiments or examples of the application described and the features of the various embodiments or examples may be combined and combined by those skilled in the art without contradiction.
The embodiment of the application solves the problems that in the prior art, a platinum-doped product is easy to have poor in-chip VF uniformity and a VF-Trr curve is poor by providing the gold-platinum double-doping method of the fast recovery diode, and a better VF-Trr curve is obtained.
The technical scheme in the embodiment of the application aims to solve the problems, and the overall thought is as follows:
examples:
a gold-platinum double doping method of a fast recovery diode comprises the following steps:
s1, as shown in FIG. 1, an N-type epitaxial layer 2 is grown on an N-type silicon substrate 1, and an oxide layer 3 is grown on the N-type epitaxial layer 2.
S2, as shown in FIG. 2, a ring region and a cell region are opened on the oxide layer 3 by photoetching, boron ions are injected, and then the P-type lightly doped region 4 is formed by annealing treatment.
Wherein, the doping concentration of boron ions is 1E12-9E14, the annealing temperature is 1000-1300 ℃, and during the annealing, nitrogen with the depth of 1-10slm is introduced, and finally, a lightly doped heterocyclic zone and a cellular zone with the junction depth of 1-15um are formed.
And S3, as shown in FIG. 3, growing polysilicon on the product obtained in the step S2 to form a polysilicon layer 5, heavily doping the polysilicon layer 5, and removing the polysilicon on the ring region and the cell region by photoetching.
Wherein, the polysilicon layer is doped with phosphorus ions, and the doping concentration is 1E20-9E22.
S4, as shown in FIG. 4, sputtering or evaporating a layer of platinum 6 on the back surface of the N-type silicon substrate 1, and performing high-temperature annealing.
The annealing temperature of the platinum is 930-950 ℃, during the annealing, 1-10slm of nitrogen is introduced, and the metal platinum is activated in the nitrogen atmosphere to form a deep energy level recombination center to control the minority carrier lifetime.
S5, as shown in FIG. 5, sputtering or evaporating a layer of gold 7 on the front surface of the product obtained after the step S4, and performing secondary high-temperature annealing.
Wherein, the temperature of Jin Tuihuo is 500-900 ℃, and 1-10slm of nitrogen is introduced during the annealing. And annealing the gold atoms in a nitrogen atmosphere, further optimizing the formed composite center by introducing the gold atoms, reducing the concentration of the composite center formed by the platinum atoms, reducing the influence of uneven concentration of platinum impurities on VF, and finally obtaining a better VF-Trr curve.
S6, as shown in FIG. 6, plating a required metal layer on the front surface of the product obtained in the step S5 through sputtering or evaporation, and forming a front electrode 8 through photoetching and etching; the back electrode 9 is formed by plating a desired metal layer on the back surface by sputtering or evaporation.
The technical scheme provided by the embodiment of the application at least has the following technical effects or advantages:
1. according to the doping method, the back side is sputtered with platinum, the front side is provided with heavily doped polycrystalline silicon, so that the defects of a substrate material and the influence caused by impurity infiltration in the processing process are reduced, and the uniformity of VF in a chip is optimized;
2. in the doping method, the composite center distribution is optimized by sputtering platinum on the back and doping gold on the front, and the advantage of gold atomic energy level is utilized to finally obtain a better VF-Trr curve;
3. the heavily doped polysilicon of the ring region in the doping method can eliminate the influence of the bending effect of the junction surface, weaken the intensity of the surface electric field and improve the PN junction breakdown voltage of the power quick recovery device.
While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.
Claims (6)
1. The gold-platinum double doping method of the fast recovery diode is characterized by comprising the following steps of:
s1, growing an N-type epitaxial layer on an N-type silicon substrate, and growing an oxide layer on the N-type epitaxial layer;
s2, opening a ring region and a cell region on the oxide layer through photoetching, injecting a small amount of boron ions, and forming a P-type lightly doped region through annealing treatment;
s3, growing polysilicon on the product obtained in the step S2 to form a polysilicon layer, heavily doping the polysilicon layer, and removing the polysilicon on the ring area and the cell area through photoetching;
s4, sputtering or evaporating a layer of platinum on the back surface of the N-type silicon substrate, performing high-temperature annealing, and activating the metal platinum to form a deep energy level composite center to control the minority carrier lifetime;
s5, sputtering or evaporating a layer of gold on the front surface of the product obtained in the step S4, performing secondary high-temperature annealing, annealing gold atoms, further optimizing formed composite centers through the introduction of the gold atoms, reducing the concentration of the composite centers formed by platinum atoms, reducing the influence of uneven concentration of platinum impurities on VF, and finally obtaining a better VF-Trr curve;
in step S3, the heavily doped polysilicon attracts the platinum impurities on the back to perform a large amount of enrichment, so as to reduce the influence caused by defects of the substrate material and impurity infiltration in the processing process, and optimize the uniformity of on-chip VF.
2. The gold-platinum double doping method according to claim 1, wherein: in the step S2, the doping concentration of the boron ions is 1E12-9E14, the annealing temperature is 1000-1300 ℃, and 1-10slm of nitrogen is introduced during the annealing.
3. The gold-platinum double doping method according to claim 2, wherein: and in the step S3, the polysilicon layer is doped with phosphorus ions, and the doping concentration is 1E20-9E22.
4. A gold-platinum double doping method according to claim 3, wherein: in the step S4, the annealing temperature of the platinum is 930-950 ℃, and 1-10slm of nitrogen is introduced during annealing.
5. The gold-platinum double doping method according to claim 4, wherein: in the step S5, the temperature of Jin Tuihuo is 500-900 ℃, and 1-10slm of nitrogen is introduced during annealing.
6. The gold-platinum double doping method according to claim 1, further comprising the steps of:
s6, plating a metal layer on the front surface through sputtering or evaporation, and forming a front electrode through photoetching; and plating a metal layer on the back surface by sputtering or evaporating to form a back electrode.
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| CN114093928A (en) * | 2021-11-11 | 2022-02-25 | 扬州国宇电子有限公司 | Platinum doping method of fast recovery diode |
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| US20120153438A1 (en) * | 2010-12-16 | 2012-06-21 | Solid State Devices, Inc. | Multiple noble metals for lifetime suppression for power semiconductors |
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