CN207781616U - Power semiconductor - Google Patents

Abstract

This application discloses power semiconductors.The device includes：Positioned at the Facad structure of the first surface of semiconductor substrate, the Facad structure includes well region and emitter region, and the emitter region is located in the well region；Positioned at the buffering area and collecting zone of the second surface of the semiconductor substrate, the collecting zone is extended to from the second surface and is abutted with the buffering area, wherein, the semiconductor substrate forms the drift region of the power semiconductor, the drift region, the emitter region and the buffering area are the first doping type, the well region and the collecting zone are the second doping type, first doping type and second doping type are opposite each other, the second surface of the semiconductor substrate passes through laser treatment, to reduce the roughness of the second surface of the semiconductor substrate, and the oxygen content in the reduction buffering area.

Description

Power semiconductor

Technical field

The utility model is related to semiconductor devices, more particularly, to power semiconductor.

Background technology

Power semiconductor is widely used in electronic equipment, for example, in power amplifier as amplifying transistor or Person is in power circuit as switching transistor.Power semiconductor includes bipolar transistor, metal-oxide semiconductor (MOS) crystalline substance Body pipe (MOSFET) and insulated gate bipolar transistor (IGBT) etc..

IGBT has both the high input impedance and bipolar junction transistor of MOS memory (MOSFET) The current-carrying capability of (Bipolar Junction Transistor, BJT) can simplify gate driving requirement, while enhance conducting shape State property energy.It has many advantages, such as the frequency range of low saturation voltage, high current density, high blocking ability and up to 100kHz, therefore Bipolar transistor during lower-wattage can be replaced to apply rapidly and the grid clip cutout silicon control rectification in higher-power applications Body (Gate Turn-off Thyristor, GTO).

The switch mechanism of IGBT and vertical double-diffused MOS FET (VDMOSFET) are just the same.Using the grid control of MOSFET It is made to turn on and off.IGBT is P+ layers of the drain electrode addition in power MOSFET, i.e. the collector side of IGBT is P+ layers, to increase Add P+N knot, conductivity modulation effect is introduced in carrier drift area when work, to overcome high-pressure work and low on-resistance Contradiction.

In the evolution of IGBT, main research topic is to improve the trade-off relation of saturation voltage and switching characteristic, There are the optimization of gate oxidation films, the miniaturization of cellular size and optimization to reduce the major technique that saturation voltage uses, reduce and close The new construction of resistance break, new life control method.There are N+ buffering areas, P+ current collections to reduce the major technique that fall time uses Optimization and the new life control method of pole layer concentration and thickness, it is non-with the continuous improvement of IGBT device manufacturing technology level Break-through (NPT) type IGBT melts chip using the high area of resistivity, and the epitaxial wafer of fictitious hosts costliness has been current IGBT devices The main way of part production.Non- break-through (NPT) type IGBT is to pass through thinned wafer thickness, example after the completion of IGBT Facad structures The IGBT of such as nominal pressure resistance 600V needs the thickness for being thinned to 80~85um or so, then in chip back surface ion implanting and annealing Technique forms the lower PN junction of emission effciency, simultaneously because the N drift region thickness for bearing high blocking voltage is increased, so that Depletion layer penetration phenomenon is not will produce under high voltages.

Further, inject/irradiate H+ in the bottom of chip to form N+ buffering areas, to reduce the thickness of drift region, And deeper buffering area is formed in IGBT device body, improve the dv/dt characteristics of power semiconductor.However, the buffering The formation in area generates the defect of multiple and different energy levels in the wafer, and the breakdown voltage of power semiconductor is caused to reduce and leak electricity Stream increases.In order to reduce buffering area defect adverse effect, at present using area melt chip, and improve heat treatment temperature and when Between, cause production efficiency to reduce and is increased with device cost.

Therefore, it is desirable to the defects count of buffering area is further reduced in power semiconductor with improve breakdown voltage and Reduce leakage current.

Utility model content

In view of this, the purpose of this utility model is to provide power semiconductor, wherein right before forming buffering area The second surface of semiconductor substrate carries out laser treatment improving breakdown voltage, reducing leakage current and reducing device cost.

According to the utility model, a kind of power semiconductor is provided, including：Positioned at the first surface of semiconductor substrate Facad structure, the Facad structure include well region and emitter region, and the emitter region is located in the well region；Positioned at the semiconductor The buffering area and collecting zone of the second surface of substrate, the collecting zone extend to and buffering area neighbour from the second surface Connect, wherein the semiconductor substrate forms the drift region of the power semiconductor, the drift region, the emitter region and The buffering area is the first doping type, and the well region and the collecting zone are the second doping type, first doping type It is opposite each other with second doping type, the surface roughness of the second surface of the semiconductor substrate after laser treatment To be less than or equal to 0.01 micron.

Preferably, power semiconductor further includes：With first contacting for emitter region electrical connection, and with the collection Second contact of electric area's electrical connection.

Preferably, the semiconductor substrate is to be made selected from zone-melting process (FZ), vertical pulling method (CZ) or magnetic field Czochralski method (MCZ) Silicon wafer.

Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type In another kind.

According to the power semiconductor of the utility model embodiment, ion note is carried out in the second surface of semiconductor substrate The oxygen atom content for reducing pretreatment zone in substrate slice before entering in advance by laser treatment, so as to reduce subsequent shape At the defects of buffering area density.This can effectively improve by defect exist and cause power semiconductor dynamic The low-voltage breakdown Problem of Failure occurred when snowslide, to improve breakdown voltage and reduce leakage current.It is possible to further adopt The silicon wafer made of use cost more cheap but relatively high oxygen element content vertical pulling method (CZ) or magnetic field Czochralski method (MCZ) Piece can form Thermal donor layer, production effect when forming buffer layer using lower heat treatment temperature and heat treatment time Rate improves, thus can reduce device cost.

In a preferred embodiment, N-type buffer layer is formed using dopant any in H+, He2+, S, to Can further decrease the defects count of ion implanting introducing, for example, with it is lower by oxygen atom and vacancy formed the centers OV or The defects of person A center E (90K), the centers K H (195K) and V2O E (230K), in a further preferred embodiment, N-type, are slow It rushes layer to be formed using H+ dopants, compared with He2+ injects, leakage current present in power semiconductor can be inhibited, into one Step improves the junction temperature of semiconductor devices.

Description of the drawings

By referring to the drawings to the description of the utility model embodiment, above-mentioned and other mesh of the utility model , feature and advantage will be apparent from, in the accompanying drawings：

The section of power semiconductor each production phase according to the utility model embodiment is shown respectively in Fig. 1 to 6 Schematic diagram.

Fig. 7 shows the defect type and energy level of buffering area in power semiconductor.

Fig. 8 shows that power semiconductor carries out laser treatment to surface and do not carry out the oxygen of two kinds of situations of laser treatment The content distribution of elements figure.

Specific implementation mode

Hereinafter reference will be made to the drawings is more fully described the utility model.In various figures, identical element is using similar Reference numeral indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown Certain well known parts.

Many specific details of the utility model, such as the structure of device, material, size, place are described hereinafter Science and engineering skill and technology, to be more clearly understood that the utility model.But just as the skilled person will understand, The utility model can not be realized according to these specific details.

The utility model can be presented in a variety of manners, some of them example explained below.

The section of power semiconductor each production phase according to the utility model embodiment is shown respectively in Fig. 1 to 6 Schematic diagram.

As shown in Figure 1, having formed the Facad structure of power semiconductor in semiconductor substrate 101.It ties in the front Structure for example includes the well region 102 being located in semiconductor substrate 101, the emitter region 103 in well region 102, is located on well region 102 The gate dielectric layer 104 and grid conductor 105, the interlayer dielectric layer 106 above grid conductor 105 and via interlayer of side Through-hole in dielectric layer 106 contacts 107 with first that emitter region 103 is electrically connected.Gate dielectric layer 104 and the formation of grid conductor 105 Gate stack.

Semiconductor substrate 101 can be semiconductor substrate of any suitable type, such as silicon substrate, germanium silicon substrate etc.. The embodiment, semiconductor substrate 101 are, for example, doped N-type<100>The silicon wafer of crystal orientation.The semiconductor substrate 101 can be The silicon wafer that zone-melting process (FZ), vertical pulling method (CZ) or magnetic field Czochralski method (MCZ) make, thickness is, for example, 625 microns to 675 micro- Rice.As known to technical staff, it is suitable for the device of different resistivity using the silicon wafer that distinct methods make.Into one Step ground, according to the resistivity of the nominal pressure resistance selection semiconductor substrate of power semiconductor.For example, the work(of nominal pressure resistance 600V The resistivity for the semiconductor substrate 101 that rate semiconductor devices uses for 18ohmcm to 27ohmcm, nominal pressure resistance 1200V's The resistivity for the semiconductor substrate 101 that power semiconductor uses is 45ohmcm to 55ohmcm.

Semiconductor substrate 101 includes each other relative first surface and second surface.In the first table of semiconductor substrate 101 On face Facad structure is formed using multiple steps.Preferably, before forming Facad structure, isolation structure can also be formed to limit Determine the active area of power semiconductor.

Further, using the ion implanting executed successively, p-type trap is formed in the first surface of N-type semiconductor substrate 101 Area 102, and N-type emitter region 103 is formed in P type trap zone 102.

Further, by thermal oxide in N-type semiconductor substrate 101, the exposure of P type trap zone 102 and N-type emitter region 103 Surface forms gate dielectric layer 104.For example, the material of gate dielectric layer 104 can be silica, thickness can be between 500 Angstrom between 1500 angstroms.

Further, the thickness of the deposit polycrystalline silicon layer on gate dielectric layer 104, the polysilicon layer can be between 5000 angstroms To between 8000 angstroms.The doping type of the polysilicon layer is N-type, and resistivity is between 2 ohmcms between 30 ohmcms. Polysilicon layer is patterned using techniques such as photoetching, development, etchings, to form the grid conductor 105 of MOSFET element.

Then, interlayer dielectric layer 106 is formed above grid conductor 105, as shown in Figure 1.The interlayer dielectric layer 106 is for example Can be silica (SIO2) and boron-phosphorosilicate glass (BPSG), overall thickness is between 8000 angstroms to 15000 angstroms.

Further, on interlayer dielectric layer 106 through-hole is formed by the techniques such as photoetching and etching.The through-hole exposes well region 102 and emitter region 103 at least part surface.

Further, in device surface deposited metal layer, to form the first contact 107.This first contact 107 for example by Aluminium or aluminium silicon or aluminium copper silicon composition, but not limited to this.

First contact 107 is the conductive layer that metal layer is formed by patterning, has been shown in figure 107 filling of the first contact Through-hole in interlayer dielectric layer 106, to form the source contact for reaching emitter region 103 (i.e. source region) via through-hole.It can manage Solution, the step yet form the gate contact that grid conductor 105 is reached via through-hole.

After the Facad structure of above-mentioned power semiconductor is completed, the second surface of semiconductor substrate 101 is carried out It is thinned, as shown in Figure 2.

It is, for example, to grind and corrode to be thinned in this step, until the thickness of 101 member-retaining portion of semiconductor substrate is default Thickness.It is thinned for example, machine is thinned using the routine of semi-conductor industry, bistrique model is generally 2000#~8000#.

In this embodiment, above-mentioned preset thickness is determined according to the nominal pressure resistance of power semiconductor.For nominal The preset thickness of the power semiconductor of pressure-resistant 600V, semiconductor substrate 101 is 75 microns to 85 microns, for nominal pressure resistance The preset thickness of the power semiconductor of 1200V, semiconductor substrate 101 is 125 microns to 135 microns.After being thinned, partly lead The second surface of body substrate 101 is due to mechanical reduction, and there are 0.1 micron of surface roughnesses to 1.0 micron ranges.

Then, laser treatment is carried out to the second surface of semiconductor substrate 101, to obtain flat surface and reduce defect number Amount, as shown in Figure 3.

In this step, surface planarisation processing is carried out using wafer laser processing equipment, that is, uses laser beam irradiation half The second surface of conductor substrate 101, to carry out local heat treatmet.The laser treatment condition is that optical maser wavelength is more than or equal to 532 Nanometer, preferably 1064 nanometers, 5 watts to 80 watts of average output power, spot size is 10 microns × 2 millimeters to 30 microns × 4 Millimeter.The instantaneous energy density of the laser focal spot can reach 2 joules per cms to 5 joules per cms.

Laser facula in the laser treatment can focus in the predetermined depth of semiconductor substrate 101.In processing procedure In, laser generates heat transfer and thermal diffusion process extremely fast with semiconductor substrate 101, can make semiconductor substrate 101 in moment Surface temperature in reach 1200 degrees Celsius to 1400 degrees Celsius, to realize the rearrangement of substrate material lattice.Meanwhile it should Laser treatment expels the interstitial oxygen concentration in the position section crossed by laser treatment so that in process due to temperature in substrate material Degree changes and the vacancy of the higher concentration of generation is combined the microdefect density to be formed to be greatly reduced with interstitial oxygen concentration.Further, since subtracting Thin technique causes mechanical damage to 101 surface of semiconductor substrate, by laser treatment after, surface roughness can also be eliminated, So that the second surface of semiconductor substrate 101 reverts to the surface close to mirror-smooth, i.e. it is micro- to be decreased to 0.01 for surface roughness Rice is lower, eliminates the influence that coarse substrate surface causes the ion implanting of subsequent step shadow effect.

The predetermined depth of the laser treatment is more than the depth of the buffering area formed in later step so that buffering area is located at place It manages in region, to reduce defects count caused by oxygen atom.

Then, ion implanting is carried out from the second surface of semiconductor substrate 101, in the second surface of semiconductor substrate 101 It is formed about N-type buffering area 108, as shown in Figure 4.The remainder of semiconductor substrate 101 forms N-type drift region.

In this step, carry out one or many high energy H+ ion implantings, Implantation Energy generally 100KeV extremely 1500KeV, dosage 1E12 ions it is every square centimeter to 1E13 ions it is every square centimeter between.If using multiple high energy H+ from Son injection, may be used the dosage that the dosage gradually risen either continuously decreases and the Implantation Energy gradually risen or by The Implantation Energy gradually reduced, to obtain ideal concentration distribution.The dopant used in the ion implanting is not limited to H+, Ke Yishi Selected from any one of H+, He2+ and S.

Then, ion implanting is carried out from the second surface of semiconductor substrate 101, in the second surface of semiconductor substrate 101 It is formed about p-type collecting zone 109, as shown in Figure 5.

In this step, B+ ion implantings are carried out, are then annealed, to form the p-type current collection of power semiconductor Area 109.

Then, the second contact 110 is formed on the second surface of semiconductor substrate 101, as shown in Figure 6.

In this step, by evaporation or sputtering technology, metal layer is formed on the second surface of semiconductor substrate 101, It is contacted to form contacted with p-type collecting zone 109 second.The step completes the entire technique of power semiconductor.

Fig. 7 shows the defect type and energy level of buffering area in power semiconductor.Have in the defects of substrate material more Type, wherein (oxygen is double empty by (Lacking oxygen) centers OV or the centers A that energy level is E (90K), the centers K H (195K) and V2O Position) content of E (230K) these defects is all related with the oxygen atom content in substrate material.What 90K, 195K, 230K were indicated It is K value, energy level E, H refer to energy value possessed by electron outside nucleus.

These may still served as a contrast after heat treatment with the relevant defect of oxygen content in substrate material Jing Guo certain temperature Exist in bottom material, especially the centers K H (195K).The center starts to occur in 370~400 degree Celsius range of temperature, and 450 degrees Celsius of temperatures above annealing then disappear.Research papers point out that the essence at the centers K is CiOi, be one kind by interstitial carbon The defect of atom and oxygen atom composition, concentration are higher than the concentration at the centers OV.The centers K are positively charged.When power semiconductor device When the shutdown of part is sufficiently fast, the centers K will be used as alms giver, will increase Effective Doping concentration, can instantaneously reduce hitting at PN junction Voltage is worn, the avalanche breakdown of device is caused to occur when voltage is far below Static Breakdown Voltage.

In addition, the center E (230K) some be this V2O defect by the charging state of individual and dual V2O defects It is in the semiconductor device smaller to the influence of minority carrier life time, but the leakage current of the device of the certain helium injection in the center is higher than expansion The principal element of platinum device.

Fig. 8 shows that power semiconductor carries out laser treatment to surface and do not carry out the oxygen of two kinds of situations of laser treatment The content distribution of elements figure.It can be seen that by comparison, the oxygen atom of processing region in substrate slice reduced after laser pre-treated Content, so as to reduce the defects of the buffering area subsequently formed density, can effectively improve by defect exist and lead The low-voltage breakdown Problem of Failure that power semiconductor occurs in dynamic avalanche is caused, to improve breakdown voltage and reduction Leakage current.

As described above, carrying out the laser treatment such as Fig. 3 after the second surface of semiconductor substrate is thinned.In the embodiment In, laser treatment condition be optical maser wavelength be more than or equal to 532 nanometers, preferably 1064 nanometers, 5 watts to 80 of average output power Watt, spot size is 10 microns × 3 millimeters.It is every square centimeter to 5 that the instantaneous energy density of the laser focal spot can reach erg-ten Joules per cm.After the hot spot of laser acts on semiconductor substrate second surface and predetermined depth away from second surface, Make to reach 1200~1400 DEG C in 101 surface temperature of semiconductor substrate in moment, realizes the rearrangement of silicon materials lattice, simultaneously Combined with interstitial oxygen concentration due to the vacancy of the higher concentration generated in process due to temperature change in silicon substrate material The microdefect density of formation significantly reduces, and expels the interstitial oxygen concentration in the position section crossed by laser treatment.

In subsequent steps, N-type buffering area is formed about in semiconductor substrate second surface using ion implanting.The N Type buffering area forms the Thermal donor layer of hypoxemia vacancy content.

It is to use the elements such as H+/He2+/S as dopant using the power semiconductor described in the utility model The N-type buffer layer of formation forms the centers OV or the centers A E (90K), the centers K H (195K) with lower by oxygen atom and vacancy And the defects of V2O E (230K), can effectively improve due to the centers K exist caused by power semiconductor dynamic The low-voltage breakdown Problem of Failure occurred when snowslide.The existing electric leakage of semiconductor devices after He2+ injections can be reduced simultaneously Stream, improves the junction temperature of semiconductor devices.

Further, it is reduced in advance by laser treatment before the second surface of semiconductor substrate carries out ion implanting The oxygen atom content of pretreatment zone in substrate slice.Therefore, when forming buffer layer can use lower heat treatment temperature with And heat treatment time forms Thermal donor layer, production efficiency improves.Furthermore, it is possible to but oxygen element more cheap using use cost The silicon wafer that the relatively high vertical pulling method of content (CZ) or magnetic field Czochralski method (MCZ) make, can reduce device cost.

It should be noted that herein, relational terms such as first and second and the like are used merely to a reality Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to Non-exclusive inclusion, so that process, article or equipment including a series of elements include not only those elements, but also Further include other elements that are not explicitly listed, or further includes for this process, article or the intrinsic element of equipment. In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including the element Process, there is also other identical elements in article or equipment.

It is as described above according to the embodiments of the present invention, these embodiments there is no all details of detailed descriptionthe, The specific embodiment that the utility model is only described is not limited yet.Obviously, as described above, many modification and change can be made Change.These embodiments are chosen and specifically described to this specification, is in order to preferably explain the principles of the present invention and actually to answer With to enable skilled artisan to utilize the utility model and repairing on the basis of the utility model well Change use.The utility model is limited only by the claims and their full scope and equivalents.

Claims (4)

1. a kind of power semiconductor, including：

Positioned at the Facad structure of the first surface of semiconductor substrate, the Facad structure includes well region and emitter region, the transmitting Area is located in the well region；

Positioned at the buffering area and collecting zone of the second surface of the semiconductor substrate, the collecting zone extends from the second surface It is abutted to the buffering area,

It is characterized in that, the semiconductor substrate forms the drift region of the power semiconductor, the drift region, the hair It is the first doping type to penetrate area and the buffering area, and the well region and the collecting zone are the second doping type, and described first mixes Miscellany type and second doping type are opposite each other,

Surface roughness of the second surface of the semiconductor substrate after laser treatment is less than or equal to 0.01 micron.

2. power semiconductor according to claim 1, which is characterized in that further include：It is electrically connected with the emitter region First contact, and second contacted with collecting zone electrical connection.

3. power semiconductor according to claim 1, which is characterized in that the semiconductor substrate is selected from zone-melting process (FZ), the silicon wafer that vertical pulling method (CZ) or magnetic field Czochralski method (MCZ) make.

4. power semiconductor according to claim 1, which is characterized in that first doping type is N-type and p-type In one kind, second doping type be N-type and p-type in another kind.