CN108321191A - Power semiconductor and its manufacturing method - Google Patents
Power semiconductor and its manufacturing method Download PDFInfo
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- CN108321191A CN108321191A CN201711450430.3A CN201711450430A CN108321191A CN 108321191 A CN108321191 A CN 108321191A CN 201711450430 A CN201711450430 A CN 201711450430A CN 108321191 A CN108321191 A CN 108321191A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 130
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 238000000034 method Methods 0.000 claims abstract description 57
- 230000003139 buffering effect Effects 0.000 claims abstract description 40
- 238000013532 laser treatment Methods 0.000 claims abstract description 30
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000001301 oxygen Substances 0.000 claims abstract description 16
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 5
- 230000003746 surface roughness Effects 0.000 claims description 5
- 238000004857 zone melting Methods 0.000 claims description 5
- 241000931526 Acer campestre Species 0.000 claims description 4
- 230000003287 optical effect Effects 0.000 claims description 4
- 235000007164 Oryza sativa Nutrition 0.000 claims description 3
- 235000009566 rice Nutrition 0.000 claims description 3
- 240000007594 Oryza sativa Species 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 21
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 230000007423 decrease Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 31
- 150000002500 ions Chemical class 0.000 description 18
- 239000000463 material Substances 0.000 description 9
- 125000004430 oxygen atom Chemical group O* 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000005457 optimization Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 241000209094 Oryza Species 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 230000008707 rearrangement Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 235000019592 roughness Nutrition 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 206010021143 Hypoxia Diseases 0.000 description 1
- KMWBBMXGHHLDKL-UHFFFAOYSA-N [AlH3].[Si] Chemical compound [AlH3].[Si] KMWBBMXGHHLDKL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- -1 aluminium copper silicon Chemical compound 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000571 coke Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002552 dosage form Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 208000018875 hypoxemia Diseases 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
This application discloses power semiconductor and its manufacturing methods.The method includes：Facad structure is formed in the first surface of semiconductor substrate, the Facad structure includes well region and emitter region, and the emitter region is located in the well region；The semiconductor substrate is thinned from the second surface of the semiconductor substrate, the second surface and the first surface are relative to each other；Laser treatment is carried out to the second surface of the semiconductor substrate；And buffering area and collecting zone are formed in the second surface of the semiconductor substrate, the collecting zone is extended to from the second surface and is abutted with the buffering area.This method carries out laser treatment before forming buffering area, to the second surface of semiconductor substrate, to reduce the oxygen content in the buffering area subsequently formed, further decreases defect concentration, to improve breakdown voltage and reduce leakage current, and reduces device cost.
Description
Technical field
The present invention relates to semiconductor devices, more particularly, to power semiconductor and its manufacturing method.
Background technology
Power semiconductor is widely used in electronic equipment, for example, in power amplifier as amplifying transistor or
Person is in power circuit as switching transistor.Power semiconductor includes bipolar transistor, metal-oxide semiconductor (MOS) crystalline substance
Body pipe (MOSFET) and insulated gate bipolar transistor (IGBT) etc..
IGBT has both the high input impedance and bipolar junction transistor of MOS memory (MOSFET)
The current-carrying capability of (Bipolar Junction Transistor, BJT) can simplify gate driving requirement, while enhance conducting shape
State property energy.It has many advantages, such as the frequency range of low saturation voltage, high current density, high blocking ability and up to 100kHz, therefore
Bipolar transistor during lower-wattage can be replaced to apply rapidly and the grid clip cutout silicon control rectification in higher-power applications
Body (Gate Turn-off Thyristor, GTO).
The switch mechanism of IGBT and vertical double-diffused MOS FET (VDMOSFET) are just the same.Using the grid control of MOSFET
It is made to turn on and off.IGBT is P+ layers of the drain electrode addition in power MOSFET, i.e. the collector side of IGBT is P+ layers, to increase
Add P+N knot, conductivity modulation effect is introduced in carrier drift area when work, to overcome high-pressure work and low on-resistance
Contradiction.
In the evolution of IGBT, main research topic is to improve the trade-off relation of saturation voltage and switching characteristic,
There are the optimization of gate oxidation films, the miniaturization of cellular size and optimization to reduce the major technique that saturation voltage uses, reduce and close
The new construction of resistance break, new life control method.There are N+ buffering areas, P+ current collections to reduce the major technique that fall time uses
Optimization and the new life control method of pole layer concentration and thickness, it is non-with the continuous improvement of IGBT device manufacturing technology level
Break-through (NPT) type IGBT melts chip using the high area of resistivity, and the epitaxial wafer of fictitious hosts costliness has been current IGBT devices
The main way of part production.Non- break-through (NPT) type IGBT is to pass through thinned wafer thickness, example after the completion of IGBT Facad structures
The IGBT of such as nominal pressure resistance 600V needs the thickness for being thinned to 80~85um or so, then in chip back surface ion implanting and annealing
The method of technique forms the lower PN junction of emission effciency, simultaneously because the N drift region thickness for bearing high blocking voltage is increased,
So that not will produce depletion layer penetration phenomenon under high voltages.
Further, inject/irradiate H+ in the bottom of chip to form N+ buffering areas, to reduce the thickness of drift region,
And deeper buffering area is formed in IGBT device body, improve the dv/dt characteristics of power semiconductor.However, the buffering
The formation in area generates the defect of multiple and different energy levels in the wafer, and the breakdown voltage of power semiconductor is caused to reduce and leak electricity
Stream increases.In order to reduce buffering area defect adverse effect, the method used include using area melt chip, and improve
Heat treatment temperature and time.The shortcomings that these methods is that production efficiency reduces and device cost increases.
Therefore, it is desirable to the defects count of buffering area is further reduced in power semiconductor with improve breakdown voltage and
Reduce leakage current.
Invention content
In view of this, the object of the present invention is to provide power semiconductor and its manufacturing methods, wherein buffered being formed
Laser treatment is carried out to the second surface of semiconductor substrate before area with improve breakdown voltage, reduce leakage current and reduce device at
This.
According to an aspect of the present invention, a kind of method for manufacturing power semiconductor is provided, including：In semiconductor
The first surface of substrate forms Facad structure, and the Facad structure includes well region and emitter region, and the emitter region is located at the trap
Qu Zhong；The semiconductor substrate is thinned from the second surface of the semiconductor substrate, the second surface and described the
One surface is relative to each other；Laser treatment is carried out to the second surface of the semiconductor substrate；And in the semiconductor substrate
Second surface forms buffering area and collecting zone, and the collecting zone is extended to from the second surface and abutted with the buffering area,
In, the semiconductor substrate forms the drift region of the power semiconductor, the drift region, the emitter region and described slow
It is the first doping type to rush area, and the well region and the collecting zone are the second doping type, first doping type with it is described
Second doping type is opposite each other.
Preferably, the laser treatment reduces the roughness of the second surface of the semiconductor substrate, and described in reduction
Oxygen content in buffering area.
Preferably, in the laser treatment, the instantaneous energy density of laser focal spot is 2 joules per cms to 5 cokes
Ear is every square centimeter.
Preferably, the condition of the laser treatment is：Optical maser wavelength is more than or equal to 532 nanometers, and 5 watts of average output power is extremely
80 watts, spot size is 10 microns × 2 millimeters to 30 microns × 4 millimeters.
Preferably, the depth of the laser treatment is more than the depth of the buffering area.
Preferably, the formation buffering area and the step of collecting zone, include：From the second surface of the semiconductor substrate into
The first ion implanting of row, to form the buffering area；And carry out the second ion note from the second surface of the semiconductor substrate
Enter, to form the collecting zone.
Preferably, the dopant used in the first ion implanting is selected from any one of H+, He2+ and S.
Preferably, the dopant used in the second ion implanting is B+.
Preferably, processing method further includes：Formed and the emitter region is electrically connected first contacts, and formation with it is described
Second contact of collecting zone electrical connection.
Preferably, the semiconductor substrate is to be made selected from zone-melting process (FZ), vertical pulling method (CZ) or magnetic field Czochralski method (MCZ)
Silicon wafer.
Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type
In another kind.
According to another aspect of the present invention, a kind of power semiconductor is provided, including：Positioned at the first of semiconductor substrate
The Facad structure on surface, the Facad structure include well region and emitter region, and the emitter region is located in the well region；Positioned at described
The buffering area and collecting zone of the second surface of semiconductor substrate, the collecting zone extend to and the buffering from the second surface
Area abuts, wherein the semiconductor substrate forms the drift region of the power semiconductor, the drift region, the transmitting
Area and the buffering area are the first doping type, and the well region and the collecting zone are the second doping type, first doping
Type and second doping type are opposite each other, and the second surface of the semiconductor substrate passes through laser treatment, to reduce
The roughness of the second surface of semiconductor substrate is stated, and reduces the oxygen content in the buffering area.
Preferably, power semiconductor further includes：With first contacting for emitter region electrical connection, and with the collection
Second contact of electric area's electrical connection.
Preferably, the semiconductor substrate is to be made selected from zone-melting process (FZ), vertical pulling method (CZ) or magnetic field Czochralski method (MCZ)
Silicon wafer.
Preferably, surface roughness of the second surface of the semiconductor substrate after laser treatment be 0.01 micron or
It is lower.
Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type
In another kind.
Power semiconductor according to the ... of the embodiment of the present invention and its manufacturing method, semiconductor substrate second surface into
The oxygen atom content for reducing pretreatment zone in substrate slice before row ion implanting in advance by laser treatment, so as to subtract
The defects of buffering area subsequently formed less density.This method can effectively improve by defect exist and cause power partly to be led
The low-voltage that body device occurs in dynamic avalanche punctures Problem of Failure, to improve breakdown voltage and reduce leakage current.Into
One step, which may be used the more cheap but relatively high oxygen element content vertical pulling method (CZ) or magnetic of use cost
The silicon wafer that field vertical pulling method (MCZ) makes, when can use lower heat treatment temperature and heat treatment when forming buffer layer
Between form Thermal donor layer, production efficiency improves, thus can reduce device cost.
In a preferred embodiment, N-type buffer layer is formed using any dopant in H+, He2+, S, to
Can further decrease the defects count of ion implanting introducing, for example, with it is lower by oxygen atom and vacancy formed the centers OV or
The defects of person A center E (90K), the centers K H (195K) and V2O E (230K), in a further preferred embodiment, using H+
Dopant forms N-type buffer layer, compared with He2+ injects, can inhibit leakage current present in power semiconductor, into one
Step improves the junction temperature of semiconductor devices.
Description of the drawings
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings：
Each stage in the manufacturing method of power semiconductor according to the ... of the embodiment of the present invention is shown respectively in Fig. 1 to 6
Schematic cross-section.
Fig. 7 shows the defect type and energy level of buffering area in power semiconductor.
Fig. 8 shows to carry out laser treatment to surface in the manufacturing method of power semiconductor and not carry out at laser
Manage the oxygen element content distribution map of two kinds of situations.
Specific implementation mode
Hereinafter reference will be made to the drawings is more fully described the present invention.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.
Many specific details of the present invention, such as the structure of device, material, size, processing work is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
The present invention can be presented in a variety of manners, some of them example explained below.
Each stage in the manufacturing method of power semiconductor according to the ... of the embodiment of the present invention is shown respectively in Fig. 1 to 6
Schematic cross-section.
As shown in Figure 1, having formed the Facad structure of power semiconductor in semiconductor substrate 101.It ties in the front
Structure for example includes the well region 102 being located in semiconductor substrate 101, the emitter region 103 in well region 102, is located on well region 102
The gate dielectric layer 104 and grid conductor 105, the interlayer dielectric layer 106 above grid conductor 105 and via interlayer of side
Through-hole in dielectric layer 106 contacts 107 with first that emitter region 103 is electrically connected.Gate dielectric layer 104 and the formation of grid conductor 105
Gate stack.
Semiconductor substrate 101 can be semiconductor substrate of any suitable type, such as silicon substrate, germanium silicon substrate etc..
The embodiment, semiconductor substrate 101 are, for example, doped N-type<100>The silicon wafer of crystal orientation.The semiconductor substrate 101 can be
The silicon wafer that zone-melting process (FZ), vertical pulling method (CZ) or magnetic field Czochralski method (MCZ) make, thickness is, for example, 625 microns to 675 micro-
Rice.As known to technical staff, it is suitable for the device of different resistivity using the silicon wafer that distinct methods make.Into one
Step ground, according to the resistivity of the nominal pressure resistance selection semiconductor substrate of power semiconductor.For example, the work(of nominal pressure resistance 600V
The resistivity for the semiconductor substrate 101 that rate semiconductor devices uses for 18ohmcm to 27ohmcm, nominal pressure resistance 1200V's
The resistivity for the semiconductor substrate 101 that power semiconductor uses is 45ohmcm to 55ohmcm.
Semiconductor substrate 101 includes each other relative first surface and second surface.In the first table of semiconductor substrate 101
On face Facad structure is formed using multiple steps.Preferably, before forming Facad structure, isolation structure can also be formed to limit
Determine the active area of power semiconductor.
Further, using the ion implanting executed successively, p-type trap is formed in the first surface of N-type semiconductor substrate 101
Area 102, and N-type emitter region 103 is formed in P type trap zone 102.
Further, by thermal oxide in N-type semiconductor substrate 101, the exposure of P type trap zone 102 and N-type emitter region 103
Surface forms gate dielectric layer 104.For example, the material of gate dielectric layer 104 can be silica, thickness can be between 500
Angstrom between 1500 angstroms.
Further, the thickness of the deposit polycrystalline silicon layer on gate dielectric layer 104, the polysilicon layer can be between 5000 angstroms
To between 8000 angstroms.The doping type of the polysilicon layer is N-type, and resistivity is between 2 ohmcms between 30 ohmcms.
Polysilicon layer is patterned using techniques such as photoetching, development, etchings, to form the grid conductor 105 of MOSFET element.
Then, interlayer dielectric layer 106 is formed above grid conductor 105, as shown in Figure 1.The interlayer dielectric layer 106 is for example
Can be silica (SIO2) and boron-phosphorosilicate glass (BPSG), overall thickness is between 8000 angstroms to 15000 angstroms.
Further, on interlayer dielectric layer 106 through-hole is formed by the techniques such as photoetching and etching.The through-hole exposes well region
102 and emitter region 103 at least part surface.
Further, in device surface deposited metal layer, to form the first contact 107.This first contact 107 for example by
Aluminium or aluminium silicon or aluminium copper silicon composition, but not limited to this.
First contact 107 is the conductive layer that metal layer is formed by patterning, has been shown in figure 107 filling of the first contact
Through-hole in interlayer dielectric layer 106, to form the source contact for reaching emitter region 103 (i.e. source region) via through-hole.It can manage
Solution, the step yet form the gate contact that grid conductor 105 is reached via through-hole.
After the Facad structure of above-mentioned power semiconductor is completed, the second surface of semiconductor substrate 101 is carried out
It is thinned, as shown in Figure 2.
The thining method used in this step is, for example, to grind and corrode, up to 101 member-retaining portion of semiconductor substrate
Thickness is preset thickness.For example, using semi-conductor industry routine be thinned machine be thinned, bistrique model be generally 2000#~
8000#。
In this embodiment, above-mentioned preset thickness is determined according to the nominal pressure resistance of power semiconductor.For nominal
The preset thickness of the power semiconductor of pressure-resistant 600V, semiconductor substrate 101 is 75 microns to 85 microns, for nominal pressure resistance
The preset thickness of the power semiconductor of 1200V, semiconductor substrate 101 is 125 microns to 135 microns.After being thinned, partly lead
The second surface of body substrate 101 is due to mechanical reduction, and there are 0.1 micron of surface roughnesses to 1.0 micron ranges.
Then, laser treatment is carried out to the second surface of semiconductor substrate 101, to obtain flat surface and reduce defect number
Amount, as shown in Figure 3.
In this step, surface planarisation processing is carried out using wafer laser processing equipment, that is, uses laser beam irradiation half
The second surface of conductor substrate 101, to carry out local heat treatmet.The laser treatment condition is that optical maser wavelength is more than or equal to 532
Nanometer, preferably 1064 nanometers, 5 watts to 80 watts of average output power, spot size is 10 microns × 2 millimeters to 30 microns × 4
Millimeter.The instantaneous energy density of the laser focal spot can reach 2 joules per cms to 5 joules per cms.
Laser facula in the laser treatment can focus in the predetermined depth of semiconductor substrate 101.In processing procedure
In, laser generates heat transfer and thermal diffusion process extremely fast with semiconductor substrate 101, can make semiconductor substrate 101 in moment
Surface temperature in reach 1200 degrees Celsius to 1400 degrees Celsius, to realize the rearrangement of substrate material lattice.Meanwhile it should
Laser treatment expels the interstitial oxygen concentration in the position section crossed by laser treatment so that in process due to temperature in substrate material
Degree changes and the vacancy of the higher concentration of generation is combined the microdefect density to be formed to be greatly reduced with interstitial oxygen concentration.Further, since subtracting
Thin technique causes mechanical damage to 101 surface of semiconductor substrate, by laser treatment after, surface roughness can also be eliminated,
So that the second surface of semiconductor substrate 101 reverts to the surface close to mirror-smooth, i.e. it is micro- to be decreased to 0.01 for surface roughness
Rice is lower, eliminates the influence that coarse substrate surface causes the ion implanting of subsequent step shadow effect.
The predetermined depth of the laser treatment is more than the depth of the buffering area formed in later step so that buffering area is located at place
It manages in region, to reduce defects count caused by oxygen atom.
Then, ion implanting is carried out from the second surface of semiconductor substrate 101, in the second surface of semiconductor substrate 101
It is formed about N-type buffering area 108, as shown in Figure 4.The remainder of semiconductor substrate 101 forms N-type drift region.
In this step, carry out one or many high energy H+ ion implantings, Implantation Energy generally 100KeV extremely
1500KeV, dosage 1E12 ions it is every square centimeter to 1E13 ions it is every square centimeter between.If using multiple high energy H+ from
Son injection, may be used the dosage that the dosage gradually risen either continuously decreases and the Implantation Energy gradually risen or by
The Implantation Energy gradually reduced, to obtain ideal concentration distribution.The dopant used in the ion implanting is not limited to H+, Ke Yishi
Selected from any one of H+, He2+ and S.
Then, ion implanting is carried out from the second surface of semiconductor substrate 101, in the second surface of semiconductor substrate 101
It is formed about p-type collecting zone 109, as shown in Figure 5.
In this step, B+ ion implantings are carried out, are then annealed, to form the p-type current collection of power semiconductor
Area 109.
Then, the second contact 110 is formed on the second surface of semiconductor substrate 101, as shown in Figure 6.
In this step, by evaporation or sputtering technology, metal layer is formed on the second surface of semiconductor substrate 101,
It is contacted to form contacted with p-type collecting zone 109 second.The step completes the entire technique of power semiconductor.
Fig. 7 shows the defect type and energy level of buffering area in power semiconductor.Have in the defects of substrate material more
Type, wherein (oxygen is double empty by (Lacking oxygen) centers OV or the centers A that energy level is E (90K), the centers K H (195K) and V2O
Position) content of E (230K) these defects is all related with the oxygen atom content in substrate material.What 90K, 195K, 230K were indicated
It is K value, energy level E, H refer to energy value possessed by electron outside nucleus.
These may still served as a contrast after heat treatment with the relevant defect of oxygen content in substrate material Jing Guo certain temperature
Exist in bottom material, especially the centers K H (195K).The center starts to occur in 370~400 degree Celsius range of temperature, and
450 degrees Celsius of temperatures above annealing then disappear.Research papers point out that the essence at the centers K is CiOi, be one kind by interstitial carbon
The defect of atom and oxygen atom composition, concentration are higher than the concentration at the centers OV.The centers K are positively charged.When power semiconductor device
When the shutdown of part is sufficiently fast, the centers K will be used as alms giver, will increase Effective Doping concentration, can instantaneously reduce hitting at PN junction
Voltage is worn, the avalanche breakdown of device is caused to occur when voltage is far below Static Breakdown Voltage.
In addition, the center E (230K) some be this V2O defect by the charging state of individual and dual V2O defects
It is in the semiconductor device smaller to the influence of minority carrier life time, but the leakage current of the device of the certain helium injection in the center is higher than expansion
The principal element of platinum device.
Fig. 8 shows to carry out laser treatment to surface in the manufacturing method of power semiconductor and not carry out at laser
Manage the oxygen element content distribution map of two kinds of situations.It can be seen that by comparison, reduced in substrate slice after laser pre-treated
Manage region oxygen atom content, so as to reduce the defects of the buffering area subsequently formed density, can effectively improve by
Defect exist and lead to the low-voltage breakdown Problem of Failure that power semiconductor occurs in dynamic avalanche, to improve
Breakdown voltage and reduction leakage current.
As described above, carrying out the laser treatment such as Fig. 3 after the second surface of semiconductor substrate is thinned.In the embodiment
In, laser treatment condition be optical maser wavelength be more than or equal to 532 nanometers, preferably 1064 nanometers, 5 watts to 80 of average output power
Watt, spot size is 10 microns × 3 millimeters.It is every square centimeter to 5 that the instantaneous energy density of the laser focal spot can reach erg-ten
Joules per cm.After the hot spot of laser acts on semiconductor substrate second surface and predetermined depth away from second surface,
Make to reach 1200~1400 DEG C in 101 surface temperature of semiconductor substrate in moment, realizes the rearrangement of silicon materials lattice, simultaneously
Combined with interstitial oxygen concentration due to the vacancy of the higher concentration generated in process due to temperature change in silicon substrate material
The microdefect density of formation significantly reduces, and expels the interstitial oxygen concentration in the position section crossed by laser treatment.
In subsequent steps, N-type buffering area is formed about in semiconductor substrate second surface using ion implanting.The N
Type buffering area forms the Thermal donor layer of hypoxemia vacancy content.
Using the manufacturing method of heretofore described power semiconductor, it is used as and is mixed using elements such as H+/He2+/S
Miscellaneous dosage form at N-type buffer layer have and lower the centers OV or the centers A E (90K), the centers K H formed by oxygen atom and vacancy
The defects of (195K) and V2O E (230K), can effectively improve power semiconductor caused by existing due to the centers K
The low-voltage breakdown Problem of Failure occurred in dynamic avalanche.The semiconductor devices after He2+ injections can be reduced simultaneously to exist
Leakage current, improve the junction temperature of semiconductor devices.
Further, it is reduced in advance by laser treatment before the second surface of semiconductor substrate carries out ion implanting
The oxygen atom content of pretreatment zone in substrate slice.Therefore, when forming buffer layer can use lower heat treatment temperature with
And heat treatment time forms Thermal donor layer, production efficiency improves.In addition, use cost may be used more just in the manufacturing method
The silicon wafer that suitable but relatively high oxygen element content vertical pulling method (CZ) or magnetic field Czochralski method (MCZ) makes, can reduce device
Cost.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also include other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
As described above according to the embodiment of the present invention, there is no all details of detailed descriptionthe for these embodiments, also not
Limit the specific embodiment that the invention is only described.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is in order to preferably explain the principle of the present invention and practical application, belonging to making
Technical field technical staff can utilize modification of the invention and on the basis of the present invention to use well.The present invention is only by right
The limitation of claim and its full scope and equivalent.
Claims (16)
1. a kind of method for manufacturing power semiconductor, including：
Facad structure is formed in the first surface of semiconductor substrate, the Facad structure includes well region and emitter region, the transmitting
Area is located in the well region；
The semiconductor substrate is thinned from the second surface of the semiconductor substrate, the second surface and described first
Surface is relative to each other；
Laser treatment is carried out to the second surface of the semiconductor substrate；And
Buffering area is formed in the second surface of the semiconductor substrate and collecting zone, the collecting zone extend from the second surface
It is abutted to the buffering area,
Wherein, the semiconductor substrate forms the drift region of the power semiconductor, the drift region, the emitter region and
The buffering area is the first doping type, and the well region and the collecting zone are the second doping type, first doping type
It is opposite each other with second doping type.
2. according to the method described in claim 1, wherein, the laser treatment reduces the second surface of the semiconductor substrate
Roughness, and reduce the oxygen content in the buffering area.
3. according to the method described in claim 2, wherein, in the laser treatment, the instantaneous energy density of laser focal spot is 2
Joules per cm is to 5 joules per cms.
4. according to the method described in claim 3, wherein, the condition of the laser treatment is：Optical maser wavelength is received more than or equal to 532
Rice, 5 watts to 80 watts of average output power, spot size are 10 microns × 2 millimeters to 30 microns × 4 millimeters.
5. according to the method described in claim 2, wherein, the depth of the laser treatment is more than the depth of the buffering area.
6. according to the method described in claim 1, wherein, the step of formation buffering area and collecting zone, includes：
The first ion implanting is carried out from the second surface of the semiconductor substrate, to form the buffering area；And
The second ion implanting is carried out from the second surface of the semiconductor substrate, to form the collecting zone.
7. according to the method described in claim 6, wherein, the dopant used in the first ion implanting is selected from H+, He2+
Any one of with S.
8. according to the method described in claim 6, wherein, the dopant used in the second ion implanting is B+.
9. according to the method described in claim 6, further including：Formation is contacted with first that the emitter region is electrically connected and shape
At with the collecting zone is electrically connected second contacts.
10. method according to any one of claim 1 to 9, wherein the semiconductor substrate is selected from zone-melting process
(FZ), the silicon wafer that vertical pulling method (CZ) or magnetic field Czochralski method (MCZ) make.
11. method according to any one of claim 1 to 9, wherein first doping type is in N-type and p-type
One kind, second doping type are the another kind in N-type and p-type.
12. a kind of power semiconductor, including：
Positioned at the Facad structure of the first surface of semiconductor substrate, the Facad structure includes well region and emitter region, the transmitting
Area is located in the well region；
Positioned at the buffering area and collecting zone of the second surface of the semiconductor substrate, the collecting zone extends from the second surface
It is abutted to the buffering area,
Wherein, the semiconductor substrate forms the drift region of the power semiconductor, the drift region, the emitter region and
The buffering area is the first doping type, and the well region and the collecting zone are the second doping type, first doping type
It is opposite each other with second doping type,
The second surface of the semiconductor substrate pass through laser treatment, with reduce the semiconductor substrate second surface it is coarse
Degree, and reduce the oxygen content in the buffering area.
13. power semiconductor according to claim 12, further includes：First be electrically connected with the emitter region connects
It touches, and is contacted with the second of collecting zone electrical connection.
14. power semiconductor according to claim 12, wherein the semiconductor substrate is selected from zone-melting process
(FZ), the silicon wafer that vertical pulling method (CZ) or magnetic field Czochralski method (MCZ) make.
15. power semiconductor according to claim 12, wherein the second surface of the semiconductor substrate is through too drastic
Surface roughness after light processing is 0.01 micron or lower.
16. power semiconductor according to claim 12, wherein first doping type is in N-type and p-type
One kind, second doping type are the another kind in N-type and p-type.
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