CN103730356A - Method for manufacturing back face of power semiconductor device - Google Patents
Method for manufacturing back face of power semiconductor device Download PDFInfo
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- CN103730356A CN103730356A CN201310753735.7A CN201310753735A CN103730356A CN 103730356 A CN103730356 A CN 103730356A CN 201310753735 A CN201310753735 A CN 201310753735A CN 103730356 A CN103730356 A CN 103730356A
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 45
- 239000010703 silicon Substances 0.000 claims abstract description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 238000000137 annealing Methods 0.000 claims abstract description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052796 boron Inorganic materials 0.000 claims abstract description 14
- 238000005224 laser annealing Methods 0.000 claims abstract description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 7
- 239000011574 phosphorus Substances 0.000 claims abstract description 7
- 238000002513 implantation Methods 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 claims description 3
- 241000931526 Acer campestre Species 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 10
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 238000005215 recombination Methods 0.000 abstract description 3
- 230000006798 recombination Effects 0.000 abstract description 3
- 239000000969 carrier Substances 0.000 abstract 1
- 239000013078 crystal Substances 0.000 abstract 1
- 239000002344 surface layer Substances 0.000 abstract 1
- 239000002800 charge carrier Substances 0.000 description 6
- 239000012190 activator Substances 0.000 description 3
- 238000011084 recovery Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 206010019133 Hangover Diseases 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
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Abstract
The invention relates to a method for manufacturing the back face of an IGBT device. The method at least comprises the following steps that (a) the back face of a silicon wafer with the front face structure processed completely is thinned; (b) protons H+ are injected into the back face of the silicon wafer through a high-powered ion implanter; (c) low-temperature annealing is conducted on the silicon wafer; (d) phosphorus and/or boron impurities are injected into the back face of the silicon wafer through the ion implanter; (e) a crystal lattice on the surface layer of the back face of the silicon wafer is repaired through the laser annealing technology and the impurities are activated. According to the method, a minority carrier control zone is formed by a recombination center generated by ion implantation defects, and the minority carrier lifetime is effectively shortened. When an IGBT is switched off in the forward direction, through the improvement of the recombination efficiency of carriers, the switch-off time of the IGBT is effectively shortened, power consumption of the IGBT is effectively reduced, and the method is simple, effective and convenient to popularize.
Description
Technical field
The present invention relates to semiconductor processing and manufacturing technical field, more particularly, relate to a kind of power semiconductor back side manufacture method.
Background technology
IGBT is less sub-device, and it not only has good on state characteristic, also has the numerous characteristics of power MOSFET, and as wide in easy driving, safety operation area, peak current is large, sturdy and durable etc.
The maximum constraints of IGBT turn-off speed is the minority carrier life time in N epitaxial loayer (being the base of PNP pipe).Because not being subject to external circuit, this base affects, so can not shorten IGBT switching time with external drive circuit.Stored charge in base, can cause that when IGBT turn-offs, significant delay pulse appears in current waveform, the electric current of IGBT can not be reduced to rapidly hole-recombination electric current, thereby increased turn-off power loss, and in half bridge circuit, for fear of two IGBT conducting simultaneously, also need to increase by two Dead Times between IGBT ON time, therefore, must manage to reduce minority carrier life time to shorten recombination time.
PT-IGBT(plane punch IGBT) in order to solve the contradiction of conducting voltage and switching time, conventionally need to adopt high energy electron width according to the life-span that reduces few son, to reduce, turn-off hangover electric current, but it can proton and defect thereof to minority carrier life time controlled area exert an influence.And for high pressure NPT-IGBT(non-punch through IGBT more than 1700V), for reducing forward conduction saturation voltage, need to improve the injection efficiency of back side emitter, now minority carrier life time control technology is also essential.In addition, along with RC-IGBT(is contrary, lead recently type IGBT) exploitation, although adopted FS-TRENCH(field cut-off groove) structure, IGBT itself does not need to reduce minority carrier life time, the diode that integrate in parallel with IGBT device also has the requirement of shortening minority carrier life time in the region limiting.
Therefore, need in the industry other simply and effectively to shorten the preparation method of minority carrier life time, the turn-off time of reduction IGBT device and the IGBT device of power consumption.
Summary of the invention
The object of the present invention is to provide a kind of IGBT device back side manufacture method, to shorten turn-off time and the power consumption of minority carrier life time, reduction IGBT device.
For achieving the above object, the present invention's one technical scheme is as follows:
A kind of IGBT device back side manufacture method, at least comprises the steps: a), by the silicon chip back side attenuate of Facad structure completion of processing; B), at energetic ion implanter Proton Implantation H+ for silicon chip back side; C), silicon chip is carried out to process annealing; D), at silicon chip back side, with ion implantor, inject phosphorus and/or boron impurity; E), with laser annealing technique, complete the lattice reparation on silicon chip back side top layer, and activator impurity.
Preferably, step b) specifically comprises: the injection of H+ proton is carried out with million electro-volt ion implantor in the back side at silicon chip, and implantation dosage is 10
12cm
-2to 10
15cm
-2between, the degree of depth reaches more than ten microns.
Preferably, silicon chip back side is carried out to twice described in proton inject, Implantation Energy is respectively 1.0MeV and 600KeV, implantation dosage is all 1 × 10
12cm
-2.
Preferably, steps d) in, in silicon chip back side 1-2 micrometer depth, with ion implantor, inject: the impurity of phosphorus and boron; Or, boron impurity.
Preferably, step e) in, with laser annealing technique, process silicon chip back side, make that impurity in silicon chip back side 1-2 micrometer depth is all or part of activates to recover lattice.
The back side manufacture method of IGBT device provided by the invention, the complex centre that utilizes Implantation defect to produce forms less sub-controlled area at silicon chip back side, can effectively reduce minority carrier life time; When IGBT forward turn-offs, it,, by improving the combined efficiency of charge carrier, effectively reduces turn-off time and the power consumption of IGBT, and the method is simple and effective, is applicable to the manufacturing of multiple power device in this area.
Accompanying drawing explanation
Fig. 1 illustrates the IGBT device back side manufacture method schematic flow sheet that first embodiment of the invention provides;
Fig. 2 illustrates the IGBT device architecture schematic diagram that IGBT device back side manufacture method that the above embodiment of the present invention provides obtains.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.
As shown in Figure 1, the IGBT device back side manufacture method that first embodiment of the invention provides, comprises the steps:
Step S10, by the silicon chip back side attenuate of Facad structure completion of processing.
Wherein, Facad structure at least comprises emitter and the grid of IGBT device.
Step S11, at energetic ion implanter Proton Implantation H+ for silicon chip back side.
Because protonatomic mass is light, Implantation penetration power is strong, the present invention is based on this characteristic and adopted the mode of Proton Implantation, and particularly, this step specifically comprises: the injection of H+ proton is carried out with million electro-volt ion implantor in the back side at silicon chip, and implantation dosage is 10
12cm
-2to 10
15cm
-2between, the degree of depth reaches more than ten microns.
Further, in this step, can carry out continuously twice proton injection to silicon chip back side, Implantation Energy is respectively 1.0MeV and 600KeV, and implantation dosage is all 1 × 10
12cm
-2.
Step S12, silicon chip is carried out to process annealing.
Particularly, can at the temperature of 250 ℃-300 ℃, carry out process annealing.Annealing time is for example 30 minutes, and annealing temperature is for example 300 ℃.
Process annealing makes proton and the residual defect thereof injected form charge carrier complex centre.
Step S13, ion implantor injects phosphorus and/or boron impurity for the silicon chip back side.
Particularly, in this silicon chip back side 1-2 micrometer depth, with ion implantor, inject: the impurity of phosphorus and boron; Or, boron impurity.
Under preferable case, implanted dopant is boron impurity, and Implantation Energy is 60KeV, and implantation dosage is 5E14cm
-2.
Step S14, with laser annealing technique, complete the lattice reparation on silicon chip back side top layer, and activator impurity.
In this step S14, with laser annealing technique, process silicon chip back side, make all or part of the activation with recovery lattice of impurity in silicon chip back side 1-2 micrometer depth.Wherein, laser wavelength range can be 500-600nm, is preferably 532nm.
After this step, can form the backside collector of IGBT device, it forms IGBT device with the emitter of front side of silicon wafer together with grid.
Should be understood that laser annealing has following features: suitably select optical maser wavelength can control the annealing degree of depth of silicon chip.In this embodiment, annealing severity control, in the degree of depth of 1-2 micron, makes the doping ion implantation damage in this degree of depth obtain desirable recovery, and ion implanted impurity is activated fully, to form the back side collector junction of high injection efficiency; And there is residual defect after the temperature action of the proton of the suitable degree of depth and 250 ℃-300 ℃ and can not be subject to the impact of laser annealing, and guaranteed the existence in charge carrier complex centre, play the effect of minority carrier life time control.
Therefore, by the laser annealing technique in this step, can repair Implantation defect activator impurity in 1-2 micron, form the backside collector of high injection efficiency, can not exert an influence to the proton in minority carrier life time controlled area and defect thereof again.When IGBT forward turn-offs, charge carrier combined efficiency can effectively be improved in minority carrier life time controlled area, shortens minority carrier life time, reduces turn-off time and power consumption; When IGBT forward conduction, the backside collector of high injection efficiency can obtain again low conducting voltage, reduces the on-state power consumption of IGBT.
The preferred implementation of the above embodiment of the present invention and adopt parameter be, after the Facad structure of silicon chip is all machined, by wafer thinning to certain thickness; Silicon chip back side is carried out to twice proton injection with energetic ion implanter, energy is for being respectively 1.0MeV and 600KeV, and implantation dosage is all 1 × 10
12cm
-2; At 300 ℃ of temperature, carry out the process annealing of 30 minutes, make Implantation proton and its residual defect form charge carrier complex centre; At silicon chip back side boron ion implantation, energy is 60KeV, and dosage is 5E14cm-2; Finally with 532nm laser, silicon chip back side is annealed, the defect of injecting is repaired, and boron is activated.
The back side manufacture method of the IGBT device providing according to the above embodiment of the present invention, the Facad structure of its silicon chip adopting completion of processing, as shown in Figure 2, its Facad structure at least comprises emitter 1 and grid 3, by back side Proton Implantation, process annealing, back side implanted dopant and the laser annealing technique step of carrying out successively above, can obtain the degree of depth at silicon chip back side and reach more than ten microns few sub-controlled areas 4, and in the 0.5um of top layer, obtain P overleaf
+layer 2.
The back side manufacture method of the IGBT device that the above embodiment of the present invention provides, the complex centre that utilizes Implantation defect to produce forms less sub-controlled area at silicon chip back side, can effectively reduce minority carrier life time; When IGBT forward turn-offs, it,, by improving the combined efficiency of charge carrier, effectively reduces turn-off time and the power consumption of IGBT, and the method is simple and effective, is applicable to the manufacturing of multiple power device in this area.
Above-described is only the preferred embodiments of the present invention; described embodiment is not in order to limit scope of patent protection of the present invention; therefore the equivalent structure that every utilization specification of the present invention and accompanying drawing content are done changes, and in like manner all should be included in protection scope of the present invention.
Claims (10)
1. an IGBT device back side manufacture method, at least comprises the steps:
A), by the silicon chip back side attenuate of Facad structure completion of processing;
B), at energetic ion implanter Proton Implantation H+ for described silicon chip back side;
C), described silicon chip is carried out to process annealing;
D), at described silicon chip back side, with ion implantor, inject phosphorus and/or boron impurity;
E), with laser annealing technique, complete the lattice reparation on described silicon chip back side top layer, and activate described impurity.
2. manufacture method according to claim 1, is characterized in that, described step b) specifically comprises: the injection of H+ proton is carried out with million electro-volt ion implantor in the back side at described silicon chip, and implantation dosage is 10
12cm
-2to 10
15cm
-2between, the degree of depth reaches more than ten microns.
3. manufacture method according to claim 2, is characterized in that, described step b) in, described silicon chip back side is carried out to twice described in proton inject, Implantation Energy is respectively 1.0MeV and 600KeV, implantation dosage is all 1 × 10
12cm
-2.
4. manufacture method according to claim 1, is characterized in that, described step is carried out process annealing with 250 ℃-300 ℃ in c).
5. manufacture method according to claim 4, is characterized in that, described step c) in, annealing time is 30 minutes, annealing temperature is 300 ℃.
6. manufacture method according to claim 1, is characterized in that, described steps d) in, in described silicon chip back side 1-2 micrometer depth, with ion implantor, inject:
The impurity of phosphorus and boron; Or,
Boron impurity.
7. manufacture method according to claim 6, is characterized in that, described steps d) in, implanted dopant is boron impurity, and Implantation Energy is 60KeV, and implantation dosage is 5E14cm
-2.
8. manufacture method according to claim 1, is characterized in that, described step e) in, with laser annealing technique, process described silicon chip back side, make that impurity in described silicon chip back side 1-2 micrometer depth is all or part of activates to recover lattice.
9. manufacture method according to claim 8, is characterized in that, described optical maser wavelength is 500-600nm.
10. according to the manufacture method described in any one in claim 1 to 9, it is characterized in that, described Facad structure at least comprises emitter and grid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310753735.7A CN103730356A (en) | 2013-12-31 | 2013-12-31 | Method for manufacturing back face of power semiconductor device |
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|---|---|---|---|
| CN201310753735.7A CN103730356A (en) | 2013-12-31 | 2013-12-31 | Method for manufacturing back face of power semiconductor device |
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| Publication Number | Publication Date |
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| CN201310753735.7A Pending CN103730356A (en) | 2013-12-31 | 2013-12-31 | Method for manufacturing back face of power semiconductor device |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157569A (en) * | 2014-08-26 | 2014-11-19 | 清华大学 | Technology for manufacturing fast recovery diode |
| CN104637803A (en) * | 2015-01-30 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | Process method for improving IGBT (Insulated Gate Bipolar Transistor) back metallization |
| CN107564806A (en) * | 2016-07-01 | 2018-01-09 | 英飞凌科技股份有限公司 | Reduce the impurity concentration in semiconductor body |
| CN108321191A (en) * | 2017-12-27 | 2018-07-24 | 杭州士兰集成电路有限公司 | Power semiconductor and its manufacturing method |
| CN109216472A (en) * | 2018-08-28 | 2019-01-15 | 全球能源互联网研究院有限公司 | fast recovery diode and preparation method thereof |
| CN109411344A (en) * | 2017-08-18 | 2019-03-01 | 英飞凌科技股份有限公司 | Semiconductor devices and manufacture including CZ semiconductor body include the method for the semiconductor devices of CZ semiconductor body |
| CN109712886A (en) * | 2018-12-17 | 2019-05-03 | 成都森未科技有限公司 | A kind of back side processing technology of power semiconductor |
| WO2020043094A1 (en) * | 2018-08-28 | 2020-03-05 | 全球能源互联网研究院有限公司 | Semiconductor device and preparation method therefor, and fast recovery diode and preparation method therefor |
| CN116072530B (en) * | 2022-12-01 | 2024-01-19 | 北京核力同创科技有限公司 | Preparation method of FS-IGBT back electrode |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157569A (en) * | 2014-08-26 | 2014-11-19 | 清华大学 | Technology for manufacturing fast recovery diode |
| CN104157569B (en) * | 2014-08-26 | 2017-06-30 | 清华大学 | Fast recovery diode method of manufacturing technology |
| CN104637803A (en) * | 2015-01-30 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | Process method for improving IGBT (Insulated Gate Bipolar Transistor) back metallization |
| CN107564806A (en) * | 2016-07-01 | 2018-01-09 | 英飞凌科技股份有限公司 | Reduce the impurity concentration in semiconductor body |
| CN109411344A (en) * | 2017-08-18 | 2019-03-01 | 英飞凌科技股份有限公司 | Semiconductor devices and manufacture including CZ semiconductor body include the method for the semiconductor devices of CZ semiconductor body |
| CN109411344B (en) * | 2017-08-18 | 2024-01-02 | 英飞凌科技股份有限公司 | Semiconductor device comprising a CZ semiconductor body and method for manufacturing a semiconductor device comprising a CZ semiconductor body |
| CN108321191A (en) * | 2017-12-27 | 2018-07-24 | 杭州士兰集成电路有限公司 | Power semiconductor and its manufacturing method |
| CN109216472A (en) * | 2018-08-28 | 2019-01-15 | 全球能源互联网研究院有限公司 | fast recovery diode and preparation method thereof |
| WO2020043094A1 (en) * | 2018-08-28 | 2020-03-05 | 全球能源互联网研究院有限公司 | Semiconductor device and preparation method therefor, and fast recovery diode and preparation method therefor |
| CN109712886A (en) * | 2018-12-17 | 2019-05-03 | 成都森未科技有限公司 | A kind of back side processing technology of power semiconductor |
| CN116072530B (en) * | 2022-12-01 | 2024-01-19 | 北京核力同创科技有限公司 | Preparation method of FS-IGBT back electrode |
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