CN112103330A - Multi-peak buffer layer structure on back surface of power device, IGBT chip and FRD chip - Google Patents
Multi-peak buffer layer structure on back surface of power device, IGBT chip and FRD chip Download PDFInfo
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- CN112103330A CN112103330A CN201910521437.2A CN201910521437A CN112103330A CN 112103330 A CN112103330 A CN 112103330A CN 201910521437 A CN201910521437 A CN 201910521437A CN 112103330 A CN112103330 A CN 112103330A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 239000000463 material Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005468 ion implantation Methods 0.000 claims description 21
- 230000000737 periodic effect Effects 0.000 claims description 10
- 230000007423 decrease Effects 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 15
- 230000008569 process Effects 0.000 abstract description 13
- 238000005516 engineering process Methods 0.000 abstract description 5
- 238000012545 processing Methods 0.000 abstract description 5
- 238000011161 development Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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Abstract
The invention provides a back multi-peak buffer layer structure of a power device, an IGBT chip and an FRD chip, wherein the back multi-peak buffer layer structure of the power device comprises: the semiconductor power device comprises an N-type semiconductor substrate material (100), a surface boundary (101) of the back surface of the power device and a buffer layer arranged between the N-type semiconductor substrate material (100) and the surface boundary (101); the buffer layer includes: the back multi-peak buffer layer structure, the IGBT chip and the FRD chip provided by the invention reduce the whole thermal process of the processing technology of the power device and greatly improve the reliability of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a multi-peak buffer layer structure on the back of a power device, an IGBT chip and an FRD chip.
Background
With the continuous and high-speed development of economy, the energy crisis is gradually serious, the supply and demand are in serious contradiction, and the development of energy-saving industry and new energy industry is urgent. The power electronic device plays an important role in energy conservation, is a key component for mechanical automation and intelligent control, and is a semiconductor device for saving electric energy. Therefore, the vigorous development of design and manufacture of power electronic power devices and development and application of modules are important measures for saving electric energy.
The power devices such as IGBT and FRD chips are provided with a buffer layer structure on the back of the chip for optimizing the parameters of reverse voltage resistance and forward conduction voltage drop of the chip, the existing back buffer layer is formed by phosphorus elements, a high-temperature long-time junction pushing process is needed after injection is carried out on the back of the chip, and the process temperature is high, so that the process needs to be carried out in the former step of the whole process flow of the chip, but along with different chip voltage grades, particularly the IGBT and the FRD chips below 1200V, the whole thickness of the chip is thin, after the junction pushing is carried out by using the traditional phosphorus elements, the subsequent process steps can be influenced by a sheet, the process difficulty is increased, and meanwhile, the high-temperature junction pushing process can also cause the crystal lattice change of the whole chip.
Disclosure of Invention
The invention provides a multi-peak buffer layer structure on the back of a power device, an IGBT chip and an FRD chip, aiming at the problems of high process difficulty and low reliability of the whole thermal process of the prior art.
A power device backside multi-peak buffer layer structure includes:
the semiconductor power device comprises an N-type semiconductor substrate material (100), a surface boundary (101) of the back surface of the power device and a buffer layer arranged between the N-type semiconductor substrate material (100) and the surface boundary (101);
the buffer layer includes: and the N-type doped region is formed by at least two times of ion implantation, wherein one time of ion implantation forms one N-type doped region.
Further, the ions include: any one of the first periodic elements of the periodic table of elements.
Further, the number of the N-type doped regions increases with the increase of the rated voltage.
Further, the number of the N-type doped regions includes:
when the rated voltage of the device is 1200V, the number of the formed N-type doped regions is 2;
when the rated voltage of the device is 1700V, the number of the formed N-type doped regions is 2-3;
when the rated voltage of the device is 3300V, the number of the formed N-type doped regions is 3-4;
when the rated voltage of the device is 4500V, the number of the formed N-type doped regions is 4-5;
when the rated voltage of the device is 6500V, the number of the formed N-type doped regions is 5-6; one kind of (1).
Further, the concentration of the N-type doped region increases sequentially with the increase of the ion implantation times.
Further, the distance from the N-type doped region to the surface boundary (101) is reduced sequentially as the ion implantation times are increased.
Further, when the rated voltage of the device is 1200V and the number of the formed N-type doped regions is 2,
the farthest distance from the N-type doped region to the surface boundary (101) is 5-8um, and the highest doping concentration is 10-100 times of the bulk concentration of the N-type semiconductor substrate material (100).
Further, when the rated voltage of the device is 1700V and the number of the formed N-type doped regions is 2-3,
the farthest distance from the N-type doped region to the surface boundary (101) is 7-12um, and the highest doping concentration is 10-100 times of the bulk concentration of the N-type semiconductor substrate material (100).
Further, when the rated voltage of the device is 3000V, and the number of the formed N-type doped regions is 3-4,
the farthest distance from the N-type doped region to the surface boundary (101) is 10-20um, and the highest doping concentration is 10-150 times of the bulk concentration of the N-type semiconductor substrate material (100).
Further, when the rated voltage of the device is 4500V and the number of the formed N-type doped regions is 4-5,
the farthest distance from the N-type doped region to the surface boundary (101) is 15-25um, and the highest doping concentration is 10-200 times of the bulk concentration of the N-type semiconductor substrate material (100).
Further, when the rated voltage of the device is 6500V and the number of the formed N-type doped regions is 5-6,
the farthest distance from the N-type doped region to the surface boundary (101) is 15-30um, and the highest doping concentration is 10-200 times of the bulk concentration of the N-type semiconductor substrate material (100).
The back of the IGBT chip is provided with the multi-peak buffer layer structure.
The back of the FRD chip is provided with the multi-peak buffer layer structure.
Compared with the closest prior art, the technical scheme provided by the invention has the following beneficial effects:
1. the multi-peak buffer layer structure on the back surface of the power device comprises an N-type doped region with donor formed by the first periodic element for many times, so that the concentration difference of the buffer layer structure is reduced, and the safe working area of the device is optimized.
2. According to the back multi-peak buffer layer structure of the power device, the heating step of the back multi-peak buffer layer structure is moved backwards under the condition that other processing technologies are hardly influenced, the overall thermal process of the processing technology of the power device is reduced, and the reliability of the device is improved.
Drawings
FIG. 1: the buffer layer structure schematic diagram of the embodiment of the invention with the number of N-type doped regions being 2;
FIG. 2: the buffer layer structure schematic diagram of the embodiment of the invention, in which the number of the N-type doped regions is 3, is provided;
FIG. 3: the buffer layer structure schematic diagram of the embodiment of the invention with the number of N-type doped regions being 4;
FIG. 4: the buffer layer structure schematic diagram of the embodiment of the invention with the number of N-type doped regions being 5;
FIG. 5: the buffer layer structure of the embodiment of the invention is schematically represented, wherein the number of the N-type doped regions is 6.
Detailed Description
The technical solutions provided by the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the present invention, and not all of it.
Example 1
A power device backside multi-peak buffer layer structure includes:
an N-type semiconductor substrate material 100; a surface boundary 101 that is the back of the N-type semiconductor liner material; n-type doped regions 201 and 206 within the N-type semiconductor substrate material 100,
the number of the N-type doped regions is more than or equal to 2 and less than or equal to 6, and the N-type doped regions are formed by adopting first periodic elements of a periodic table of elements to carry out ion implantation.
Power devices such as IGBTs or FRD chips, the surface confinement 101 of the back side of the N-type semiconductor substrate material is required to have the carrier concentration and diffusion depth required to prevent the depletion layer from punch-through. Inside the N-type semiconductor material 100, an N-type doped region having an impurity concentration higher than that of the N-type semiconductor material 100 is formed in order to suppress diffusion of a depletion layer. From region 201 to region 206, the N-type doping concentration increases in sequence, and the N-type doping region decreases in sequence from the surface boundary 101 of the back surface of the N-type semiconductor material. In addition, the method for forming the N-type doped region of the N-type buffer layer comprises the following steps: at relatively low accelerating voltages, donors are formed by the first periodic element of the periodic table of elements that gives a deeper range.
However, the number of N-type doped regions formed by ion implantation in the N-type semiconductor material 100 varies according to the rated voltage of the power device.
Example 2
The power device with the rated voltage of 1200V provided by the invention has the advantages that the number of N-type doped regions for forming the buffer layer is 2, the concentration of the N-type doped regions is sequentially increased along with the increase of the ion implantation times, the highest doped concentration is preferably 10 times to 100 times of the concentration of 100 bodies of an N-type semiconductor substrate material, the distance from the N-type doped regions to a surface boundary 101 is sequentially reduced along with the increase of the ion implantation times, and the farthest distance is preferably 5-8 um.
The power device with the rated voltage of 1700V provided by the invention has the advantages that the number of N-type doped regions for forming the buffer layer is 2-3, the concentration of the N-type doped regions is sequentially increased along with the increase of the ion implantation times, the highest doped concentration is preferably 10-100 times of the concentration of 100 bodies of the N-type semiconductor substrate material, the distance from the N-type doped regions to the surface boundary 101 is sequentially reduced along with the increase of the ion implantation times, and the farthest distance is preferably 7-12 um.
The power device with the rated voltage of 3300V provided by the invention is used for forming the buffer layer, the number of N-type doped regions is 3-4, wherein the concentration of the N-type doped regions is sequentially increased along with the increase of the ion implantation times, the highest doped concentration is preferably 10-150 times of the bulk concentration of an N-type semiconductor substrate material 100, the distance from the N-type doped region to a surface boundary 101 is sequentially reduced along with the increase of the ion implantation times, and the farthest distance is preferably 10-20 um.
The power device with the rated voltage of 4500V provided by the invention has the advantages that the number of N-type doped regions for forming the buffer layer is 4-5, the concentration of the N-type doped regions is sequentially increased along with the increase of the ion implantation times, the highest doped concentration is preferably 10-200 times of the bulk concentration of an N-type semiconductor substrate material 100, the distance from the N-type doped region to a surface boundary 101 is sequentially reduced along with the increase of the ion implantation times, and the farthest distance is preferably 15-25 um.
The power device with the rated voltage of 6500V provided by the invention is used for forming a buffer layer, the number of N-type doped regions is 5-6, wherein the concentration of the N-type doped regions is sequentially increased along with the increase of the ion implantation times, the highest doped concentration is preferably 10-200 times of the bulk concentration of an N-type semiconductor substrate material 100, the distance from the N-type doped region to a surface boundary 101 is sequentially reduced along with the increase of the ion implantation times, and the farthest distance is preferably 15-30 um.
The preparation method of the back multi-peak buffer layer structure of the power device provided by the invention comprises the following steps:
1) thinning the back surface of the power device, and when the voltage grade is 1200V to 4500V, the thickness range left by thinning is 100um to 600 um;
2) carrying out a plurality of times of ion implantation processes with different energies on the back of the power device by using a first periodic element to form an N-type doped region, wherein the implantation energy range is 0.1MeV to 1.5MeV, and the implantation metering range is 1e12/cm2 to 1e14/cm 2;
3) and carrying out an annealing process to form the multi-peak buffer layer structure on the back surface of the power device, wherein the temperature range is 200-600 ℃.
The back multi-peak buffer layer structure of the power device can enable the forming steps of the back multi-peak buffer layer structure to be moved backwards under the condition that other processing technologies are hardly influenced, so that the overall thermal process of the processing technology of the power device is reduced, and the reliability of the device is improved; and the concentration difference of the buffer layer structure can be reduced, and the safe working area of the device is optimized.
Example 3
The back of the IGBT chip is provided with the multi-peak buffer layer structure.
Example 4
The back of the FRD chip is provided with the multi-peak buffer layer structure.
The above description is only exemplary of the invention and should not be taken as limiting the invention, as any modification, equivalent replacement, or improvement made within the spirit and principle of the invention is intended to be covered by the appended claims.
Claims (13)
1. A power device backside multi-peak buffer layer structure, the structure comprising:
the semiconductor power device comprises an N-type semiconductor substrate material (100), a surface boundary (101) of the back surface of the power device and a buffer layer arranged between the N-type semiconductor substrate material (100) and the surface boundary (101);
the buffer layer includes: and the N-type doped region is formed by at least two times of ion implantation, wherein one time of ion implantation forms one N-type doped region.
2. The power device backside multi-peak buffer layer structure of claim 1, wherein the ions comprise: any one of the first periodic elements of the periodic table of elements.
3. The backside multi-peak buffer layer structure of claim 1, wherein the number of N-type doped regions increases with increasing voltage rating.
4. The backside multi-peak buffer layer structure of claim 3, wherein the number of N-type doped regions comprises:
when the rated voltage of the device is 1200V, the number of the formed N-type doped regions is 2;
when the rated voltage of the device is 1700V, the number of the formed N-type doped regions is 2-3;
when the rated voltage of the device is 3300V, the number of the formed N-type doped regions is 3-4;
when the rated voltage of the device is 4500V, the number of the formed N-type doped regions is 4-5;
when the rated voltage of the device is 6500V, the number of the formed N-type doped regions is 5-6;
one kind of (1).
5. The backside multi-peak buffer layer structure of claim 4, wherein the concentration of the N-type doped region increases sequentially with the number of ion implantations.
6. The backside multi-peak buffer layer structure of claim 5, wherein the distance from the N-type doped region to the surface boundary (101) decreases sequentially with increasing number of ion implantations.
7. The backside multi-peak buffer layer structure of claim 4, wherein when the rated voltage of the device is 1200V and the number of N-type doped regions formed is 2,
the farthest distance from the N-type doped region to the surface boundary (101) is 5-8um, and the highest doping concentration is 10-100 times of the bulk concentration of the N-type semiconductor substrate material (100).
8. The backside multi-peak buffer layer structure of claim 4, wherein when the rated voltage of the device is 1700V and the number of N-type doped regions formed is 2-3,
the farthest distance from the N-type doped region to the surface boundary (101) is 7-12um, and the highest doping concentration is 10-100 times of the bulk concentration of the N-type semiconductor substrate material (100).
9. The backside multi-peak buffer layer structure of claim 4, wherein when the rated voltage of the device is 3300V and the number of N-type doped regions formed is 3-4,
the farthest distance from the N-type doped region to the surface boundary (101) is 10-20um, and the highest doping concentration is 10-150 times of the bulk concentration of the N-type semiconductor substrate material (100).
10. The backside multi-peak buffer layer structure of claim 4, wherein when the rated voltage of the device is 4500V and the number of N-type doped regions formed is 4-5,
the farthest distance from the N-type doped region to the surface boundary (101) is 15-25um, and the highest doping concentration is 10-200 times of the bulk concentration of the N-type semiconductor substrate material (100).
11. The backside multi-peak buffer layer structure of claim 4, wherein when the rated voltage of the device is 6500V and the number of N-type doped regions formed is 5-6,
the farthest distance from the N-type doped region to the surface boundary (101) is 15-30um, and the highest doping concentration is 10-200 times of the bulk concentration of the N-type semiconductor substrate material (100).
12. An IGBT chip, characterized in that, the IGBT chip back has the multiple peak buffer layer structure as any one of claims 1-11.
13. An FRD chip, wherein the back surface of the IGBT chip is provided with a multi-peak buffer layer structure as defined in any one of claims 1 to 11.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910521437.2A CN112103330A (en) | 2019-06-17 | 2019-06-17 | Multi-peak buffer layer structure on back surface of power device, IGBT chip and FRD chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910521437.2A CN112103330A (en) | 2019-06-17 | 2019-06-17 | Multi-peak buffer layer structure on back surface of power device, IGBT chip and FRD chip |
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| CN112103330A true CN112103330A (en) | 2020-12-18 |
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| CN201910521437.2A Pending CN112103330A (en) | 2019-06-17 | 2019-06-17 | Multi-peak buffer layer structure on back surface of power device, IGBT chip and FRD chip |
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