CN103839804A - Preparation method of electric field blocking type IGBT structure - Google Patents
Preparation method of electric field blocking type IGBT structure Download PDFInfo
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- CN103839804A CN103839804A CN201310086227.8A CN201310086227A CN103839804A CN 103839804 A CN103839804 A CN 103839804A CN 201310086227 A CN201310086227 A CN 201310086227A CN 103839804 A CN103839804 A CN 103839804A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 230000005684 electric field Effects 0.000 title claims abstract description 16
- 230000000903 blocking effect Effects 0.000 title abstract description 3
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 6
- 239000010931 gold Substances 0.000 claims abstract description 6
- 229910052737 gold Inorganic materials 0.000 claims abstract description 6
- 239000011248 coating agent Substances 0.000 claims description 32
- 238000000576 coating method Methods 0.000 claims description 32
- 238000002513 implantation Methods 0.000 claims description 29
- 238000000137 annealing Methods 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000004857 zone melting Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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Abstract
The invention discloses a preparation method of an electric field blocking type IGBT structure, and belongs to the technical field of semiconductor power devices. The preparation method comprises the steps of selecting an N + single chip as an N + type substrate, sequentially forming a first epitaxial layer and a second epitaxial layer on the N + type substrate by an epitaxial method, and sequentially forming a P + base region, an N + emitter region, a grid oxide layer, a grid and an emitter on the epitaxial layer; thinning the back of the N + type substrate, removing part of the first epitaxial layer to form an N + type buffer layer, wherein the second epitaxial layer is an N-base region; and forming a P + collector layer on the back surface of the N + type buffer layer by an ion implantation method, and then growing a back gold metal layer on the P + collector layer, wherein the thickness of the N + type buffer layer is 5-35 μm, and the resistivity of the N + type buffer layer is 1-10 omega cm. The invention can make the thickness of the N-base region thinner, thereby reducing the turn-on voltage and turn-off time of the IGBT.
Description
Technical field
The invention belongs to semiconductor power device technology field, particularly a kind of preparation method of electric field blocking-up type IGBT structure.
Background technology
Igbt (IGBT) is widely applied in power electronic system as power switch.Conduction voltage drop and turn-off time are to affect the key parameter of IGBT under in working order.Conduction voltage drop is lower, and the power loss of IGBT under conducting state is less.Turn-off time is less, and IGBT is lower from being conducting to power loss the handoff procedure of shutoff.Under conducting state, charge carrier injects and forms a large amount of charge carrier (electronics and hole) in IGBT N-base from positive MOS raceway groove and backside collector, thereby reduces the resistance of base and then its conduction voltage drop is reduced.On the other hand, from the handoff procedure that is conducting to shutoff, the charge carrier of N-base storage need to be removed completely, can reduce the turn-off time by the carrier concentration that reduces the width of base or reduce in base.
The preparation of IGBT comprises the formation of substrate, positive technique and back process.In IGBT preparation technology, first form positive PN junction, gate electrode and emitter pattern by positive technique, be then grinding and the corrosion at the back side.According to the difference of the structure of device and the electric pressure of application, the Si substrate thickness after final attenuate is also different.Generally adopt epitaxial substrate for punch IGBT, extension N+ resilient coating and N-base layer successively on P+ substrate.P+ substrate after attenuate is as P+ collector region.Because the doping content of back side P+ collector electrode is larger, punch IGBT has lower conduction voltage drop, but its turn-off time is larger.Generally adopt light dope N-type zone melting single-crystal substrate for non-punch device, after attenuate, collector electrode is by the method preparation of Implantation overleaf.Collector electrode doping content can accurately be controlled, generally will be lower than the same terms punch IGBT.Under identical blocking voltage, non-punch through IGBT has thicker base thickness, and therefore its conduction voltage drop is relatively high.
Electric field blocking-up type IGBT have advantages of punch and non-punch through IGBT the two, its substrate adopts light dope N-type zone melting single-crystal substrate, is first N-type Implantation (for example P ion) annealing formation one deck N+ resilient coating attenuate after.Then be that P type Implantation (for example B ion) annealing form collector layer.The introducing of N+ resilient coating can make the width of N-type base become less, thereby has less conduction voltage drop and turn-off time.The thickness of N+ resilient coating is subject to the energy of Implantation and the restriction of annealing temperature, and generally its thickness is less than 2 μ m.If prepare thicker N+ type resilient coating, to adopt expensive energetic ion injection device and laser annealing apparatus, this has increased manufacturing cost.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of preparation method of electric field blocking-up type IGBT structure, has solved the problem of preparing thicker N+ type resilient coating technical sophistication in prior art.
For solving the problems of the technologies described above, the invention provides a kind of preparation method of electric field blocking-up type IGBT structure, comprise the steps:
Select N+ single-chip as N+ type substrate;
Front at described N+ type substrate forms the first epitaxial loayer and the second epitaxial loayer successively by the method for extension;
On described epitaxial loayer, form successively P+ base, N+ emitter region, grid oxic horizon, grid and emitter;
By the thinning back side of described N+ type substrate, remove described the first epitaxial loayer of part, form N+ type resilient coating, described the second epitaxial loayer is N-base;
The back side at described N+ type resilient coating forms P+ collector layer by the method for Implantation;
Growth back of the body gold metal layer on described P+ collector layer.
Further, described N+ type buffer layer thickness is 5-35 μ m, and the resistivity of described N+ type resilient coating is 1 – 10 Ω cm.
Preferably, described N+ type buffer layer thickness is 10-30 μ m.
Further, the thickness of described N-base is 50-200 μ m, and the resistivity of described N-base is 30 – 100 Ω cm.
Further, the resistivity of described N+ type substrate is 0.01 – 0.001 Ω cm.
Further, after described formation the first epitaxial loayer, after Implantation and high annealing, then form described the second epitaxial loayer;
Further, while forming described the second epitaxial loayer, the dosage of described Implantation is 1e11/cm
2– 1e13/cm
2.
Further, in described formation P+ collector layer, the dosage of described Implantation is 1e12/cm
2– 1e16/cm
2.
Further, in described formation P+ collector layer, the ion of described Implantation is B or BF2.
Further, in described formation P+ collector layer, the energy of described Implantation is 20KeV-100KeV.
The preparation method of a kind of electric field blocking-up type IGBT structure provided by the invention, in preparing thicker N+ type resilient coating, can make the thickness of N-base become thinner, thereby reduces conducting voltage and the turn-off time of IGBT.In addition, in preparation technology, this method adopts epitaxial substrate, and preparation method is simple, and is convenient to integrated.
Accompanying drawing explanation
A kind of electric field blocking-up type IGBT structure that Fig. 1 provides for the embodiment of the present invention.
Embodiment
Embodiment 1:
A preparation method for electric field blocking-up type IGBT structure, comprises the steps:
Step 101: select heavily doped N+ single-chip as N+ type substrate, impurity is As, the resistivity of N+ type substrate is 0.01 Ω cm;
Step 102: form successively the first epitaxial loayer and the second epitaxial loayer by the method for extension on N+ type substrate; Wherein, the thickness of the first epitaxial loayer is 40 μ m, and the resistivity of the first epitaxial loayer is 10 Ω cm, form after the first epitaxial loayer, after Implantation and high annealing, then form the second epitaxial loayer, the impurity of Implantation is P, and energy is 2000KeV, and the dosage of Implantation is 1e13/cm
2, the temperature of activated at annealing is 1000 ℃, the time is 60 seconds; The second epitaxial loayer is N-base, and the thickness of N-base is 200 μ m, and the resistivity of N-type base is 100 Ω cm;
Step 103: form successively P+ base, N+ emitter region, grid oxic horizon, grid and emitter on the second epitaxial loayer, adopt conventional preparation method;
Step 104: by the thinning back side of N+ type substrate, remove part the first epitaxial loayer, form N+ type resilient coating, the first epitaxial loayer removes 20 μ m, and after attenuate, the thickness of N+ type resilient coating is 20 μ m;
Step 105: the back side at N+ type substrate forms P+ collector layer by the method for Implantation, and the dosage of Implantation is 1e12/cm
2, ion is B, and the energy of injection is 100KeV, and the temperature of impurity activation is under 500 ℃ of conditions, and annealing time is 10 seconds;
Step 106: at P+ collector layer, adopt deposition process, growth back of the body gold metal layer, this metal level is made up of Al, Ti, Ni and Ag from top to bottom successively.
Embodiment 2:
A preparation method for electric field blocking-up type IGBT structure, comprises the steps:
Step 201: select heavily doped N+ single-chip as N+ type substrate, impurity is As, the resistivity of N+ type substrate is 0.001 Ω cm;
Step 202: form successively the first epitaxial loayer and the second epitaxial loayer by the method for extension on N+ type substrate; Wherein, the thickness of the first epitaxial loayer is 10 μ m, and the resistivity of the first epitaxial loayer is 1 Ω cm, form after the first epitaxial loayer, after Implantation and high annealing, then form the second epitaxial loayer, the impurity injecting is As, and energy is 40KeV, and the dosage of Implantation is 1e11/cm
2, activated at annealing, typical condition is 1000 ℃, the time is 30 seconds; The second epitaxial loayer is N-base, and the thickness of N-base is 50 μ m, and the resistivity of N-base is 30 Ω cm;
Step 203: form successively P+ base, N+ emitter region, grid oxic horizon, grid and emitter on the second epitaxial loayer, adopt conventional preparation method;
Step 204: by the thinning back side of N+ type substrate, remove part the first epitaxial loayer, form N+ type resilient coating, the first epitaxial loayer at least removes 5 μ m, and after attenuate, the thickness of N+ type resilient coating is 5 μ m;
Step 205: the back side at N+ type substrate forms P+ collector layer by the method for Implantation, and the dosage of Implantation is 1e16/cm
2, ion is BF
2, the energy of injection is 20KeV, impurity activation, under 300 ℃ of conditions, is annealed 10 seconds;
Step 206: at P+ collector layer, adopt deposition process, growth back of the body gold metal layer, this metal level is made up of Al, Ti, Ni and Ag from top to bottom successively.
Embodiment 3:
A preparation method for electric field blocking-up type IGBT structure, comprises the steps:
Step 301: select heavily doped N+ single-chip as N+ type substrate, impurity is As, the resistivity of N+ type substrate is 0.006 Ω cm;
Step 302: form successively the first epitaxial loayer and the second epitaxial loayer by the method for extension on N+ type substrate; Wherein, the thickness of the first epitaxial loayer is 40 μ m, and the resistivity of the first epitaxial loayer is that 5 Ω cm the second epitaxial loayers are N-base, and the thickness of N-base is 100 μ m, and the resistivity of N-type base is 90 Ω cm;
Step 303: form successively P+ base, N+ emitter region, grid oxic horizon, grid and emitter on the second epitaxial loayer, adopt conventional preparation method;
Step 304: by the thinning back side of N+ type substrate, remove part the first epitaxial loayer, form N+ type resilient coating, the first epitaxial loayer removes 30 μ m, and after attenuate, the thickness of N+ type resilient coating is 10 μ m;
Step 305: the back side at N+ type substrate forms P+ collector layer by the method for Implantation, and the dosage of Implantation is 1e16/cm
2, ion is BF
2, the energy of injection is 20KeV, impurity activation, under 300 ℃ of conditions, is annealed 120 minutes;
Step 306: at P+ collector layer, adopt deposition process, growth back of the body gold metal layer, this metal level is made up of Al, Ti, Ni and Ag from top to bottom successively.
Embodiment 4:
Referring to Fig. 1, a kind of electric field blocking-up type IGBT structure of being prepared by embodiment 1, is applicable to the IGBT device of 1200V, and this IGBT structure comprises successively from back-to-front, P+ collector electrode, N+ resilient coating, N-substrate, P+ base, grid and emitter; Wherein, the N+ type buffer layer thickness in IGBT structure is 20 μ m, and the resistivity of this N+ type resilient coating is 1 Ω cm.
Embodiment 5:
2 one kinds of electric field blocking-up type IGBT structures being prepared by embodiment 2, are applicable to the IGBT device of 1200V, and this IGBT structure comprises successively from back-to-front, P+ collector electrode, N+ resilient coating, N-substrate, P+ base, grid and emitter; Wherein, the N+ type buffer layer thickness in IGBT structure is 5 μ m, and the resistivity of this N+ type resilient coating is 10 Ω cm.
Embodiment 6:
A kind of electric field blocking-up type IGBT structure of being prepared by embodiment 3, is applicable to the IGBT device of 1200V, and this IGBT structure comprises successively from back-to-front, P+ collector electrode, N+ resilient coating, N-substrate, P+ base, grid and emitter; Wherein, the N+ type buffer layer thickness in IGBT structure is 10 μ m, and the resistivity of this N+ type resilient coating is 5 Ω cm.
The method that the embodiment of the present invention provides, its advantage shows the following aspects:
1) IGBT preparation adopts epitaxial substrate, and preparation method is simple, and is convenient to integrated.
2) N+ type resilient coating adopts the method preparation of extension, is entrained in the process of extension and completes simultaneously, can adopt expensive energetic ion to inject and laser active annealing device.
3) thickness of N+ resilient coating is determined by the thickness of the first epitaxial loayer, and its thickness can regulate arbitrarily.The thickness of the slow layer of N+ prepared by the method for traditional employing Implantation is subject to the restriction of ion implantation energy, and typical thickness is in 2 μ m left and right, and this method is difficult to prepare the N+ resilient coating that thickness is greater than 10 μ m.The concentration of N+ type resilient coating prepared by this method can further be optimized by Implantation subsequently.
4) thickness of the N+ resilient coating that prepared by this method is at 5 μ m between 35 μ m, and thicker compared with the resilient coating of preparing with traditional employing ion injection method, its doping content is also lower.The IGBT that adopts preparation in this way has less high-temperature current leakage, therefore has better reliability.On the other hand, because N+ resilient coating has lower doping content and larger thickness, therefore IGBT has less electric current and the rate of change of voltage in the process of turn-on and turn-off, and therefore to resist the ability that various electrical parameters impact stronger for IGBT.
5) P+ collector layer adopts the method for Implantation to form, accurately controlled doping CONCENTRATION DISTRIBUTION.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to example, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement technical scheme of the present invention, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of claim scope of the present invention.
Claims (10)
1. a preparation method for electric field blocking-up type IGBT structure, is characterized in that, comprises the steps:
Select N+ single-chip as N+ type substrate;
Front at described N+ type substrate forms the first epitaxial loayer and the second epitaxial loayer successively by the method for extension;
On described the second epitaxial loayer, form successively P+ base, N+ emitter region, grid oxic horizon, grid and emitter;
By the thinning back side of described N+ type substrate, remove described the first epitaxial loayer of part, form N+ type resilient coating, described the second epitaxial loayer is N-base;
The back side at described N+ type resilient coating forms P+ collector layer by the method for Implantation;
Growth back of the body gold metal layer on described P+ collector layer.
2. method according to claim 1, is characterized in that, described N+ type buffer layer thickness is 5-35 μ m, and the resistivity of described N+ type resilient coating is 1 – 10 Ω cm.
3. method according to claim 2, is characterized in that, described N+ type buffer layer thickness is 10-30 μ m.
4. method according to claim 1, is characterized in that, the thickness of described N-base is 50-200 μ m, and the resistivity of described N-base is 30 – 100 Ω cm.
5. method according to claim 1, is characterized in that, the resistivity of described N+ type substrate is 0.01 – 0.001 Ω cm.
6. method according to claim 1, is characterized in that, after described formation the first epitaxial loayer, after Implantation and high annealing, then forms described the second epitaxial loayer.
7. method according to claim 6, is characterized in that, described ion is the 5th major element, and the dosage of injection is 1e11/cm
2– 1e13/cm
2.
8. method according to claim 1, is characterized in that, in described formation P+ collector layer, the dosage of described Implantation is 1e12/cm
2– 1e16/cm
2.
9. method according to claim 8, is characterized in that, the ion of described Implantation is B or BF
2.
10. method according to claim 8, is characterized in that, the energy of described Implantation is 20KeV-100KeV.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109244125A (en) * | 2017-06-29 | 2019-01-18 | 万国半导体(开曼)股份有限公司 | Introduce the reverse conduction IGBT and preparation method thereof in epitaxial layer field stop area |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070120215A1 (en) * | 2005-11-30 | 2007-05-31 | Chong-Man Yun | Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same |
| CN101436542A (en) * | 2008-12-19 | 2009-05-20 | 北京工业大学 | Method for manufacturing insulated gate bipolar transistor with variable buffer layer concentration inner transparent collecting zone |
| CN102347355A (en) * | 2010-07-30 | 2012-02-08 | 万国半导体股份有限公司 | Method of minimizing field stop insulated gate bipolar transistor (igbt) buffer and emitter charge variation |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070120215A1 (en) * | 2005-11-30 | 2007-05-31 | Chong-Man Yun | Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same |
| CN101436542A (en) * | 2008-12-19 | 2009-05-20 | 北京工业大学 | Method for manufacturing insulated gate bipolar transistor with variable buffer layer concentration inner transparent collecting zone |
| CN102347355A (en) * | 2010-07-30 | 2012-02-08 | 万国半导体股份有限公司 | Method of minimizing field stop insulated gate bipolar transistor (igbt) buffer and emitter charge variation |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109244125A (en) * | 2017-06-29 | 2019-01-18 | 万国半导体(开曼)股份有限公司 | Introduce the reverse conduction IGBT and preparation method thereof in epitaxial layer field stop area |
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