CN102931223B - IGBT collector structure - Google Patents
IGBT collector structure Download PDFInfo
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- CN102931223B CN102931223B CN201210494615.5A CN201210494615A CN102931223B CN 102931223 B CN102931223 B CN 102931223B CN 201210494615 A CN201210494615 A CN 201210494615A CN 102931223 B CN102931223 B CN 102931223B
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Abstract
The invention provides a kind of IGBT collector structure, comprise N-type base, the N+ type area level spaced apart that the back side being also included in N-type base is formed, and at the back side of N-type base, the P+ type collector layer spaced apart that above-mentioned N+ type area level uncovered area spaced apart is formed.Described N+ type area level spaced apart is by pentad after the interval, the back side of N-type base is injected, and is formed after followed by all thermal processs in the front that experienced by N-type base.Or described N+ type area level spaced apart is by the back side epitaxial growth one deck N+ type layer in N-type base, after then being etched by interval, and obtains after followed by all thermal processs in the front that experienced by N-type base.The present invention is for the formation of the collector structure of IGBT.
Description
Technical field
The present invention relates to a kind of structure of electronic component, especially a kind of IGBT collector structure.
Background technology
IGBT: the initial of insulated gate bipolar transistor is called for short, and a kind of voltage-controlled type power device, is generally applied as high-voltage switch gear.Usually according to electric field in drift region in-fighting condition heartily, be divided into punch and non-punch, after go out again on-the-spot cut-off type with technological development.As shown in Figure 1, be non-punch (NPT) device, its chip design thickness is thicker, cause the saturation conduction pressure drop Vce (sat) of device higher, and when device turns off, there is Carrier recombination process, turn-off time is longer, and the dynamic and static performance of device is all poor.But the pressure drop of this device saturation conduction raises along with temperature and raises (positive temperature coefficient), be suitable for application in parallel; The device anti-short circuit capability of this structure is fine in addition.As shown in Figure 2, for field cut-off type (FS) device, electric field is ended owing to introducing N+ resilient coating (shown in the Reference numeral 2 in Fig. 2) in a chip design, chip design thinner thickness, the Vce (sat) of device and switch performance are all better than NPT device, but its N+ resilient coating is after front technique completes, realized by the injection of pentad high energy and annealing overleaf, very high to equipment requirement, technological requirement is higher implements more complicated, in addition FS type device anti-short circuit capability is poorer than NPT type device, Vce (sat) is although be also positive temperature coefficient, but be not as excellent as NPT type device, not too be applicable to application in parallel.
Summary of the invention
The object of the invention is supplementary the deficiencies in the prior art, a kind of IGBT collector structure is provided, combines the advantage of NPT type device and FS type device, have employed the IGBT of this structure, its thickness is suitable with FS type device on the one hand, and the dynamic and static state performance of device is suitable with FS type device.Meanwhile, because back side N+ resilient coating is spaced apart, the anti-short circuit capability of device is better, and Vce (sat) is comparatively strong positive temperature coefficient simultaneously, can meet the demand of application in parallel.N+ resilient coating spaced apart of the present invention (i.e. N+ type area level spaced apart) is followed after front, N-type base experiences all thermal processs and is formed in addition, its annealing enough fully causes pentad to advance the degree of depth enough large, the injection carrying out high energy is not needed to be formed, lower to equipment requirement.The technical solution used in the present invention is:
A kind of IGBT collector structure, comprise N-type base, the N+ type area level spaced apart that the back side being also included in N-type base is formed, and at the back side of N-type base, the P+ type collector layer spaced apart that above-mentioned N+ type area level uncovered area spaced apart is formed.
Described N+ type area level spaced apart is by pentad after the interval, the back side of N-type base is injected, and is formed after followed by all thermal processs in the front that experienced by N-type base.
Described N+ type area level spaced apart or the back side epitaxial growth one deck N+ type layer passed through in N-type base, after then being etched by interval, and obtained after followed by all thermal processs in the front that experienced by N-type base.
Advantage of the present invention: the IGBT that have employed this structure, thickness is suitable with FS type device on the one hand, and the dynamic and static state performance of device is suitable with FS type device.Meanwhile, because back side N+ resilient coating is spaced apart, the anti-short circuit capability of device is better.When this structure is formed, do not need the high energy ion implantation carrying out pentad, lower to equipment requirement.
Accompanying drawing explanation
Fig. 1 is traditional non-punch through IGBT structure chart.
Fig. 2 is field cut-off type IGBT structure figure.
Fig. 3 is backing material schematic diagram of the present invention.
Fig. 4 is N+ type shallow-layer schematic diagram spaced apart of the present invention.
Fig. 5 is N+ type area level schematic diagram spaced apart of the present invention.
Fig. 6 is IGBT collector structure schematic diagram of the present invention.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
As shown in Fig. 4, Fig. 5, Fig. 6:
A kind of IGBT collector structure, comprise N-type base 3, the N+ type area level 5 spaced apart that the back side being also included in N-type base 3 is formed, and at the back side of N-type base 3, the P+ type collector layer 6 spaced apart that above-mentioned N+ type area level 5 uncovered area spaced apart is formed.
Described N+ type area level 5 spaced apart is by pentad after the interval, the back side of N-type base 3 is injected, and is formed after followed by all thermal processs in the front that experienced by N-type base 3.
Described N+ type area level 5 spaced apart or the back side epitaxial growth one deck N+ type layer passed through in N-type base 3, after then being etched by interval, and obtained after followed by all thermal processs in the front that experienced by N-type base 3.
The following detailed description of the preparation method of this IGBT collector structure, as shown in Fig. 3, Fig. 4, Fig. 5, Fig. 6.
A () first chooses suitable backing material according to design object, as the material of N-type base 3; As shown in Figure 3, using not thinning N-type silicon wafer as backing material.
(b) secondly, as shown in Figure 4, using after substrate thinning as N-type base 3, inject pentad (not needing high energy ion implantation) in the compartment of terrain, the back side of N-type base 3; Owing to not annealing in this step, in the very little thin layer in surface that the N+ type shallow-layer 4 spaced apart that the pentad of injection is formed also just rests on the back side, N-type base 3.
C () then, after protecting the back side of N-type base 3, the complete PROCESS FOR TREATMENT in front is carried out in the front for N-type base 3, wherein comprises thermal process; The N+ type shallow-layer 4 spaced apart at the back side, N-type base 3 formed in step (b) followed by all thermal processs (comprising annealing process) in the front that experienced by N-type base 3, defines N+ type area level 5 spaced apart.As shown in Figure 5, because annealing is enough abundant, N+ type area level 5 spaced apart comparatively can go deep into the back side, N-type base 3.
D () is last, after the front protecting to N-type base 3, at the back side of N-type base 3; above-mentioned N+ type area level 5 uncovered area spaced apart; triad compartment of terrain is injected, subsequently through process annealing or laser annealing, forms described P+ type collector layer 6 spaced apart.
In this method, being infused in of pentad is just carried out at first, can follow thereafter front, N-type base 3 and experience all thermal processs, and its annealing is enough abundant, and advance the degree of depth enough large, the structure of formation can be born necessarily withstand voltage, improves the withstand voltage of device.
By controlling the ratio of pentad and triad injection zone area, effectively can control injection efficiency, improving the dynamic property of device.
In above-mentioned (b) step, also can by the back side epitaxial growth one deck N+ type layer in N-type base 3, after then being etched by interval, etching goes unwanted part, leaves the part of needs, namely obtains N+ type shallow-layer 4 spaced apart.
Claims (1)
1. the manufacture method of an IGBT collector structure, comprise N-type base (3), and the N+ type area level (5) spaced apart that the back side of N-type base (3) is formed, and at the back side of N-type base (3), the P+ type collector layer (6) spaced apart that above-mentioned N+ type area level (5) uncovered area spaced apart is formed;
It is characterized in that:
(a) first using not thinning N-type silicon wafer as backing material;
(b) secondly, using after substrate thinning as N-type base (3), inject pentad in the compartment of terrain, the back side of N-type base (3); Owing to not annealing in this step, in the very little thin layer in surface that the N+ type shallow-layer (4) spaced apart that the pentad of injection is formed also just rests on N-type base (3) back side;
C () then, after protecting the back side of N-type base (3), complete PROCESS FOR TREATMENT is carried out in the front for N-type base (3), wherein comprises thermal process; The N+ type shallow-layer (4) spaced apart at N-type base (3) back side formed in step (b) followed by all thermal processs in the front that experienced by N-type base (3), defines N+ type area level (5) spaced apart; Because annealing is enough abundant, N+ type area level (5) spaced apart comparatively can go deep into N-type base (3) back side;
D () is last; after front protecting to N-type base (3); at the back side of N-type base (3); above-mentioned N+ type area level (5) uncovered area spaced apart; triad compartment of terrain is injected; subsequently through process annealing or laser annealing, form described P+ type collector layer (6) spaced apart.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201210494615.5A CN102931223B (en) | 2012-11-28 | 2012-11-28 | IGBT collector structure |
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| CN201210494615.5A CN102931223B (en) | 2012-11-28 | 2012-11-28 | IGBT collector structure |
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| CN102931223A CN102931223A (en) | 2013-02-13 |
| CN102931223B true CN102931223B (en) | 2015-11-04 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104282551A (en) * | 2013-07-03 | 2015-01-14 | 无锡华润上华半导体有限公司 | Method for manufacturing IGBT |
| CN103500704A (en) * | 2013-09-29 | 2014-01-08 | 武汉新芯集成电路制造有限公司 | Ion implantation method for back face of wafer |
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| CN1577884A (en) * | 2003-07-24 | 2005-02-09 | 三菱电机株式会社 | Insulated gate bipolar transistor and its production method and current transformation circuit |
| CN1691349A (en) * | 2004-04-28 | 2005-11-02 | 三菱电机株式会社 | Reverse conducting semiconductor device and a fabrication method thereof |
| CN101000911A (en) * | 2006-01-10 | 2007-07-18 | 株式会社电装 | Semiconductor device having IGBT and diode |
| CN101026161A (en) * | 2006-02-24 | 2007-08-29 | 株式会社电装 | Semiconductor device having IGBT and diode |
| CN101170109A (en) * | 2006-10-27 | 2008-04-30 | 三菱电机株式会社 | Semiconductor device and manufacturing method thereof |
| CN101478001A (en) * | 2008-11-27 | 2009-07-08 | 电子科技大学 | Collecting electrode IGBT having hole injection structure |
| CN101494238A (en) * | 2008-01-23 | 2009-07-29 | 三菱电机株式会社 | Semiconductor device |
| CN101764139A (en) * | 2008-12-24 | 2010-06-30 | 株式会社电装 | Semiconductor device including insulated gate bipolar transistor and diode |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH06196705A (en) * | 1992-12-24 | 1994-07-15 | Hitachi Ltd | Reverse-current carrying type insulated gate bipolar transistor and manufacture thereof |
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2012
- 2012-11-28 CN CN201210494615.5A patent/CN102931223B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1577884A (en) * | 2003-07-24 | 2005-02-09 | 三菱电机株式会社 | Insulated gate bipolar transistor and its production method and current transformation circuit |
| CN1691349A (en) * | 2004-04-28 | 2005-11-02 | 三菱电机株式会社 | Reverse conducting semiconductor device and a fabrication method thereof |
| CN101000911A (en) * | 2006-01-10 | 2007-07-18 | 株式会社电装 | Semiconductor device having IGBT and diode |
| CN101026161A (en) * | 2006-02-24 | 2007-08-29 | 株式会社电装 | Semiconductor device having IGBT and diode |
| CN101170109A (en) * | 2006-10-27 | 2008-04-30 | 三菱电机株式会社 | Semiconductor device and manufacturing method thereof |
| CN101494238A (en) * | 2008-01-23 | 2009-07-29 | 三菱电机株式会社 | Semiconductor device |
| CN101478001A (en) * | 2008-11-27 | 2009-07-08 | 电子科技大学 | Collecting electrode IGBT having hole injection structure |
| CN101764139A (en) * | 2008-12-24 | 2010-06-30 | 株式会社电装 | Semiconductor device including insulated gate bipolar transistor and diode |
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Inventor after: Chen Hong Inventor after: Zhu Yangjun Inventor after: Lu Shuojin Inventor after: Xu Chengfu Inventor before: Chen Hong Inventor before: Zhu Yangjun Inventor before: Wu Kai Inventor before: Xu Chengfu Inventor before: Lu Shuojin |
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Effective date of registration: 20130117 Address after: 214135 Jiangsu New District of Wuxi City Linghu Road No. 200 China Sensor Network International Innovation Park C building 4 floor Applicant after: Jiangsu Internet of Things Research & Develoment Co., Ltd. Applicant after: Institute of Microelectronics, Chinese Academy of Sciences Applicant after: Jiangsu Zhongke Junshine Technology Co., Ltd. Address before: 214135 Jiangsu New District of Wuxi City Linghu Road No. 200 China Sensor Network International Innovation Park building C Applicant before: Jiangsu Internet of Things Research & Develoment Co., Ltd. |
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