CN103500704A - Ion implantation method for back face of wafer - Google Patents

Ion implantation method for back face of wafer Download PDF

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Publication number
CN103500704A
CN103500704A CN201310459704.0A CN201310459704A CN103500704A CN 103500704 A CN103500704 A CN 103500704A CN 201310459704 A CN201310459704 A CN 201310459704A CN 103500704 A CN103500704 A CN 103500704A
Authority
CN
China
Prior art keywords
ion
wafer
wafer rear
injection method
back face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310459704.0A
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Chinese (zh)
Inventor
洪齐元
黄海
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Original Assignee
Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan Xinxin Semiconductor Manufacturing Co Ltd filed Critical Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Priority to CN201310459704.0A priority Critical patent/CN103500704A/en
Publication of CN103500704A publication Critical patent/CN103500704A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H01J37/3171—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation for ion implantation
    • H01J37/3172—Maskless patterned ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Analytical Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

The invention discloses an ion implantation method for a back face of a wafer. The ion implantation method comprises the following steps: 1, thinning the back face of the wafer; 2, performing low-energy ion shallow doping implantation on the thinned back face of the wafer; 3, performing heat treatment by using a furnace tube to diffuse impurity ions towards the front face of the wafer to a required depth. According to the method, the doped ions are diffused to the required depth by the method for performing heat diffusion after the low-energy ion shallow implantation, so that the damage to a device is avoided and the performance of the device can also be met.

Description

A kind of ion injection method of wafer rear
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly a kind of ion injection method of wafer rear.
Background technology
The treatment process of wafer rear is widely used in the fields such as function element, and the main flow technique of making the such devices needs is the techniques such as the attenuate of wafer rear, Implantation, thermal annealing.Wherein ion implantation technology is particularly crucial, and because wafer frontside has formed certain active device, the excessively dark words of Implantation can be damaged device, and excessively shallow words can't meet the demand of device, therefore very strict to the requirement of technique.Present stage mainly concentrates on carries out strict technology controlling and process to the aspects such as the degree of depth of the wafer thickness after attenuate, Implantation, and (process window) is narrower for process window.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of wafer rear ion injection method, makes the ion of doping diffuse to desired depth, has so both avoided the damage of device, can meet again the performance of device.
For solving the problems of the technologies described above, the invention provides a kind of ion injection method of wafer rear, comprise the steps:
Step 1, carry out reduction processing to wafer rear;
Step 2, the wafer rear after attenuate carries out the shallow doping of low energy ion and injects;
Step 3, heat-treat with boiler tube, makes foreign ion diffuse to desired depth to wafer frontside.
Preferably, described reduction processing adopts wet etch process or Ginding process, and the thickness thinning scope is at 5～300um.
Preferably, the operating condition that the shallow doping of described low energy ion is injected is: the ion implantation energy scope is at 5～50Kev, and the ion dose scope is 10 13～10 15/ cm 2, the doping ion is germanium ion.
Preferably, in described 3～4 hours heat treated processing times, temperature is at 300～400 ℃.
The ion injection method of a kind of wafer rear of the present invention, can realize good wafer rear Implantation effect.
The accompanying drawing explanation
The ion injection method embodiment schematic flow sheet that Fig. 1 is a kind of wafer rear of the present invention.
Embodiment
Below in conjunction with accompanying drawing, principle of the present invention and feature are described, example, only for explaining the present invention, is not intended to limit scope of the present invention.
The ion injection method embodiment schematic flow sheet that Fig. 1 is a kind of wafer rear of the present invention, as shown in Figure 1, a kind of ion injection method of wafer rear, comprise the steps:
Step 1, carry out reduction processing to wafer rear; Reduction processing adopts wet etch process or Ginding process, and thickness thinning is 5um or 300um.Thickness thinning can be for 5um to the arbitrary value between 300um, and for example in other embodiments, thickness thinning can be 100um.
Step 2, the wafer rear after attenuate carries out the shallow doping of low energy ion and injects.
The operating condition that the shallow doping of described low energy ion is injected is:
Ion implantation energy is 5Kev or 50Kev.Ion implantation energy can be for 5Kev to the arbitrary value between 50Kev, and for example in other embodiments, ion implantation energy can be 10Kev.
Ion dose is 10 13cm 2or 10 15/ cm 2.Ion implantation dosage can be 10 13cm 2to 10 15/ cm 2between arbitrary value, for example in other embodiments, ion implantation energy can be 10 14cm 2.The doping ion is germanium ion.
Can control foreign ion by described technological parameter and inject the degree of depth.
Step 3, heat-treat the wafer rear that completes the shallow doping injection of low energy ion with boiler tube, makes foreign ion diffuse to desired depth to wafer frontside.
Heat treatment time is 3 hours or 4 hours.Heat treatment time can be the arbitrary value between 3 hours to 4 hours; For example in other embodiments, heat treatment time can be 2 hours.
Temperature is 300 ℃ or 400 ℃.Temperature can be the arbitrary value between 300 ℃ to 400 ℃, and for example in other embodiments, temperature is 200 ℃.
The present invention adopts the method for thermal diffusion afterwards by the shallow injection of ion of low energy, make the ion of doping diffuse to desired depth, has so both avoided the damage of device, can meet again the performance of device.
The above implementation step and method have only been expressed one embodiment of the present invention, and description is comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.Under the prerequisite that does not break away from patent design of the present invention, the distortion of doing and improvement should all belong to the protection range of patent of the present invention.

Claims (4)

1. the ion injection method of a wafer rear, comprise the steps:
Step 1, carry out reduction processing to wafer rear;
Step 2, the wafer rear after attenuate carries out the shallow doping of low energy ion and injects;
Step 3, heat-treat with boiler tube, makes foreign ion diffuse to desired depth to wafer frontside.
2. the ion injection method of a kind of wafer rear according to claim 1, is characterized in that, described reduction processing adopts wet etch process or Ginding process, and the thickness thinning scope is at 5～300um.
3. the ion injection method of a kind of wafer rear according to claim 1 and 2, is characterized in that, the operating condition that the shallow doping of described low energy ion is injected is: the ion implantation energy scope is at 5～50Kev, and the ion dose scope is 10 13～10 15/ cm 2, the doping ion is germanium ion.
4. the ion injection method of a kind of wafer rear according to claim 3, is characterized in that, in described 3～4 hours heat treated processing times, temperature is at 300～400 ℃.
CN201310459704.0A 2013-09-29 2013-09-29 Ion implantation method for back face of wafer Pending CN103500704A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310459704.0A CN103500704A (en) 2013-09-29 2013-09-29 Ion implantation method for back face of wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310459704.0A CN103500704A (en) 2013-09-29 2013-09-29 Ion implantation method for back face of wafer

Publications (1)

Publication Number Publication Date
CN103500704A true CN103500704A (en) 2014-01-08

Family

ID=49865900

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310459704.0A Pending CN103500704A (en) 2013-09-29 2013-09-29 Ion implantation method for back face of wafer

Country Status (1)

Country Link
CN (1) CN103500704A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104393006A (en) * 2014-09-30 2015-03-04 上海华力微电子有限公司 Manufacturing method of back-illuminated CIS product
CN111441072A (en) * 2020-03-27 2020-07-24 绍兴同芯成集成电路有限公司 Method for producing crystal grains by cutting crystal grains first and then electroplating on two sides

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5570035A (en) * 1978-11-20 1980-05-27 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
CN102931223A (en) * 2012-11-28 2013-02-13 江苏物联网研究发展中心 IGBT (Insulated Gate Bipolar Translator) collection electrode structure
CN103050387A (en) * 2012-12-18 2013-04-17 上海华虹Nec电子有限公司 Ion implantation method for silicon back surface

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5570035A (en) * 1978-11-20 1980-05-27 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
CN102931223A (en) * 2012-11-28 2013-02-13 江苏物联网研究发展中心 IGBT (Insulated Gate Bipolar Translator) collection electrode structure
CN103050387A (en) * 2012-12-18 2013-04-17 上海华虹Nec电子有限公司 Ion implantation method for silicon back surface

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104393006A (en) * 2014-09-30 2015-03-04 上海华力微电子有限公司 Manufacturing method of back-illuminated CIS product
CN111441072A (en) * 2020-03-27 2020-07-24 绍兴同芯成集成电路有限公司 Method for producing crystal grains by cutting crystal grains first and then electroplating on two sides

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Application publication date: 20140108