CN100552974C - Semiconductor element and forming method thereof - Google Patents
Semiconductor element and forming method thereof Download PDFInfo
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Abstract
Semiconductor element of the present invention has Semiconductor substrate; Gate stack is positioned on the Semiconductor substrate; N type lightly-doped source/drain region is arranged in Semiconductor substrate and adjoins gate is piled up, and wherein n type lightly-doped source/drain region comprises n type impurity; N type heavy-doped source/drain region is arranged in Semiconductor substrate and adjoins gate is piled up, and wherein this n type heavy-doped source/drain region comprises n type impurity; The amorphous state injection region is arranged in Semiconductor substrate in advance, and wherein the amorphous state injection region comprises the injection region, back in advance; And the Resistance, gap, being arranged in Semiconductor substrate, the degree of depth of its Resistance, intermediate gap is greater than the degree of depth of n type lightly-doped source/drain region, but less than the degree of depth of injection region, back.Because Resistance, gap of the present invention between injection region, back and lightly-doped source/drain region, can reduce the problem of phosphorous diffusion in lightly-doped source/drain region.In addition, because phosphorus has the overactivity rate, so the MOS element has low sheet resistor.
Description
Technical field
The present invention relates to a kind of semiconductor element, relate more specifically to form metal oxide half dollar spare with super shallow junction.
Background technology
Because transistorized size continues to dwindle, in order to control short-channel effect, the reduction vertical junction degree of depth and the horizontal proliferation of inhibition impurity become a major challenge.More little metal-oxide semiconductor (MOS) (hereinafter to be referred as MOS) element, its source/drain electrode is extended with the diffusion of impurities of heavily doped source/drain electrode big more to the influence of its characteristic.When particularly the impurity of source/drain electrode extension area obviously diffuses to channel region, will make between source electrode and the drain electrode and produce problems such as short-channel effect and leakage current.For addressing the above problem, adopted several different methods control diffusion of impurities.
The method of first kind of restriction p type or n type diffusion of impurities as shown in Figure 1.In Fig. 1, grid 6 is formed on the substrate 2.N type and/or p type impurity are injected into the source/drain region 8 and the grid 6 of n type MOS (hereinafter to be referred as NMOS) element and/or p type MOS (hereinafter to be referred as PMOS) element respectively.Arrow 10 is that above-mentioned ion injects.Concerning the NMOS element, nitrogen and fluorine can be injected into source/drain region 8 altogether; Concerning the PMOS element, nitrogen and carbon can be injected into source/drain region 8 altogether.Nitrogen, carbon, fluorine have the effect that slows down diffusion of impurities.Therefore, during annealing after the MOS element injects, diffusion of impurities is controlled, and makes source/drain region 8 have higher concentration and preferred profile control.
In Fig. 2, in the NMOS element, the method for the phosphorus doping profile of control deep source/drain polar region 16.At first form grid 12 on substrate 20, then ion injection n type impurity such as arsenic form sidewall spacer 11 again to form lightly-doped source/drain region (lightly doped source/drain is hereinafter to be referred as LDD) 14.Arrow 22 phosphonium ions inject, and in order to form deep source/drain polar region 16, this zone is co-implanting carbon and fluorine also.Carbon and fluorine can reduce phosphorous diffusion and improve the concentration of phosphorus, when improving transistor drive current, can not cause short-channel effect.
High-performance components needs the LDD district of shallow and overactivity.In general, the diffusion length of arsenic is short, therefore is applicable to form the LDD district.But the activation degree of arsenic is low, the therefore LDD sheet resistor height that is formed by arsenic, thereby the drive current of reduction element function such as NMOS element.Another kind of common n type impurity is phosphorus, and its activation degree height but diffusion length is long can influence junction depth and diffuse to channel region significantly.In sum, the new method of Technology Need of making integrated circuit at present forms the LDD district of shallow and overactivity.
Summary of the invention
The invention provides a kind of semiconductor element, comprise Semiconductor substrate; Gate stack is positioned on the Semiconductor substrate; N type lightly-doped source/drain region is arranged in Semiconductor substrate and adjoins gate is piled up, and wherein n type lightly-doped source/drain region comprises a n type impurity; N type heavy-doped source/drain region is arranged in Semiconductor substrate and adjoins gate is piled up, and wherein n type heavy-doped source/drain region comprises the 2nd n type impurity; The amorphous state injection region is arranged in Semiconductor substrate in advance, and wherein the amorphous state injection region comprises the injection region, back in advance; And the Resistance, gap, being arranged in Semiconductor substrate, the degree of depth of its Resistance, intermediate gap is greater than the degree of depth of n type lightly-doped source/drain region, but less than the degree of depth of injection region, back.
According to semiconductor element of the present invention, the degree of depth of Resistance, wherein said gap is between the degree of depth of the degree of depth of described n type lightly-doped source/drain region and described n type heavy-doped source/drain region.
According to semiconductor element of the present invention, the degree of depth of Resistance, wherein said gap equates in fact with the degree of depth of described n type heavy-doped source/drain region.
According to semiconductor element of the present invention, the degree of depth of Resistance, wherein said gap is greater than the degree of depth of described n type heavy-doped source/drain region.
According to semiconductor element of the present invention, wherein said gate stack is down channel region, to the small part channel region be not Resistance, described gap.
According to semiconductor element of the present invention, Resistance, wherein said gap comprise carbon, its concentration is between about 5E14/cm
3With about 5E15/cm
3Between.
The present invention also provides a kind of formation method of semiconductor element, comprises Semiconductor substrate is provided; Form gate stack on Semiconductor substrate; Form in advance the amorphous state injection region in Semiconductor substrate, wherein the amorphous state injection region comprises the injection region, back in advance; Form the Resistance, gap in Semiconductor substrate; Form lightly-doped source/drain region in Semiconductor substrate and adjoins gate pile up, wherein lightly-doped source/drain region comprises phosphorus, the degree of depth of its Resistance, intermediate gap is greater than the degree of depth of n type lightly-doped source/drain region, but less than the degree of depth of injection region, back; And form heavy-doped source/drain region in Semiconductor substrate and adjoins gate pile up.
According to formation method of the present invention, the step that wherein forms Resistance, described gap comprises carbon ion is injected into zone between described lightly-doped source/drain region and the described heavy-doped source/bottom, drain region.
According to the formation method of semiconductor element of the present invention, the step that wherein forms Resistance, described gap comprises carbon ion is injected into and dark zones such as described heavy-doped source/drain region.
According to the formation method of semiconductor element of the present invention, the step that wherein forms Resistance, described gap comprises carbon ion is injected into the zone darker than described heavy-doped source/drain region.
Because Resistance, gap of the present invention between injection region, back and lightly-doped source/drain region, can reduce the problem of phosphorous diffusion in lightly-doped source/drain region.In addition, because phosphorus has the overactivity rate, so the MOS element has low sheet resistor.
Description of drawings
Fig. 1 is the method that known technology is made the MOS element, and wherein nitrogen and fluorine are in order to stop the diffusion of n type impurity, and nitrogen and carbon are in order to stop the diffusion of p type impurity;
Fig. 2 is the method that known technology is made the MOS element, at the regional co-implanting carbon and the fluorine that inject phosphorus;
Fig. 3-Fig. 8 C is in the embodiment of the invention, forms the flow process profile of NMOS element;
Fig. 9 is the mechanism of a preferred embodiment of the present invention;
Figure 10 is the section of structure of a preferred embodiment of the present invention;
Figure 11 is in the one embodiment of the invention, the curve chart of the corresponding degree of depth of phosphorus concentration; And
Figure 12 is among the present invention, the curve chart of the corresponding junction depth of knot steepness.
Wherein, description of reference numerals is as follows:
2,20,40～substrate; 6,12,46～grid; 8～source/drain electrode; 10,50～ion injects; 11,64～sidewall spacer; 14,60～LDD district; 16～deep source/drain polar region; 22～phosphonium ion injects; 44～gate dielectric; 48～dizzy shape district; 52～PAI injects; 54～PAI district; 55～EOR district; Resistance, 56～gap; 66～N+S/D district; 68～high gap concentration range; The LDD district that 70～phosphonium ion injects; 80～metal silication district; 82～CESL; 84～ILD; 86～contact plunger; 90,92,94～phosphorus distribution curve; The degree of depth in D1～PAI district; The degree of depth in D2～LDD district; The degree of depth of D3～Resistance, gap; The degree of depth in D4～N+S/D district.
Embodiment
In high-performance NMOS element, source/drain region is preferable to have low sheet resistor and shallow junction.Yet these two requirements are mutual contradiction often.In order to reduce sheet resistor, must use more activated impurity, this will make the diffusion of impurities of injection region and increase junction depth.In preferred embodiment of the present invention, the impurity that (be called lightly-doped source/drain region again, be called for short the LDD district) extended in source/drain electrode is phosphorus.Under the situation of control phosphorous diffusion, the LDD district of preferred embodiment of the present invention has high concentration phosphorus.Fig. 3-8C shows the technology cutaway view of preferred embodiment of the present invention, and in different figure, similar elements is with labeled.
In Fig. 3, the gate dielectric 44 of gate stack is formed on the substrate 40, and grid 46 is formed on the gate dielectric 44.Substrate 40 is preferably silicon on silicon substrate such as the insulating barrier (SOI) structure.In addition, the material of substrate 40 also can be stress silicon or other the similar materials on general backing material such as SiGe, the SiGe.Gate dielectric 44 is preferably oxide such as thermal oxide.In addition, gate dielectric 44 also can be nitride, nitrogen oxide, oxycarbide, high dielectric constant material or above-mentioned combination.Known to the present technique personage, the method that forms gate stack is after forming gate dielectric and grid layer in regular turn on the substrate 40, and patterning is to form grid 46 and gate dielectric 44 again.
In Fig. 4, ion injects p type impurity such as boron or indium and forms dizzy shape district (pocket/haloregion) 48.Arrow 50 injects for ion, and its angle is preferable less than 50 degree.Known to the present technique personage, the impurity that can import more than one is in dizzy shape district 48.In preferred embodiment, the dizzy shape district 48 of p type is positioned at the periphery in the LDD district that next forms, in order to the n type impurity of neutralization diffusion.
In Fig. 5, form PAI districts 54 as arrow 52 with amorphous state injection (pre-amorphized implantation is hereinafter to be referred as PAI) in advance.PAI district 54 can reduce the tunneling effect of impurity, but and activated impurity.In preferred embodiment, PAI utilizes germanium ion.In other embodiments, PAI utilizes carbon ion.The impurity that PAI can avoid injecting subsequently wears that tunnel is crossed lattice and diffusion surpasses desired depth.Concerning the carbon ion that injects subsequently, PAI after annealing process crystallization and occupy lattice again.The distributed pole in PAI district is limited to injection region, back (end of range is hereinafter to be referred as EOR) 55, and therefore the zone for maximum germanium ions stop to have high gap concentration.Though EOR district 55 is a line in the drawings, be understandable that the EOR district is actually banded regions, may be positioned at the position darker than the Gaussian Profile peak of germanium ion.
The angle of PAI is preferable less than 50 degree, is more preferred from the angle of two kinds of mutual subtends.The injection energy of germanium ion is preferable between about 5keV and about 40keV, is more preferred from about 20keV.The degree of depth in PAI district is D1.The depth D 1 of PAI is preferable greater than the source/drain region that forms subsequently and the junction depth of source/drain electrode extension area.The dosage that its ion of PAI district injects is preferable between 1E14/cm
2With about 1E15/cm
2Between, be preferably about 5E14/cm
2
In Fig. 6, then form Resistance, gap 56, its generation type is preferably carbon ion and injects.This ion implantation angle is preferable less than 50 degree, is more preferred from the angle of two kinds of mutual subtends.Oblique ion injects and makes Resistance, gap 56 extend to grid 46 times, therefore has preferable effect.In this example, grid 46 is not Resistance, gap 56 down to the small part channel region.The ion implantation dosage of Resistance, gap 56 is preferable between about 5E14/cm
2With about 5E15/cm
2Between, be more preferred from about 1E15/cm
2Preferable ion implantation energy is more preferred from about 5keV between about 3keV and about 10keV.In Fig. 6, Resistance, gap 56 is banded, but is understandable that carbon ion is a Gaussian Profile, has the sub-fraction can be darker, and sub-fraction is more shallow, even shallow surface to substrate 40.Banded regions is the zone of maximum concentration.In preferred embodiment, the energy that ion injects has only a kind of (the ion injection with different-energy can make to distribute and broaden).In other embodiments, the narrower scope of energy that carbon ion injects, the gap between highest energy and the minimum energy is no more than 3keV.In another embodiment, the injection energy of ion is a wide region, and therefore carbon ion is distributed to the surface of substrate 40.
In Fig. 7, then form LDD district 60, its formation method is that phosphonium ion injects.In addition, also can when injecting, inject phosphonium ion arsenic altogether.The dosage that the phosphonium ion in LDD district 60 injects is preferable between about 1E14/cm
2With about 1E16/cm
2Between, be more preferred from about 1E15/cm
2Because this formation method is common technology, in this omission.
In Fig. 8 A-8C, then form sidewall spacer 64 and n type heavy-doped source/drain electrode (hereinafter to be referred as N+S/D) district 66.As is known to the person skilled in the art, after the formation method code-pattern ground dielectric layer of sidewall spacer 64, remove the dielectric layer of horizontal plane, along the sidewall reservation sidewall spacer 64 of grid 46 with gate dielectric 44.
Then with sidewall spacer 64 as mask, ion injects n type impurity such as phosphorus to form N+S/D district 66, its degree of depth is D4.Also but ion injects arsenic in addition, or the combination of phosphorus and arsenic.The dosage that this ion injects is preferable between about 5E15/cm
2With about 6E15/cm
2Between.Fig. 8 A is a preferred embodiment of the present invention, and the degree of depth of its Resistance, intermediate gap 56 is greater than the degree of depth of N+S/D district 66 with LDD district 60.Thus, Resistance, gap 56 can stop EOR district 55 interstitial diffusion to the N+S/D district 66 with LDD district 60.Fig. 8 B is another preferred embodiment of the present invention, and the degree of depth of its Resistance, intermediate gap 56 is less than the degree of depth in N+S/D district 66, but greater than the degree of depth in LDD district 60.Thus, Resistance, gap 56 can stop that the interstitial diffusion in EOR district 55 is to LDD district 60.Fig. 8 C is the another preferred embodiment of the present invention, and the depth D 3 of its Resistance, intermediate gap 56 degree of depth with the N+S/D district in fact is identical.Thus, Resistance, gap 56 not only stops the interstitial diffusion in EOR district 55 to LDD district 60, and its carbon mixes and also stops the diffusion of impurities in EOR district 55 to N+S/D district 66.
Activate the impurity of above-mentioned technology subsequently, preferable activating process is rta technique (hereinafter to be referred as RTA).The temperature of RTA is preferable between about 950 ℃ to 1100 ℃.In a preferred embodiment, this technological temperature is about 1020 ℃.In addition, this activating process can be general known method such as boiler tube annealing, annealing laser, short annealing or other similar annealing processs.
Fig. 9 shows mechanism possible when activating.X-axis is the following degree of depth in substrate 40 surfaces, and Y-axis is a phosphorus concentration.In preferred embodiment, the degree of depth in LDD district is D2, and its concentration profile is 70.The degree of depth of Resistance, gap (shadow region) is D3, and the degree of depth of EOR district (degree of depth than dotted line 68 is also dark) is D1.Above-mentioned D1, D2, and D3 please refer to Fig. 8 A-8C.As mentioned above, the depth D 1 in EOR district is greater than the depth D 3 of Resistance, gap, and the depth D 3 of Resistance, gap is greater than the depth D 2 in LDD district.Thus, the Resistance, gap of containing carbon is positioned at the LDD district (solid line 70) that high gap concentration range (dotted line 68) and phosphonium ion inject.In activating process, the gap can be spread towards the phosphonium ion injection region, but the carbon of Resistance, gap can be caught the gap, makes the gap can't diffuse to the LDD district.Since the gap can't with the phosphorus effect, therefore when stopping the gap, also suppress phosphorous diffusion significantly.The preferable degree of depth greater than source/drain junction of the degree of depth of the high concentration region in its gap, PAI district can reduce the problem of source/drain region leakage current to substrate.
In Figure 10, on said structure, form metal silication district 80, contact etch stop layer (hereinafter to be referred as CESL) 82, interlayer dielectric layer (hereinafter to be referred as ILD) 84 and contact plunger 86.The formation method in metal silication district 80 forms a thin metal layer (not shown) earlier in said structure, and suitable metal is cobalt, nickel, erbium, molybdenum, platinum or other suitable metals.Then annealing to make forms metal silication district 80 between the metal level of deposition and the silicon area under it, remove unreacted metal at last.The formation method of CESL 82 is preferably blanket-deposited.The CESL layer has two kinds of functions, and one for providing stress to element and improve the carrier mobility of element; The two protects the zone under it to avoid etching.Then deposit ILD84 on the surface of CESL 82, and form contact plunger 86.Above-mentioned technology is general common technology, in this omission.
The effect of preferred embodiment of the present invention as shown in figure 11, transverse axis is the following degree of depth of substrate, the longitudinal axis is a phosphorus concentration.Phosphorus concentration curve before the annealing is 90.The 1st example that does not have the Resistance, gap, the phosphorus distribution curve behind 1020 ℃ RTA is 92.The 2nd example of preferred embodiment of the present invention, the phosphorus distribution curve behind annealing process is 94.Compare with phosphorus distribution curve 92, the steepness (abruptness) of phosphorus distributed area line 94 is big and spread less.In addition, the activation degree of phosphorus distribution curve 94 higher (see a little 96).In the 2nd example, the sheet resistor of element is about 374 Ω/Sqr.Compare with the well known elements of the LDD with arsenic doping, improved 32%.The junction depth of the 2nd example is about 17.6 nanometers, and the knot steepness is about 2.2nm/decade.
Figure 12 is with 5E18/cm
3Activation degree as benchmark, show the steepness of different junction depths.Square frame shows in 65 nanometer technologies, the junction depth that the MOS element is preferable and the scope of steepness.What letter was sayed is the requirement that scope meets 65 nanometer technologies in the frame.With compare as the known technology (representing) in LDD district with arsenic with starlike label, the knot steepness of part embodiment of the present invention is not inconsistent specification.Yet as its sheet resistor of known technology in LDD district sheet resistor height than phosphorus of the present invention source/drain region, this will reduce element function with arsenic.
Though the present invention with several preferred embodiments openly as above; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can changing arbitrarily and revise, so protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.
Claims (10)
1. semiconductor element comprises:
Semiconductor substrate;
Gate stack is positioned on the described Semiconductor substrate;
N type lightly-doped source/drain region is arranged in described Semiconductor substrate and in abutting connection with described gate stack, wherein said n type lightly-doped source/drain region comprises a n type impurity, and a described n type impurity comprises phosphorus;
N type heavy-doped source/drain region, be arranged in described Semiconductor substrate and the described gate stack of adjacency, and the degree of depth of described n type heavy-doped source/drain region is greater than the degree of depth of described n type lightly-doped source/drain region, wherein said n type heavy-doped source/drain region comprises the 2nd n type impurity, and described the 2nd n type impurity comprises phosphorus, arsenic or above-mentioned combination;
Amorphous state injection region in advance, be arranged in described Semiconductor substrate, the distributed pole of wherein said amorphous state in advance injection region is limited to injection region, a back, and the degree of depth of injection region, described back is greater than the degree of depth of described n type heavy-doped source/drain region and the degree of depth of described n type lightly-doped source/drain region; And
Carbon ion injects the Resistance, gap, is arranged in described Semiconductor substrate, and wherein said carbon ion injects the degree of depth of the degree of depth of Resistance, gap greater than described n type lightly-doped source/drain region, but less than the described degree of depth of injection region afterwards.
2. semiconductor element as claimed in claim 1, wherein said carbon ion injects the degree of depth of Resistance, gap, between the degree of depth of the degree of depth of described n type lightly-doped source/drain region and described n type heavy-doped source/drain region.
3. semiconductor element as claimed in claim 1, wherein said carbon ion injects the degree of depth of Resistance, gap and the deep equality of described n type heavy-doped source/drain region.
4. semiconductor element as claimed in claim 1, wherein said carbon ion inject the degree of depth of the degree of depth of Resistance, gap greater than described n type heavy-doped source/drain region.
5. semiconductor element as claimed in claim 1, wherein said gate stack are channel region down, are not that described carbon ion injects the Resistance, gap to the small part channel region.
6. semiconductor element as claimed in claim 1, wherein said carbon ion inject the carbon that comprises of Resistance, gap, and its concentration is between 5E14/cm
3With 5E15/cm
3Between.
7. the formation method of a semiconductor element comprises:
Semiconductor substrate is provided;
Form gate stack on described Semiconductor substrate;
Form in advance the amorphous state injection region in described Semiconductor substrate, the distributed pole of wherein said amorphous state in advance injection region is limited to injection region, a back;
Form carbon ion and inject the Resistance, gap in described Semiconductor substrate;
Form lightly-doped source/drain region in described Semiconductor substrate and in abutting connection with described gate stack, wherein said lightly-doped source/drain region comprises phosphorus, wherein said carbon ion injects the degree of depth of the degree of depth of Resistance, gap greater than described n type lightly-doped source/drain region, but less than the described degree of depth of injection region afterwards; And
Form heavy-doped source/drain region in described Semiconductor substrate and in abutting connection with described gate stack, the degree of depth of wherein said heavy-doped source/drain region is greater than described lightly-doped source/drain region, and the degree of depth of injection region, described back is greater than the degree of depth of described heavy-doped source/drain region and the degree of depth of described lightly-doped source/drain region.
8. the formation method of semiconductor element as claimed in claim 7 wherein forms step that described carbon ion injects the Resistance, gap and comprises carbon ion is injected into the zone of described lightly-doped source/drain region between bottom described heavy-doped source/drain region.
9. the formation method of semiconductor element as claimed in claim 7 wherein forms step that described carbon ion injects the Resistance, gap and comprises carbon ion is injected into and dark zone such as described heavy-doped source/drain region.
10. the formation method of semiconductor element as claimed in claim 7 wherein forms step that described carbon ion injects the Resistance, gap and comprises carbon ion is injected into the zone darker than described heavy-doped source/drain region.
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| US8193586B2 (en) | 2008-08-25 | 2012-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Sealing structure for high-K metal gate |
| CN102543736B (en) * | 2010-12-15 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and method for manufacturing same |
| CN102437163A (en) * | 2011-08-29 | 2012-05-02 | 上海华力微电子有限公司 | CMOS (Complementary Metal Oxide Semiconductor) structure of wide forbidden band material on insulator and preparation method thereof |
| US9209316B2 (en) | 2012-03-15 | 2015-12-08 | Macronix International Co., Ltd. | ROM for constraining 2nd-bit effect |
| CN103325790B (en) * | 2012-03-19 | 2016-03-30 | 旺宏电子股份有限公司 | Read-only memory and manufacture method thereof |
| CN103325826A (en) * | 2012-03-20 | 2013-09-25 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN104576379B (en) * | 2013-10-13 | 2018-06-19 | 中国科学院微电子研究所 | A kind of MOSFET structure and its manufacturing method |
| US20150194311A1 (en) * | 2014-01-08 | 2015-07-09 | Macronix International Co., Ltd. | Method For Manufacturing Semiconductor Device |
| US9773554B2 (en) * | 2014-04-01 | 2017-09-26 | Macronix International Co., Ltd. | Composite impurity scheme for memory technologies |
| CN107104051B (en) * | 2016-02-22 | 2021-06-29 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN108281485B (en) * | 2017-01-06 | 2021-09-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US10840333B2 (en) * | 2018-10-31 | 2020-11-17 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangement and method of manufacture |
| KR20200140976A (en) * | 2019-06-07 | 2020-12-17 | 삼성전자주식회사 | Semiconductor device |
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