CN104576379B - MOSFET structure and manufacturing method thereof - Google Patents

MOSFET structure and manufacturing method thereof Download PDF

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CN104576379B
CN104576379B CN201310477078.8A CN201310477078A CN104576379B CN 104576379 B CN104576379 B CN 104576379B CN 201310477078 A CN201310477078 A CN 201310477078A CN 104576379 B CN104576379 B CN 104576379B
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substrate
source
gate stack
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diffusion barrier
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CN104576379A (en
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尹海洲
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to PCT/CN2013/085671 priority patent/WO2015051565A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

the invention provides a MOSFET manufacturing method which comprises the steps of a, providing a substrate (100), b, forming a pseudo gate stack (200) on the substrate, c, forming source and drain extension regions (101a and 101b) on two sides of the pseudo gate stack (200), d, forming a diffusion barrier region (105) in the substrate on one side of the drain extension region (101b), e, forming side walls (201) on two sides of the pseudo gate stack (200), forming source and drain regions (102) on two sides of the side walls (201) and annealing, f, forming an interlayer dielectric layer (500), removing the pseudo gate stack (200) to form a pseudo gate vacancy, and g, sequentially depositing a gate dielectric layer (601), a work function adjusting layer (602) and a gate metal layer (603) in the pseudo gate vacancy.

Description

A kind of MOSFET structure and its manufacturing method
Technical field
The present invention relates to a kind of MOSFET structure and its manufacturing methods.More specifically, it is related to one kind for reducing OFF state The MOSFET structure and its manufacturing method of leakage current.
Technical background
As device is more and more thinner, gate-induced drain leakage (GIDL) electric current for being caused by band-to-band-tunneling during device OFF state more next Bigger, it has become one of serious the problem of limiting MOSFET and FLASH memory.GIDL electric currents just introduce heat in itself Hole is injected, it causes hole to be trapped in gate oxide so as to cause the unstability of device and grid oxide layer can be caused to hit It wears.Therefore with the reduction of oxidated layer thickness, the reliability of OFF state oxide layer will be more and more important, has caused in this respect More and more concerns.
The routine techniques for reducing GIDL is to improve the temperature of gate oxide formation to about 1000 DEG C to 1100 DEG C.Improve oxygen Change the surface density of states that temperature is mainly less substrate, to reduce GIDL.Present prevailing technology mainly passes through fast speed heat oxygen Change effect technique (RTO) and insitu moisture generation technique (In-situ steam generation, ISSG) grow gate oxidation Layer.But RTO is with the oxidation of oxidation furnace than that can lead to the worse uniformity of gate oxide, this uneven device that causes Threshold voltage variation is big, this is undesirable；Oxide layer is grown also with ISSG, 55nm systems are narrowed down to device size Journey is hereinafter, the control ability reduced to GIDL electric currents also gradually lowers.
The technology that another kind reduces GIDL is to reduce the concentration of lightly doped drain (LDD).Since device size is reduced, short ditch Channel effect becomes the problem of increasingly serious.The main purpose of LDD is for this inhibition short-channel effect.In order to reduce short channel Effect, LDD must use ultra-shallow junctions.But in order to avoid the reduction of driving current, the concentration of LDD is also increasingly enhanced.If it adopts Reduce GIDL electric currents with the method for LDD concentration is reduced simply, channel region resistance will be increased, while reduce driving current, Allow the degradation of device.Therefore, GIDL electric currents are reduced to following integrated circuit (IC) with the concentration for reducing LDD simply Device is also worthless.
Therefore, a kind of metal-oxide-semiconductor production method for effectively reducing MOS device GIDL electric currents how is provided, it has also become industry The technical issues of urgently to be resolved hurrily.
Invention content
The present invention provides a kind of metal-oxide-semiconductor production methods for effectively reducing MOS device GIDL electric currents, effectively inhibit device Short-channel effect, improve device performance.Specifically, manufacturing method provided by the invention includes the following steps：
A kind of MOSFET manufacturing methods, including：
A., substrate is provided；
B. pseudo- gate stack is formed on substrate；
C. source and drain extension is formed in pseudo- gate stack both sides；
D. diffusion barrier region is formed in the substrate of leakage expansion area side；
E. side wall is formed in pseudo- gate stack both sides, source-drain area is formed in side wall both sides and annealed；
F. the interlayer dielectric layer of covering source-drain area is formed, removes pseudo- gate stack to form pseudo- grid vacancy；
G. gate stack is formed in the pseudo- grid vacancy.
Wherein, extended drain region is wrapped in the range of the diffusion barrier region, forms the impurity element of the diffusion barrier region It is carbon, the impurity concentration of the diffusion barrier region is more than le18cm-3。
Wherein, the method for forming the diffusion barrier region is ion implanting, and direction and the substrate of the ion implanting hang down Directly, and using mask plate the substrate of source is covered；Alternatively, the angle of the ion implanting is more than α, wherein tan α=L/H, L are source The length of expansion area, H are the thickness of pseudo- gate stack.
Wherein, after annealing, the source extension section length is more than leakage expansion area.
Correspondingly, the present invention also provides a kind of MOSFET structure, including：
Substrate；
Gate stack above the substrate；
Source-drain area in the substrate of the gate stack both sides；
Cover the interlayer dielectric layer of the source-drain area；
Source and drain extension below gate stack both sides of the edge；
Diffusion barrier region in the substrate of source-drain area,
Wherein, the length of the source expansion area is more than the length of leakage expansion area.
Wherein, the diffusion impervious layer is located in the substrate of drain region side, forms the impurity element of the diffusion barrier region It is carbon, the impurity concentration of the diffusion barrier region is more than l018cm-3。
According to mos transistor structure provided by the invention, by forming diffusion resistance in the Semiconductor substrate of drain terminal side Only area, after inhibiting to be formed in source and drain extension, the impurity diffusion caused by the factors such as the annealing in subsequent technique subtracts The length that small leakage expansion area is spread into the substrate below grid reduces the region of GIDL effects effect, so as to effectively Ground is reduced as the leakage current caused by GIDL effects.Compared with prior art, the present invention restrained effectively short-channel effect Harmful effect, reduce process complexity, improve device performance.
Description of the drawings
By reading the detailed description made to non-limiting example made with reference to the following drawings, of the invention is other Feature, objects and advantages will become more apparent upon：
Fig. 1~Figure 11 is the sectional view according to each fabrication stages of MOSFET in the specific embodiment of the present invention.
The same or similar reference numeral represents the same or similar component in attached drawing.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with implementation of the attached drawing to the present invention Example is described in detail.
The embodiment of the present invention is described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning to end Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached The embodiment of figure description is exemplary, and is only used for explaining the present invention, and is not construed as limiting the claims.
The present invention provides a kind of MOSFET structure, including：
Substrate 100；
Gate stack 600 above the substrate 100；
Source-drain area 102 in the 600 both sides substrate of gate stack；
Cover the interlayer dielectric layer 500 of the source-drain area；
Source and drain extension 101a, 101b below 600 both sides of the edge of gate stack；
Diffusion barrier region 105 in the substrate of source-drain area 102,
Wherein, the length of the source expansion area 101a is more than the length of leakage expansion area 101b.
Wherein, the diffusion impervious layer 105 is located in the substrate 100 of drain region side, forms the diffusion barrier region 105 Impurity element is carbon, and the impurity concentration of the diffusion barrier region 105 is more than le18cm-3。
Semiconductor channel area is located at the surface of substrate, and preferred material is monocrystalline silicon or monocrystalline germanium alloy firm, thickness For 5~20nm.The region be pole be lightly doped even it is undoped.In the case of doping, doping type is adulterated with source-drain area On the contrary.
Source region and drain region are located at 600 both sides of gate stack respectively, in the semiconductor layer above substrate.The thickness of source region is more than The thickness in drain region.It is more than the channel thickness of close drain terminal side by the channel portion thickness of source area side, is 10nm~60nm.
The production method of the present invention is described in detail below in conjunction with the accompanying drawings, is included the following steps.It should be noted that The attached drawing of each embodiment of the present invention is not necessarily to scale merely to the purpose of signal.
Substrate 100 is provided first, and the substrate material can be element semiconductor, such as silicon, germanium or compound half Conductor, such as gallium nitride, GaAs, indium phosphide.In view of processing compatibility, in the present embodiment, it is preferred that using silicon conduct The material of substrate 100.
Next, pseudo- grid structure 200 is formed on the substrate 100, as shown in Figure 1.Dummy gate structure 200 can be Individual layer or multilayer.Pseudo- grid structure 200 can include polymer material, non-crystalline silicon, polysilicon or TiN, and thickness can Think 10nm~200nm.In the present embodiment, pseudo- grid structure includes polysilicon and titanium dioxide, specifically, using chemical vapour deposition Method polysilicon is filled in grid vacancy, height is slightly below 10~20nm of side wall, then rectangular into one on the polysilicon Layer silica dioxide medium layer, forming method can be epitaxial growth, oxidation, CVD etc..Then using stand CMOS photoetching and It etches the pseudo- gate stack deposited and forms gate electrode figure.The part shape covered in SiGe channel layer 101 by gate dielectric layer Into the channel region of transistor.It should be noted that below unless otherwise noted, the deposit of various dielectric materials in the embodiment of the present invention The above-mentioned cited same or similar method of formation gate dielectric layer can be used, so it will not be repeated.
Next, being doped to the substrate of pseudo- 200 both sides of grid structure, to form source and drain extension 101a, 101b, such as scheme Shown in 2.Halo injections can also be carried out, to form Halo injection regions.The wherein dopant type and type of device of source and drain extension Unanimously, the dopant type of Halo injections is opposite with type of device.
Next, deposit photoresist on the semiconductor structure, then by exposing, developing, expose it The semiconductor structure of drain terminal side, as shown in Figure 3.Next, the ion carried out to the semiconductor structure in vertical direction is noted Enter, to form diffusion barrier region in drain terminal, as shown in Figure 3.The element for forming the diffusion barrier region is carbon, since carbon is neutral Impurity does not interfere with the carrier concentration in drain region, but substantially increase drain region side in expansion area is leaked after injection carbon Impurity concentration, the scattering frequency that so as to increase carrier diffusion when is subject to efficiently reduce carrier in leakage expansion area Diffusion length.Specifically, the impurity concentration of the diffusion barrier region 105 is more than le18cm-3.Device after the completion of ion implanting Cross-sectional view of the structure is as shown in Figure 4.
Optionally, when forming diffusion barrier region 105, it is possible to use pseudo- gate stack replaces photoresist as mask, passes through The method of inclined ion implanting realizes the injection of carbon.Specifically, as shown in figure 5, the minimum angles of ion implanting be α, wherein Tan α=L/H, L are the length of source expansion area 101a, and H is the thickness of pseudo- gate stack 200.Likewise, the diffusion barrier region formed 105 impurity concentration is more than le18cm-3.Device architecture sectional view after the completion of ion implanting is as shown in Figure 6.
Next, side wall 201 is formed on the side wall of gate stack, for grid to be separated.Specifically, it is formed sediment with LPCVD The sacrifice side wall medium layer silicon nitride of product 40nm~80nm thickness, then with the technology of receiving a visitor, gate electrode both sides formation width is 35nm again The silicon nitride spacer 201 of~75nm.Side wall 201 can also by silica, silicon oxynitride, silicon carbide and combinations thereof and/or other Suitable material is formed.Side wall 201 can have multilayered structure.Side wall 201 can also be formed by including deposition-etch technique, Its thickness range can be 10nm-100nm, such as 30nm, 50nm or 80nm.
Next, the silica dioxide medium layer that a layer thickness is 10nm~35nm thickness is deposited on the semiconductor structure, And using the dielectric layer as buffer layer, ion implanting source-drain area.For P-type crystal, dopant is boron or boron fluoride or indium or gallium Deng.For N-type crystal, dopant is phosphorus or arsenic or antimony etc..Doping concentration is 5e1019cm-3~le1020cm-3.Source-drain area is mixed After the completion of miscellaneous, interlayer dielectric layer 500 is formed on the semiconductor structure.In the present embodiment, the material of interlayer dielectric layer 500 For silica.The semiconductor structure for having deposited interlayer dielectric layer 500 is as shown in Figure 7.
It after the completion of source and drain injection, anneals to the semiconductor structure, to eliminate in ion implantation process described half Defect and interfacial state are eliminated in the damage generated in conductor structure.Specifically, temperature range during annealing is 600 DEG C~900 DEG C. During annealing, the impurity in semiconductor source drain region 102 and source and drain extension 101a, 101b can be expanded in high temperature Dissipate redistribution.Due to the presence of diffusion barrier region 105 in semiconductor, the impurity of leakage expansion area 101b is suffered in diffusion to be dissipated The impurity much larger than source expansion area 101a is penetrated, therefore its diffusion length greatly reduces, due to impurity diffusion redistribution to grid The distance of lower section extension is much smaller than source side.As shown in figure 9, the length of leakage expansion area 101b is much smaller than source and drain extension 101a Length, the area in drain region and grid overlapping region is effectively reduced, so as to effectively reduce caused by GIDL effects Leakage current.
Next, depositing silica on the semiconductor structure, interlayer dielectric layer 500 is formed.Specifically, it can be used The methods of CVD, epitaxial growth, oxidation, carries out silicon dioxide growth, is chemically-mechanicapolish polished to the silicon dioxide layer, reveals Go out pseudo- gate stack, as shown in Figure 10.Next, removal dummy gate structure 200, forms pseudo- grid vacancy.The pseudo- grid structure 200 of removal Wet etching may be used and/or dry etching removes, as shown in Figure 10.In the present embodiment, using plasma etches.
Next, as shown in figure 11, gate stack 600 is formed in grid vacancy.Gate stack can be only metal gate Pole, or there is silicide on metal/Polysilicon Composite Structures grid, wherein polysilicon upper surface.
Specifically, it is preferred that next the gate dielectric layer 601 in pseudo- grid vacancy deposits work function regulating course 602, it Form gate metal layer 603 on workfunction layers again afterwards.The gate dielectric layer 601 can be thermal oxide layer, including Silica, silicon oxynitride；Be alternatively high K dielectric, for example, HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON、HfTaON、HfTiON、Al2O3、La2O3、ZrO2, a kind of or combination in LaAlO, the thickness of gate dielectric layer 601 Can be 1nm-10nm, such as 3nm, 5nm or 8nm.Thermal oxide, chemical vapor deposition (CVD) or atomic layer deposition may be used (ALD) etc. techniques form gate dielectric layer 601.
Workfunction layers may be used the materials such as TiN, TaN and be made, and thickness range is 3nm~15nm.Metallic conductor Layer can be one layer or multilayered structure.Its material can be TaN, TaC, TiN, TaAlN, TiAlN, MoAlN, TaTbN, TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTaxIn a kind of or combination.Its thickness range for example can be 10nm-40nm, such as 20nm or 30nm.
The honest and kind technique of conventional cmos is finally entered, including clicking passivation layer, opening contact hole and metallization etc., you can system The ultra-thin SOI MOS transistor.
The present invention increases current-carrying by forming diffusion barrier region 105 in the semiconductor structure of leakage expansion area 101b sides Scattering that son is subject to reduces the leakage current caused by GIDL come carrier when inhibiting annealing in diffusion.In the present invention, The element for forming the diffusion barrier region is carbon, since carbon is neutral impurity, is not interfered with after injection carbon in expansion area is leaked The carrier concentration in drain region, but substantially increase the impurity concentration of drain region side, during so as to increase carrier diffusion by Scattering frequency, efficiently reduce leakage expansion area in carrier diffusion length so that leakage expansion area 101b length it is far small In the length of source and drain extension 101a, effectively reduce the area in drain region and grid overlapping region, so as to effectively reduce due to Leakage current caused by GIDL effects.Improve device performance.
Although be described in detail about example embodiment and its advantage, it should be understood that do not depart from the present invention spirit and In the case of protection domain defined in the appended claims, various change, substitutions and modifications can be carried out to these embodiments.It is right In other examples, those of ordinary skill in the art should be readily appreciated that while keeping in the scope of the present invention, technique The order of step can change.
In addition, the application range of the present invention is not limited to technique, mechanism, the system of the specific embodiment described in specification It makes, material composition, means, method and step.It, will be easy as those of ordinary skill in the art from the disclosure Ground understands, for current technique that is existing or will developing later, mechanism, manufacture, material composition, means, method or Step, the knot that wherein they perform the function being substantially the same with the corresponding embodiment of the invention described or acquisition is substantially the same Fruit can apply them according to the present invention.Therefore, appended claims of the present invention are intended to these techniques, mechanism, system It makes, material composition, means, method or step are included in its protection domain.

Claims (10)

1. a kind of MOSFET manufacturing methods, including：
A., substrate (100) is provided；
B. pseudo- gate stack (200) is formed on substrate；
C. source expansion area (101a) and leakage expansion area (101b) are formed in pseudo- gate stack (200) both sides；
D. diffusion barrier region (105) are formed in the substrate of described leakage expansion area (101b) side, wherein, form the diffusion resistance The impurity element for keeping off area (105) is carbon；
E. side wall (201) is formed in pseudo- gate stack (200) both sides, source-drain area (102) is formed in side wall (201) both sides and is moved back Fire；
F. the interlayer dielectric layer (500) of covering source-drain area (102) is formed, removes pseudo- gate stack (200) to form pseudo- grid vacancy；
G. gate stack is formed in the pseudo- grid vacancy.
2. manufacturing method according to claim 1, which is characterized in that included in the range of the diffusion barrier region (105) Leakage expansion area (101b).
3. manufacturing method according to claim 1 or 2, which is characterized in that the impurity of the diffusion barrier region (105) is dense Degree is more than 1e18cm-3。
4. manufacturing method according to claim 1, which is characterized in that the method for forming the diffusion barrier region (105) It is ion implanting.
5. manufacturing method according to claim 4, which is characterized in that the direction of the ion implanting and substrate transverse, and Use the substrate (100) of mask plate covering source.
6. manufacturing method according to claim 4, which is characterized in that the angle of the ion implanting is more than α, wherein tan α =L/H, L are the length of the source expansion area (101a), and H is the thickness of pseudo- gate stack (200).
7. manufacturing method according to claim 1, which is characterized in that after annealing, source expansion area (101a) length is big In leakage expansion area (101b).
8. a kind of MOSFET structure, including：
Substrate (100)；
Gate stack (600) above the substrate (100)；
Source-drain area (102) in the substrate of the gate stack (600) both sides；
Cover the interlayer dielectric layer (500) of the source-drain area (102)；
Source expansion area (101a) and leakage expansion area (101b) below gate stack (600) both sides of the edge；
Diffusion barrier region (105) in the substrate of the source-drain area (102), wherein, form the diffusion barrier region (105) Impurity element be carbon；
Wherein, the length of the source expansion area (101a) is more than the length of leakage expansion area (101b).
9. MOSFET structure according to claim 8, which is characterized in that the diffusion barrier region (105) is positioned at drain region one In the substrate (100) of side.
10. MOSFET structure according to claim 8, which is characterized in that the impurity of the diffusion barrier region (105) is dense Degree is more than 1e18cm-3。
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