CN105225956A - A kind of FinFET manufacture method - Google Patents

A kind of FinFET manufacture method Download PDF

Info

Publication number
CN105225956A
CN105225956A CN201410295576.5A CN201410295576A CN105225956A CN 105225956 A CN105225956 A CN 105225956A CN 201410295576 A CN201410295576 A CN 201410295576A CN 105225956 A CN105225956 A CN 105225956A
Authority
CN
China
Prior art keywords
fin
manufacture method
layer
impurity
ptsl
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410295576.5A
Other languages
Chinese (zh)
Inventor
尹海洲
刘云飞
张珂珂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201410295576.5A priority Critical patent/CN105225956A/en
Priority to PCT/CN2014/088594 priority patent/WO2015196639A1/en
Publication of CN105225956A publication Critical patent/CN105225956A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Abstract

The invention provides a kind of FinFET manufacture method, comprising: a. provides substrate (100), and form fin (200) over the substrate; The substrate of b. described fin (200) both sides forms separator (300); C. in the fin of described separator (300) the first half both sides, break-through barrier layer (310) and diffusion impervious layer (320) is formed; D. form source-drain area respectively at described fin two ends, in the middle part of described fin, form grid structure, and fill interlayer dielectric layer (500) in described separator (300) top.By method provided by the invention, effectively optimize PTSL distribution, improve device performance.

Description

A kind of FinFET manufacture method
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, particularly, relate to a kind of FinFET manufacture method.
Technical background
Along with the dimensions scale downward of semiconductor device, occur that threshold voltage reduces and the problem of decline with channel length, also, created short-channel effect in the semiconductor device.Relate to the challenge with manufacture view in order to tackle from semiconductor, result in FinFET, i.e. the development of FinFET.
Channel punchthrough effect (Channelpunch-througheffect) is that a kind of phenomenon be connected with the depletion region of drain junction is tied in the source of field-effect transistor.Work as channel punchthrough, just make the potential barrier between source/drain significantly reduce, then namely inject a large amount of charge carrier from source toward raceway groove, and drift by the space charge region between source-leakage, form one very large electric current; The large young pathbreaker of this electric current is subject to the restriction of space charge, is so-called space charge limited current.This space charge limited current is that the channel current controlled with grid voltage is in parallel, and therefore the total current made by device increases by channel punchthrough greatly; And in channel punchthrough situation, even if gate voltage is lower than threshold voltage, also has electric current between source-leakage and pass through.This effect is a kind of effect likely occurred in small size field-effect transistor, and along with the further reduction of channel width, it is also more and more significant on the impact of device property.
In FinFET, usually adopt and heavy doping is carried out to the fin portion below raceway groove, namely form break-through barrier layer (PTSL), suppress channel punchthrough effect.The method forming PTSL generally has two kinds, and relatively more conventional is that the method injected by direct ion forms heavily doped region in trench bottom.The PTSL distribution that this method is formed is comparatively large, often introduces impurity in channels, and the process of ion implantation itself also can form defect in channels simultaneously, affects device performance.Another kind method forms PTSL by sidewise scattered method, namely in raceway groove, directly do not carry out ion implantation, but impurity is injected fin both sides STI.Because fin itself is very thin, due to the scattering process of charge carrier itself, impurity can diffuse in fin from STI, forms PTSL distribution.The PTSL distribution that this method is formed is concentrated, and can not introduce defect in channels, significantly improves device performance.
But after PTSL is formed, owing to there is annealing for several times in subsequent technique, the impurity in PTSL at high temperature can be formed and distribute, spreads, thus introduce impurity in channels in raceway groove, affects threshold voltage and the Sub-Threshold Characteristic of device.Therefore, need to be optimized above-mentioned technique, address this problem.
Summary of the invention
The invention provides a kind of FinFET manufacture method, effectively optimize PTSL distribution, make it well concentrate on the place of punchthrough current generation, inhibit it to the diffusion of raceway groove, do not affect other performances of device simultaneously, do not increase process complexity.Concrete, the method comprises:
A kind of FinFET manufacture method, comprising:
A. provide substrate, and form fin over the substrate;
The substrate of b. described fin both sides forms separator;
C. in the fin of described separator the first half both sides, break-through barrier layer and diffusion impervious layer is formed;
D. form source-drain area respectively at described fin two ends, in the middle part of described fin, form grid structure, and fill interlayer dielectric layer above described separator.
Wherein, described break-through barrier layer and diffusion impervious layer are formed by the lateral scattering during foreign particle during ion implantation is from separator to fin.
Wherein, for N-type device, the impurity forming described break-through barrier layer is boron; The impurity forming described diffusion barrier region is carbon; The implantation dosage of described diffusion barrier region is 1.5e15cm -2~ 7.5e15cm -2.For P type device, the impurity forming described break-through barrier layer is phosphorus; The impurity forming described diffusion barrier region is germanium; The implantation dosage of described diffusion barrier region is 3e14cm -2~ 1.5e15cm -2.
Method provided by the invention, is namely formed in the technique of PTSL in lateral scattering, when injection PTSL impurity, inject corresponding diffusion simultaneously and stop impurity, for N-type device, the impurity forming PTSL is generally B, and corresponding diffusion barrier impurity is C; For P type device, the impurity forming PTSL is generally P, and corresponding diffusion barrier impurity is Ge.Diffusion barrier impurity can the diffusion of inhibition of impurities effectively, avoids PTSL distributing again in subsequent technique, optimized device performance.Adopt in this way, effectively under existing process conditions, PTSL can be made effectively to be distributed in the region of punchthrough current generation, and Impurity Distribution can not be introduced in channels, effectively optimize PTSL technique, improve device performance.
Accompanying drawing explanation
Fig. 1 ~ Fig. 4 schematically shows the profile formed according to each stage semiconductor structure of the method for manufacture semiconductor fin of the present invention; Wherein Fig. 1 illustrates the profile of the semiconductor structure after forming fin step;
Fig. 2 illustrates the profile form separator on the substrate of fin both sides after;
Fig. 3 illustrates the schematic diagram forming the step of break-through barrier layer and diffusion impervious layer in the fin of described separator the first half both sides;
Fig. 4 illustrates that described break-through barrier layer and diffusion impervious layer are the schematic diagram formed by the lateral scattering during foreign particle during ion implantation is from separator to fin.
Fig. 5 schematically shows the three-dimensional equiangular figure formed according to each stage semiconductor structure of the method for manufacture semiconductor fin of the present invention.
Embodiment
For the problems referred to above, the invention provides a kind of FinFET manufacture method, make PTSL effectively be distributed in the region of punchthrough current generation, and Impurity Distribution can not be introduced in channels.Concrete, the method comprises:
A., substrate 100 is provided, and is forming fin 200 over the substrate;
The substrate of b. described fin 200 both sides forms separator 300;
C. in the fin of described separator 300 the first half both sides, break-through barrier layer 310 and diffusion impervious layer 320 is formed;
D. form source-drain area respectively at described fin two ends, in the middle part of described fin, form grid structure, and fill interlayer dielectric layer 500 above described separator 300.Wherein, described break-through barrier layer 310 and diffusion impervious layer 320 are formed to the lateral scattering fin 200 from separator 300 by foreign particle during ion implantation.
Wherein, for N-type device, the impurity forming described break-through barrier layer 310 is boron; The impurity forming described diffusion barrier region 320 is carbon; The implantation dosage of described diffusion barrier region 320 is 1.5e15cm -2~ 7.5e15cm -2.For P type device, the impurity forming described break-through barrier layer 310 is phosphorus; The impurity forming described diffusion barrier region 320 is germanium; The implantation dosage of described diffusion barrier region 203 is 3e14cm -2~ 1.5e15cm -2.
Method provided by the invention, is namely formed in the technique of PTSL in lateral scattering, when injection PTSL impurity, inject corresponding diffusion simultaneously and stop impurity, for during N-type, the impurity forming PTSL is generally B, and corresponding diffusion barrier impurity is C; For during P type, the impurity forming PTSL is generally P, and corresponding diffusion barrier impurity is Ge.Diffusion barrier impurity can the diffusion of inhibition of impurities effectively, avoids PTSL distributing again in subsequent technique, optimized device performance.Adopt in this way, effectively under existing process conditions, PTSL can be made effectively to be distributed in the region of punchthrough current generation, and Impurity Distribution can not be introduced in channels, effectively optimize PTSL technique, improve device performance.
Hereinafter with reference to accompanying drawing, the invention of this reality is described in more detail.In various figures, identical element adopts similar Reference numeral to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.
Be to be understood that, when the structure of outlines device, when one deck, region are called be positioned at another layer, another region " above " or " top " time, can refer to be located immediately at another layer, another over, or itself and another layer, also comprise other layer or region between another region.Further, if overturn by device, this one deck, a region will be positioned at another layer, another region " below " or " below ".
If in order to describe the situation being located immediately at another layer, another over, will adopt herein " directly exist ... above " or " ... above and adjoin with it " form of presentation.
Describe hereinafter many specific details of the present invention, the structure of such as device, material, size, treatment process and technology, more clearly to understand the present invention.But just as the skilled person will understand like that, the present invention can be realized not in accordance with these specific details.Such as, the semi-conducting material of substrate and fin can be selected from IV race semiconductor, as Si or Ge, or Group III-V semiconductor, as GaAs, InP, GaN, SiC, or the lamination of above-mentioned semi-conducting material.
See Fig. 1, the invention is intended to make the semiconductor fin 200 be positioned at above substrate 100.As just example, substrate 100 and fin 200 are all made up of silicon.By etching this semiconductor layer at the surperficial epitaxial semiconductor layer of substrate 100 and form fin 200, described epitaxial growth method can be molecular beam epitaxy MBE or additive method, and described lithographic method can be dry etching or dry/wet etching.Fin 200 is highly 100 ~ 150nm.
Fin 200 carries out separator to described semiconductor structure, to form insulation layer structure 300, as shown in Figure 3 after being formed.Preferably, in semiconductor fin 200, silicon nitride and buffering silicon dioxide figure is first become, as the mask of trench etching.Next the groove with certain depth and sidewall angle is eroded away on the substrate 100.Then skim silicon dioxide is grown, with the drift angle of round and smooth groove and the damage removed in silicon face introducing in etching process.Carry out trench fill after oxidation, filled media can be silicon dioxide.Following use CMP carries out planarization to semiconductor substrate surface, and silicon nitride is as the barrier layer of CMP.Afterwards, be mask, etch semicon-ductor structure surface, introduce longitudinal diffusion when spreading in subsequent technique in fin 200 with silicon nitride, described etching depth is greater than actual required fin height.After having etched, form insulation layer structure 300, its distance from top fin 200 top 20 ~ 60nm.Finally use the phosphoric acid of heat to take out the silicon nitride exposed, expose fin 200.
Next, as shown in Figure 3, above described fin 200, form mask layer 201, as the mask that next step intermediate ion injects, protection fin 200 is not injected by impurity.This mask layer 201 can be silica or silicon nitride, preferably, adopts silicon nitride in the present embodiment, and its thickness is 30 ~ 50nm.
Mask layer 201 carries out ion implantation to described semiconductor structure, forms break-through barrier layer 310 in separator 300 after being formed.Concrete, described break-through barrier layer 310 and diffusion impervious layer 320 are formed to the lateral scattering fin 200 from separator 300 by foreign particle during ion implantation simultaneously.Remove mask layer 201 afterwards, device architecture as shown in Figure 4.
In the prior art, after forming PTSL by lateral scattering, due to the several high annealing in subsequent technique, PTSL can continue diffusion and distribute, diffuses in raceway groove, introduces impurity in channels, affects threshold voltage and other performances of device.In order to suppress this shortcoming, the present invention injects diffusion impervious layer while injection break-through barrier layer.For N-type device, the impurity forming PTSL is generally B, and corresponding diffusion barrier impurity is C; For P type device, the impurity forming PTSL is generally P, and corresponding diffusion barrier impurity is Ge.Diffusion barrier impurity can the diffusion of inhibition of impurities effectively, avoids PTSL distributing again in subsequent technique, optimized device performance.And because carbon and germanium are originally as quadrivalent element, can not introduce unwanted charge carrier, not have an impact to device property, thus the PTSL that optimizes optimized distributes and does not affect process complexity.
Next, above raceway groove, form pseudo-gate stack, and form source-drain area.Described pseudo-gate stack can be individual layer, also can be multilayer.Pseudo-gate stack can comprise polymeric material, amorphous silicon, polysilicon or TiN, and thickness can be 10 ~ 100nm.The techniques such as thermal oxidation, chemical vapour deposition (CVD) (CVD), ald (ALD) can be adopted to form pseudo-gate stack.Described source-drain area formation method can be that then ion implantation anneals active ions, in-situ doped extension and/or the combination of the two.
Alternatively, the sidewall of gate stack forms side wall, for being separated by grid.Side wall can by silicon nitride, silica, silicon oxynitride, carborundum and combination thereof, and/or other suitable materials are formed.Side wall can have sandwich construction.Side wall can be formed by comprising deposition-etch technique, and its thickness range can be 10nm-100nm, as 30nm, 50nm or 80nm.
Next, deposit interlayer dielectric layer 400, and parallel flat, expose pseudo-gate stack.Concrete, interlayer dielectric layer 400 can pass through CVD, high-density plasma CVD, spin coating or other suitable methods and be formed.The material of interlayer dielectric layer 400 can adopt and comprise SiO 2, carbon doping SiO 2, BPSG, PSG, UGS, silicon oxynitride, low-k materials or its combination.The thickness range of interlayer dielectric layer 400 can be 40nm-150nm, as 80nm, 100nm or 120nm.Next, perform planarization, pseudo-gate stack is come out, and flush with interlayer dielectric layer 400 (term in the present invention " flushes " difference in height that refers between the two in the scope that fabrication error allows).
Next, remove pseudo-gate stack, expose channel part.Concrete, pseudo-grid structure can adopt wet etching and/or dry quarter to remove.In one embodiment, using plasma etching.
Next, in pseudo-grid room, form grid structure 500, grid structure 500 comprises gate dielectric layer, work function regulating course and gate metal layer, as shown in Figure 5.Concrete, described gate dielectric layer can be thermal oxide layer, comprises silica, silicon oxynitride; Also can be high K dielectric, such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al 2o 3, La 2o 3, ZrO 2, one in LaAlO or its combination, the thickness of gate dielectric layer can be 1nm-10nm, such as 3nm, 5nm or 8nm.Described work function regulating course can adopt the materials such as TiN, TaN to make, and its thickness range is 3nm ~ 15nm.Described gate metal layer can be one deck or sandwich construction.Its material can be TaN, TaC, TiN, TaAlN, TiAlN, MoAlN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x, NiTa xin one or its combination.Its thickness range can be such as 10nm-40nm, as 20nm or 30nm.
What the method described in the present embodiment adopted is rear grid technique, but those of skill in the art can very clearly know, this invention may be used for first grid technique equally, does not repeat them here.
Method provided by the invention, is namely formed in the technique of PTSL in lateral scattering, when injection PTSL impurity, inject corresponding diffusion simultaneously and stop impurity, for N-type device, the impurity forming PTSL is generally B, and corresponding diffusion barrier impurity is C; For P type device, the impurity forming PTSL is generally P, and corresponding diffusion barrier impurity is Ge.Diffusion barrier impurity can the diffusion of inhibition of impurities effectively, avoids PTSL distributing again in subsequent technique, optimized device performance.Adopt in this way, effectively under existing process conditions, PTSL can be made effectively to be distributed in the region of punchthrough current generation, and Impurity Distribution can not be introduced in channels, effectively optimize PTSL technique, improve device performance.
Although describe in detail about example embodiment and advantage thereof, being to be understood that when not departing from the protection range of spirit of the present invention and claims restriction, various change, substitutions and modifications can being carried out to these embodiments.For other examples, those of ordinary skill in the art should easy understand maintenance scope in while, the order of processing step can change.
In addition, range of application of the present invention is not limited to the technique of the specific embodiment described in specification, mechanism, manufacture, material composition, means, method and step.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technique existed at present or be about to develop, mechanism, manufacture, material composition, means, method or step later, wherein their perform the identical function of the corresponding embodiment cardinal principle that describes with the present invention or obtain the identical result of cardinal principle, can apply according to the present invention to them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.

Claims (8)

1. a FinFET manufacture method, comprising:
A., substrate (100) is provided, and is forming fin (200) over the substrate;
The substrate of b. described fin (200) both sides forms separator (300);
C. in the fin of described separator (300) the first half both sides, break-through barrier layer (310) and diffusion impervious layer (320) is formed;
D. form source-drain area respectively at described fin two ends, in the middle part of described fin, form grid structure, and fill interlayer dielectric layer (500) in described separator (300) top.
2. manufacture method according to claim 1, it is characterized in that, described break-through barrier layer (310) and diffusion impervious layer (320) are formed to the lateral scattering fin (200) from separator (300) by foreign particle during ion implantation.
3. manufacture method according to claim 2, is characterized in that, for N-type device, the impurity forming described break-through barrier layer (310) is boron.
4. manufacture method according to claim 3, is characterized in that, the impurity forming described diffusion barrier region (320) is carbon.
5. manufacture method according to claim 4, is characterized in that, the implantation dosage of described diffusion barrier region (320) is 1.5e15cm -2~ 7.5e15cm -2.
6. manufacture method according to claim 2, is characterized in that, for P type device, the impurity forming described break-through barrier layer (310) is phosphorus.
7. manufacture method according to claim 6, is characterized in that, the impurity forming described diffusion barrier region (320) is germanium.
8. manufacture method according to claim 7, is characterized in that, the implantation dosage of described diffusion barrier region (203) is 3e14cm -2~ 1.5e15cm -2.
CN201410295576.5A 2014-06-26 2014-06-26 A kind of FinFET manufacture method Pending CN105225956A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201410295576.5A CN105225956A (en) 2014-06-26 2014-06-26 A kind of FinFET manufacture method
PCT/CN2014/088594 WO2015196639A1 (en) 2014-06-26 2014-10-15 Finfet manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410295576.5A CN105225956A (en) 2014-06-26 2014-06-26 A kind of FinFET manufacture method

Publications (1)

Publication Number Publication Date
CN105225956A true CN105225956A (en) 2016-01-06

Family

ID=54936596

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410295576.5A Pending CN105225956A (en) 2014-06-26 2014-06-26 A kind of FinFET manufacture method

Country Status (2)

Country Link
CN (1) CN105225956A (en)
WO (1) WO2015196639A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785425A (en) * 2016-08-31 2018-03-09 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof
CN107785424A (en) * 2016-08-31 2018-03-09 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof
CN107785422A (en) * 2016-08-29 2018-03-09 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and its manufacture method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080132019A1 (en) * 2006-12-05 2008-06-05 Keh-Chiang Ku Short channel effect engineering in MOS device using epitaxially carbon-doped silicon
US20090267155A1 (en) * 2008-04-24 2009-10-29 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20130280883A1 (en) * 2012-04-24 2013-10-24 Globalfoundries Inc. Methods of forming bulk finfet devices so as to reduce punch through leakage currents
CN103855011A (en) * 2012-11-30 2014-06-11 中国科学院微电子研究所 Fin field effect transistor (FinFET) and manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8497171B1 (en) * 2012-07-05 2013-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET method and structure with embedded underlying anti-punch through layer
US8610201B1 (en) * 2012-08-16 2013-12-17 Kabushiki Kaisha Toshiba FinFET comprising a punch-through stopper
US8969932B2 (en) * 2012-12-12 2015-03-03 Globalfoundries Inc. Methods of forming a finfet semiconductor device with undoped fins

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080132019A1 (en) * 2006-12-05 2008-06-05 Keh-Chiang Ku Short channel effect engineering in MOS device using epitaxially carbon-doped silicon
US20090267155A1 (en) * 2008-04-24 2009-10-29 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20130280883A1 (en) * 2012-04-24 2013-10-24 Globalfoundries Inc. Methods of forming bulk finfet devices so as to reduce punch through leakage currents
CN103855011A (en) * 2012-11-30 2014-06-11 中国科学院微电子研究所 Fin field effect transistor (FinFET) and manufacturing method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785422A (en) * 2016-08-29 2018-03-09 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and its manufacture method
CN107785422B (en) * 2016-08-29 2021-07-13 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and manufacturing method thereof
CN107785425A (en) * 2016-08-31 2018-03-09 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof
CN107785424A (en) * 2016-08-31 2018-03-09 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof
CN107785425B (en) * 2016-08-31 2020-07-10 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming the same

Also Published As

Publication number Publication date
WO2015196639A1 (en) 2015-12-30

Similar Documents

Publication Publication Date Title
CN104576383B (en) A kind of FinFET structure and its manufacture method
TWI575573B (en) Finfets and methods of forming finfets
US8809173B1 (en) Fin field-effect transistors and fabrication method thereof
CN105097556A (en) Fin field effect transistor (FET) and manufacturing method thereof
CN104576382B (en) A kind of asymmetric FinFET structure and its manufacture method
US9385212B2 (en) Method for manufacturing semiconductor device
CN105097527B (en) A kind of FinFET manufacturing methods
CN104576385A (en) FinFET structure and manufacturing method thereof
CN104576380B (en) A kind of FINFET manufacture methods
CN104576386B (en) A kind of FinFET and its manufacture method
CN105097528A (en) FINFET manufacturing method
US20150380297A1 (en) Method for manufacturing mosfet
CN105225956A (en) A kind of FinFET manufacture method
CN104347707B (en) A kind of MOSFET structure and its manufacture method
CN104217948B (en) Semiconductor making method
CN104576384A (en) FinFET structure and manufacturing method thereof
CN105632930A (en) FinFET device and manufacturing method thereof
CN108281485A (en) Semiconductor structure and forming method thereof
CN103377931B (en) Semiconductor structure and manufacture method thereof
CN105336617A (en) FinFET manufacturing method
CN105225958A (en) The formation method of fin formula field effect transistor
CN105405886A (en) FinFET structure and manufacturing method thereof
CN105845569B (en) Fin field effect transistor and forming method thereof
CN104576338A (en) Mosfet structure and manufacturing method thereof
CN105632929A (en) FinFET device and manufacturing method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20160106

RJ01 Rejection of invention patent application after publication