CN107785425A - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN107785425A CN107785425A CN201610788845.0A CN201610788845A CN107785425A CN 107785425 A CN107785425 A CN 107785425A CN 201610788845 A CN201610788845 A CN 201610788845A CN 107785425 A CN107785425 A CN 107785425A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 111
- 238000000034 method Methods 0.000 title claims abstract description 74
- 230000004888 barrier function Effects 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 238000000137 annealing Methods 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims description 157
- 238000002955 isolation Methods 0.000 claims description 69
- 239000011241 protective layer Substances 0.000 claims description 66
- 238000005516 engineering process Methods 0.000 claims description 39
- 238000005468 ion implantation Methods 0.000 claims description 35
- 238000002513 implantation Methods 0.000 claims description 29
- 239000007943 implant Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 12
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- 239000004576 sand Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- DZPJVKXUWVWEAD-UHFFFAOYSA-N [C].[N].[Si] Chemical compound [C].[N].[Si] DZPJVKXUWVWEAD-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 1
- 229910052738 indium Inorganic materials 0.000 claims 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 150000002500 ions Chemical class 0.000 description 124
- 230000008569 process Effects 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000005669 field effect Effects 0.000 description 7
- -1 phosphonium ion Chemical class 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 3
- 229910001449 indium ion Inorganic materials 0.000 description 3
- 239000012071 phase Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 210000005056 cell body Anatomy 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
Abstract
A kind of semiconductor devices and forming method thereof, wherein method includes：Semiconductor substrate is provided, there is fin in the Semiconductor substrate；Barrier layer is formed in the fin, has in the barrier layer and stops ion；After forming the barrier layer, anti- break-through layer is formed in the fin, the top surface on the barrier layer is higher than or is flush to the top surface of anti-break-through layer, has anti-break-through ion in the anti-break-through layer, the conduction type of the anti-break-through ion and it is described stop ion conduction type it is opposite；After forming the anti-break-through layer, made annealing treatment.Methods described can improve the electric property of semiconductor devices.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of semiconductor devices and forming method thereof.
Background technology
MOS (Metal-oxide-semicondutor) transistor, it is one of most important element in modern integrated circuits.MOS is brilliant
The basic structure of body pipe includes：Semiconductor substrate；Positioned at the grid structure of semiconductor substrate surface, the grid structure includes：
Gate dielectric layer positioned at semiconductor substrate surface and the gate electrode layer positioned at gate dielectric layer surface；Positioned at grid structure both sides half
Source and drain doping area in conductor substrate.
With the development of semiconductor technology, the MOS transistor of traditional plane formula dies down to the control ability of channel current,
Cause serious leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, and it generally comprises protrusion
In the fin of semiconductor substrate surface, the top surface of fin described in covering part and the grid structure of side wall, positioned at grid knot
Source and drain doping area in the fin of structure both sides.
In order to reduce influence of the short-channel effect to fin formula field effect transistor, channel leakage stream is reduced.A kind of method is
By carrying out anti-break-through injection to fin bottom, the probability of drain-source break-through is reduced, so as to reduce short-channel effect.
However, the electric property for the semiconductor devices that fin formula field effect transistor is formed still has much room for improvement in the prior art.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of semiconductor devices and forming method thereof, to improve the electricity of semiconductor devices
Learn performance.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, including：Semiconductor lining is provided
Bottom, there is fin in the Semiconductor substrate；Barrier layer is formed in the fin, has in the barrier layer and stops ion；
After forming the barrier layer, anti-break-through layer is formed in the fin, the top surface on the barrier layer is higher than or be flush to institute
State the top surface of anti-break-through layer, there is anti-break-through ion in the anti-break-through layer, the conduction type of the anti-break-through ion and
The conduction type of the stop ion is opposite；After forming the anti-break-through layer, made annealing treatment.
Optionally, forming the method on the barrier layer includes：Initial isolation structure, institute are formed on the semiconductor substrate
State the side wall of initial isolation structure covering part fin；Protection is formed in the fin portion surface that the initial isolation structure exposes
Layer；After forming the protective layer, the initial isolation structure of segment thickness is removed, forms isolation structure, the isolation structure and institute
State protective layer and expose part fin；Barrier layer is formed in the fin that the isolation structure and the protective layer expose.
Optionally, the top surface of the fin has mask layer；Forming the method for the protective layer includes：Described first
The fin side wall that beginning isolation structure exposes forms side wall protective layer；The side wall protective layer and the mask layer form protection
Layer.
Optionally, the material of the mask layer is silicon nitride or fire sand；The material of the side wall protective layer is nitridation
Silicon, fire sand or nitrogen carbon silicon boride.
Optionally, the side wall protective layer is also located at the side wall of the mask layer；The method for forming the side wall protective layer
Including：On the initial isolation structure, fin and the sidewall surfaces of mask layer and the top surface of mask layer formed initially
Side wall protective layer；The initial sidewall protective layer is etched back to until exposing the top table of initial isolation structure surface and mask layer
Face, form side wall protective layer.
Optionally, the thickness of the protective layer is 15 angstroms~50 angstroms.
Optionally, the fin that the isolation structure and protective layer expose is in the chi perpendicular to semiconductor substrate surface direction
Very little is 15 angstroms~300 angstroms.
Optionally, the method on formation barrier layer is in the fin that the isolation structure and the protective layer expose：Adopt
Injected with the first ion implantation technology in the fin that the isolation structure and protective layer expose and stop ion.
Optionally, when the conduction type of the anti-break-through ion is p-type, the conduction type for stopping ion is N-type.
Optionally, the stop ion is phosphonium ion；The parameter of first ion implantation technology includes：Implantation dosage is
1.0E12atom/cm2~5.0E13atom/cm2, Implantation Energy is 5KeV~20KeV, and implant angle is 10 degree~30 degree.
Optionally, the stop ion is arsenic ion；The parameter of first ion implantation technology includes：Implantation dosage is
1.0E12atom/cm2~5.0E13atom/cm2, Implantation Energy is 8KeV~30KeV, and implant angle is 10 degree~30 degree.
Optionally, when the conduction type of the anti-break-through ion is N-type, the conduction type for stopping ion is p-type.
Optionally, the stop ion is boron ion；The parameter of first ion implantation technology includes：Implantation dosage is
1.0E12atom/cm2~8.0E13atom/cm2, Implantation Energy is 1KeV~10KeV, and implant angle is 10 degree~30 degree.
Optionally, the stop ion is indium ion；The parameter of first ion implantation technology includes：Implantation dosage is
1.0E12atom/cm2~5.0E13atom/cm2, Implantation Energy is 5KeV~50KeV, and implant angle is 10 degree~30 degree.
Optionally, forming the method for the anti-break-through layer includes：Using the second ion implantation technology in the isolation structure
The middle anti-break-through ion of injection, makes anti-break-through ion diffuse into fin, forms anti-break-through layer in the fin.
Optionally, what the anti-break-through ion spread is oriented parallel to semiconductor substrate surface and perpendicular to fin extension side
To.
Optionally, the implant angle of second ion implantation technology is 0 degree.
Optionally, the atom percentage concentration for stopping ion is the 5% of the atom percentage concentration of anti-break-through ion
~30%.
Optionally, the parameter of the annealing includes：The gas of use includes N2, annealing temperature be 950 degrees Celsius~
1100 degrees Celsius.
The present invention also provides a kind of semiconductor devices, including：Semiconductor substrate, there is fin in the Semiconductor substrate；
Anti- break-through layer, in the fin, there is anti-break-through ion in the anti-break-through layer；Barrier layer, in the fin, institute
The top surface for stating barrier layer is higher than or is flush to the top surface of the anti-break-through layer, have in the barrier layer stop from
The conduction type of son, the conduction type for stopping ion and the anti-break-through ion is opposite.
Compared with prior art, technical scheme has advantages below：
The forming method of semiconductor devices provided by the invention, barrier layer is formd in the fin, there is resistance in barrier layer
Ion is kept off, the conduction type of the stop ion and the conduction type of the anti-break-through ion are opposite.In the annealing
During, the stop ion in the barrier layer is also diffused into the raceway groove at the top of fin, the stop diffused into raceway groove
Ion can offset the anti-break-through ion partly or completely diffused into raceway groove.So that anti-break-through ion pair semiconductor device
The influence of the threshold voltage of part reduces.So that the electric property of semiconductor devices improves.
Semiconductor devices provided by the invention, there is in fin barrier layer, have in the barrier layer and stop ion, it is described
Stop the conduction type of ion and the conduction type of the anti-break-through ion on the contrary, the stop ion can be in annealing
Into in the raceway groove at the top of fin, to offset the anti-break-through ion partly or completely diffused into raceway groove.So that anti-wear
The influence of the threshold voltage of logical ion pair semiconductor devices reduces.So that the electric property of semiconductor devices improves.
Brief description of the drawings
Fig. 1 to Fig. 3 is a kind of structural representation of semiconductor devices forming process；
Fig. 4 to Fig. 9 is the structural representation of semiconductor devices forming process in one embodiment of the invention.
Embodiment
As described in background, the electric property for the semiconductor devices that prior art is formed has much room for improvement.
Fig. 1 to Fig. 3 is a kind of structural representation of semiconductor devices forming process.
With reference to figure 1, there is provided Semiconductor substrate 100, there is fin 110 in the Semiconductor substrate 100.
With reference to figure 2, anti-break-through layer 120 is formed in the fin 110.
Fig. 3 is refer to, is formed after anti-break-through layer 120, is made annealing treatment, anti-is worn with activate in anti-break-through layer 120
Logical ion.
However, the electric property for the semiconductor devices that the above method is formed is poor, it has been investigated that, reason is：
Doped with threshold value ion in the raceway groove of semiconductor devices, the threshold value ion is used for the threshold value for adjusting semiconductor devices
Voltage.The conduction type of the threshold value ion is identical with the conduction type of the anti-break-through ion.In the mistake of the annealing
Cheng Zhong, raceway groove of the anti-break-through ion easily to the top of fin 101 in anti-break-through layer 120 spread, diffused into anti-in raceway groove
Break-through ion and threshold value ion adjust the threshold voltage of semiconductor devices jointly, cause the threshold voltage of semiconductor devices to raise.
Particularly with the semiconductor devices of ultralow threshold value voltage, the threshold voltage of semiconductor devices anti-is worn by diffuse into raceway groove
The influence of logical ion is very sensitive, therefore causes the threshold voltage of semiconductor devices too high, does not meet ultralow threshold value voltage and partly leads
The requirement of body device.Cause the electric property of semiconductor devices to reduce.
On this basis, the present invention provides a kind of forming method of semiconductor devices, including：Semiconductor substrate, institute are provided
Stating has fin in Semiconductor substrate；Barrier layer is formed in the fin, has in the barrier layer and stops ion；Form institute
After stating barrier layer, anti-break-through layer is formed in the fin, the top surface on the barrier layer is higher than or be flush to described anti-wear
Lead to the top surface of layer, there is anti-break-through ion, the conduction type of the anti-break-through ion and the resistance in the anti-break-through layer
The conduction type for keeping off ion is opposite；After forming the anti-break-through layer, made annealing treatment.
Due to foring barrier layer in the fin, have in barrier layer and stop ion, the conduction type for stopping ion
With the conduction type of the anti-break-through ion on the contrary, therefore during the annealing, the stop in the barrier layer
Ion is also diffused into the raceway groove at the top of fin, and the stop ion diffused into raceway groove can be offset partly or completely
The anti-break-through ion diffused into raceway groove.So that the influence of the threshold voltage of anti-break-through ion pair semiconductor devices reduces.From
And the electric property of semiconductor devices is improved.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 4 to Fig. 9 is the structural representation of semiconductor devices forming process in one embodiment of the invention.
With reference to figure 4, there is provided Semiconductor substrate 200, there is fin 210 in the Semiconductor substrate 200.
The Semiconductor substrate 200 can be monocrystalline silicon, polysilicon or non-crystalline silicon.Semiconductor substrate 200 can also be silicon,
The semi-conducting materials such as germanium, SiGe.In the present embodiment, the material of the Semiconductor substrate 200 is monocrystalline silicon.
In the present embodiment, the fin 210 is formed by the graphical Semiconductor substrate 200.In other embodiments
In, Ke Yishi：Fin material layer is formed on the semiconductor substrate, and then the graphical fin material layer, forms fin.
In the present embodiment, also it is used as figure formed with mask layer 220, the mask layer 220 in the top surface of fin 210
Change Semiconductor substrate 200 or graphical fin material layer to form the mask of fin 210.
In the present embodiment, after forming fin 210, retain mask layer 220, the mask layer 220 is additionally operable to subsequently carrying out
Fin 210 is protected during first ion implantation technology and the second ion implantation technology.In other embodiments, fin is formed
Afterwards, mask layer is removed.
In the present embodiment, the width of the fin 210 is 5nm~12nm.The width of the fin 210 refer to parallel to
The surface of Semiconductor substrate 200 and the size on the bearing of trend of fin 210.
The top area of the fin 210 adulterates different threshold value ions according to the type of the semiconductor devices of formation.
The threshold value ion is used for the threshold voltage for adjusting semiconductor devices.When semiconductor devices is N-type fin formula field effect transistor,
The conduction type of the threshold value ion is p-type, such as B ions or In ions；When semiconductor devices is p-type fin formula field effect transistor
When, the conduction type of the threshold value ion is N-type, such as P (phosphorus) ions or As ions.
Then, barrier layer is formed in the fin 210, has in the barrier layer and stops ion.
The process to form barrier layer is specifically introduced below with reference to Fig. 5 to Fig. 7.
With reference to figure 5, initial isolation structure 230, the initial isolation structure 230 are formed in the Semiconductor substrate 200
The side wall of covering part fin 210；Protective layer is formed on the surface of fin 210 that the initial isolation structure 230 exposes.
The material of the initial isolation structure 230 is silica or silicon oxynitride.In the present embodiment, initial isolation structure
230 material is silica.
Forming the method for the initial isolation structure 230 includes：Covering fin is formed in the Semiconductor substrate 200
210 and the initial isolation structure film of mask layer 220, the whole surface of the initial isolation structure film is higher than the top of mask layer 220
Portion surface；Remove the initial isolation structure film of the top surface higher than mask layer 220；Remove the top table higher than mask layer 220
After the initial isolation structure film in face, be etched back to the initial isolation structure film, form initial isolation structure 230, it is described initially every
Top surface from structure 230 is less than the top surface of fin 210.
The technique for forming the initial isolation structure film is depositing operation, such as fluid chemistry gas-phase deposition, plasma
Body chemical vapor phase growing technique, sub-atmospheric pressure chemical vapor deposition method or low-pressure chemical vapor deposition process.In the present embodiment,
The initial isolation structure film is formed using fluid chemistry gas-phase deposition so that region between adjacent fin 210
Filling effect is preferable.
The technique for removing the initial isolation structure film of the top surface higher than mask layer 220 is flatening process, such as chemistry
Mechanical milling tech.
The material of the protective layer is silicon nitride, fire sand or nitrogen carbon silicon boride.
In the present embodiment, forming the method for the protective layer includes：In the fin that the initial isolation structure 230 exposes
210 side walls form side wall protective layer 240；The side wall protective layer 240 and the mask layer 220 form protective layer.
The material of the side wall protective layer 240 is silicon nitride, fire sand or nitrogen carbon silicon boride.
The side wall protective layer 240 is also located at the side wall of the mask layer 220.
Forming the method for the side wall protective layer 240 includes：On the initial isolation structure 230, fin 210 and mask
The sidewall surfaces of layer 220 and the top surface of mask layer 220 form initial sidewall protective layer (not shown)；It is etched back to described
Initial sidewall protective layer until exposing the top surface of the initial surface of isolation structure 230 and mask layer 220, protect by formation side wall
Layer 240.
The technique for forming the initial sidewall protective layer is depositing operation, such as plasma activated chemical vapour deposition technique, Asia
Sub-atmospheric CVD technique, low-pressure chemical vapor deposition process or atom layer deposition process.
In the present embodiment, the technique for forming the initial sidewall protective layer is atom layer deposition process, due to atomic layer deposition
Product technique can preferably carry out conformal deposit, hence in so that the caliper uniformity of the initial sidewall protective layer is preferable.
The technique for being etched back to the initial sidewall protective layer is anisotropic dry etch process, such as anisotropic plasma
Soma carving technology or reactive ion etching process.
In other embodiments, when the top surface of fin does not retain mask layer, the protective layer covering fin
The side wall for the fin that top surface and initial isolation structure expose.
The thickness of the protective layer needs to select suitable scope, if the thickness of the protective layer is less than 15 angstroms, causes institute
It is too small to state the thickness of protective layer, during subsequently the first ion implantation technology is carried out, it is impossible to effective to prevent to stop ion
Into in the fin 210 of protected seam covering；If the thickness of the protective layer is more than 50 angstroms, process costs are caused to increase.Therefore this
In embodiment, the thickness selection of the protective layer is 15 angstroms~50 angstroms.
With reference to figure 6, after forming the protective layer, the initial isolation structure 230 of segment thickness is removed, forms isolation structure
250, the isolation structure 250 and the protective layer expose part fin 210.
The technique for removing the initial isolation structure 230 of segment thickness is to be etched back to technique.
In the present embodiment, the initial isolation structure 230 of segment thickness is removed using anisotropic dry etch process.
The thickness for the initial isolation structure 230 being removed determines the portion that isolation structure 250 and the protective layer expose
Divide fin 210 in the size perpendicular to the surface direction of Semiconductor substrate 200.
In the present embodiment, the fin 210 that the isolation structure 250 and protective layer expose is perpendicular to Semiconductor substrate
The size of 200 surface directions is 15 angstroms~300 angstroms.The meaning of this scope is selected to be：If the isolation structure 250 and protective layer
The fin 210 exposed is less than 15 angstroms in the size perpendicular to the surface direction of Semiconductor substrate 200, the barrier layer being subsequently formed
Space is too small, causes after being subsequently formed barrier layer, stops that quantity of the ion in fin 210 is very few, it is impossible to be effectively used for
Disappear and diffuse into the anti-break-through ion in the top channel of fin 210 in subsequent anneal processing.If the isolation structure 250 and guarantor
The fin 210 that sheath exposes is more than 300 angstroms in the size perpendicular to the surface direction of Semiconductor substrate 200, causes process costs
Increase.
With reference to figure 7, barrier layer 260 is formed in the fin 210 that the isolation structure 250 and the protective layer expose,
Have in the barrier layer 260 and stop ion.
It is described to stop that ion is used to subsequently diffuse into annealing process in the raceway groove at the top of fin 210, with to
Disappear the anti-break-through ion partly or completely diffused into raceway groove.
The method bag on barrier layer 260 is formed in the fin 210 that the isolation structure 250 and the protective layer expose
Include：Injected using the first ion implantation technology in the fin 210 that the isolation structure 250 and protective layer expose stop from
Son.
The conduction type phase of the conduction type for stopping ion and the anti-break-through ion in the anti-break-through layer being subsequently formed
Instead.When the conduction type of the anti-break-through ion in the anti-break-through layer being subsequently formed is p-type, the conduction type for stopping ion
For N-type.When the conduction type of the anti-break-through ion in the anti-break-through layer being subsequently formed is N-type, the conduction for stopping ion
Type is p-type.
If the Implantation Energy of first ion implantation technology is too high, cause easily to stop that ion is noted through protective layer
Enter into the fin 210 of protective layer covering, cause the cut-in voltage of semiconductor devices to drift about；If first ion implantation technology
Implantation Energy it is too low, cause the depth that is injected into the fin 210 that isolation structure 250 and protective layer expose smaller, cause
It can not effectively stop that anti-break-through ion enters raceway groove.
If the implantation dosage of first ion implantation technology is too high, cause the concentration mistake for stopping ion in barrier layer 260
Height, have excessive stop ion in subsequent anneal processing and diffuse into the raceway groove of the top area of fin 210, to semiconductor device
The influence of the threshold voltage of part is excessive；If the implantation dosage of first ion implantation technology is too low, cause to hinder in barrier layer 260
It is too low to keep off the concentration of ion, during subsequent anneal processing, stops the anti-break-through ion that ion pair is diffused into raceway groove
Negative function reduces.
The implant angle of first ion implantation technology is relevant with Implantation Energy, and the implant angle is to be served as a contrast with semiconductor
Acute angle between the normal direction of bottom 200.In the case of certain injection depth, Implantation Energy it is bigger, it is necessary to injection
Angle is smaller.
To sum up, the Implantation Energy of first ion implantation technology, implantation dosage and implant angle need to select suitably
Scope.And atomic mass corresponding to different stop ions is different.In the case where identical injects depth, atomic mass is larger
Stop ion need the energy that is lost larger, therefore need larger Implantation Energy.
When the stop ion is phosphonium ion, the parameter of first ion implantation technology includes：Implantation dosage is
1.0E12atom/cm2~5.0E13atom/cm2, Implantation Energy is 5KeV~20KeV, and implant angle is 10 degree~30 degree.
When the stop ion is arsenic ion, the parameter of first ion implantation technology includes：Implantation dosage is
1.0E12atom/cm2~5.0E13atom/cm2, Implantation Energy is 8KeV~30KeV, and implant angle is 10 degree~30 degree.
When the stop ion is boron ion, the parameter of first ion implantation technology includes：Implantation dosage is
1.0E12atom/cm2~8.0E13atom/cm2, Implantation Energy is 1KeV~10KeV, and implant angle is 10 degree~30 degree.
When the stop ion is indium ion, the parameter of first ion implantation technology includes：Implantation dosage is
1.0E12atom/cm2~5.0E13atom/cm2, Implantation Energy is 5KeV~50KeV, and implant angle is 10 degree~30 degree.
With reference to figure 8, after forming the barrier layer, anti-break-through layer 270, the top on the barrier layer are formed in fin 210
Surface is higher than or is flush to the top surface of the anti-break-through layer 270, has anti-break-through ion, institute in the anti-break-through layer 270
State anti-break-through ion conduction type and it is described stop ion conduction type it is opposite.
In the present embodiment, the method for forming the anti-break-through layer 270 is：With the second ion implantation technology in the isolation junction
Anti- break-through ion is injected in structure 250, anti-break-through ion is diffused into fin 210, anti-break-through layer is formed in fin 210
270。
Because the width of fin 210 is smaller, therefore during the second ion implantation technology of progress, in isolation structure 250
Anti- break-through ion can diffuse into fin 210, anti-break-through layer 270 is formed in fin 210, and anti-break-through layer 270 exists
It is distributed on the width of fin 210.
It should be noted that the anti-break-through ion in the isolation structure 250 is mainly along parallel to Semiconductor substrate 200
Surface and it is diffused perpendicular to the bearing of trend of fin 210, so as to diffuse into fin 210, forms anti-break-through layer 270.
In the present embodiment, during second ion implanting is carried out, the mask layer 220 is used as mask.
The implant angle of second ion implantation technology is 0 degree.
When the semiconductor devices is N-type fin formula field effect transistor, the second ion implantation technology injection is prevented
The conduction type of break-through ion is p-type, such as boron ion or indium ion；When the semiconductor devices is p-type fin field effect crystal
Guan Shi, the conduction type of the anti-break-through ion of the second ion implantation technology injection is N-type, such as phosphonium ion or arsenic ion.
Because anti-break-through ion need not enter the bottom section of fin 210 longitudinally through fin 210, but use will
The bottom section that the anti-break-through ion in isolation structure 250 enters fin 210 by way of diffusion is injected into, the can be reduced
The energy of two ion implantation technologies, so as to reduce damage of second ion implantation technology to fin 210.
In other embodiments, anti-break-through ion can be injected into the bottom section of fin longitudinally through fin, from
And anti-break-through layer is formed in the fin.
The atom percentage concentration for stopping ion is the 5%~30% of the atom percentage concentration of anti-break-through ion.
In the present embodiment, after carrying out the second ion implantation technology, and before subsequent anneal processing is carried out, the barrier layer
260 lower surface is higher than or is flush to the top surface of the anti-break-through layer 270.So that the barrier layer 260 and anti-break-through
Layer 270 does not have overlapping region.So that the influence of anti-break-through effect of the barrier layer 260 to anti-break-through layer 270 is smaller.
It should be noted that due to being initially formed barrier layer 260, anti-break-through layer 270 is formed afterwards so that is forming anti-break-through layer
When 270, the surface of isolation structure 250 is less than the top surface on barrier layer 260.Because anti-break-through layer 270 passes through isolation structure 250
The anti-break-through ion of middle injection diffuses into fin 210 and formed, and the surface of isolation structure 250 is less than the top on barrier layer 260
Surface, anti-break-through ion in isolation structure 250 can be made to be not easy to diffuse to the top surface on barrier layer 270.Therefore second from
In the case that the injection depth of sub- injection technology is shallower, it is possible to achieve barrier layer 270 and the overlapping region of anti-break-through layer 270 compared with
Few purpose.So that the influence of anti-break-through effect of the barrier layer 260 to anti-break-through layer 270 is smaller.
With reference to figure 9, after forming the anti-break-through layer 270, made annealing treatment.
The annealing is act as：Activate the resistance in anti-break-through ion and the barrier layer 260 in anti-break-through layer 270
Keep off ion.
The parameter of the annealing includes：The gas of use includes N2, annealing temperature is 950 degrees Celsius~1100 Celsius
Degree.
It should be noted that after barrier layer is formed, and before the annealing is carried out, the protective layer is gone
Remove.Or after being made annealing treatment, the protective layer is removed.
Due to foring barrier layer 260 in fin 210, have in barrier layer 260 and stop ion, the stop ion
The conduction type of conduction type and the anti-break-through ion is on the contrary, therefore during the annealing, the barrier layer
Stop ion in 260 is also diffused into the raceway groove at the top of fin 210, and the stop ion diffused into raceway groove can be offset
The anti-break-through ion partly or completely diffused into raceway groove so that the threshold voltage of anti-break-through ion pair semiconductor devices
Influence reduce.So that the electric property of semiconductor devices improves.
Accordingly, the present embodiment also provides the semiconductor devices formed using the above method, refer to Fig. 8, including：Partly lead
Body substrate 200, there is fin 210 in the Semiconductor substrate 200；Anti- break-through layer 270, it is described anti-in the fin 210
There is anti-break-through ion in break-through layer 270；Barrier layer 260, in the fin 210, the top surface on the barrier layer 260
It is higher than or is flush to the top surface of anti-break-through layer 270, has in the barrier layer 260 and stop ion, the stop ion
The conduction type of conduction type and the anti-break-through ion is opposite.
Due to having barrier layer in fin 210, have in the barrier layer 260 and stop ion, it is described to stop leading for ion
The conduction type of electric type and the anti-break-through ion is on the contrary, therefore the stop ion can enter fin in annealing
In the raceway groove at 210 tops, to offset the anti-break-through ion partly or completely diffused into raceway groove.So that anti-break-through ion
Influence to the threshold voltage of semiconductor devices reduces.So that the electric property of semiconductor devices improves.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (20)
- A kind of 1. forming method of semiconductor devices, it is characterised in that including：Semiconductor substrate is provided, there is fin in the Semiconductor substrate；Barrier layer is formed in the fin, has in the barrier layer and stops ion；After forming the barrier layer, anti-break-through layer is formed in the fin, the top surface on the barrier layer is higher than or flushed There is anti-break-through ion, the conductive-type of the anti-break-through ion in the top surface of the anti-break-through layer, the anti-break-through layer The conduction type of type and the stop ion is opposite；After forming the anti-break-through layer, made annealing treatment.
- 2. the forming method of semiconductor devices according to claim 1, it is characterised in that the method for forming the barrier layer Including：Initial isolation structure, the side wall of the initial isolation structure covering part fin are formed on the semiconductor substrate； The fin portion surface that the initial isolation structure exposes forms protective layer；After forming the protective layer, the first of segment thickness is removed Beginning isolation structure, isolation structure is formed, the isolation structure and the protective layer expose part fin；In the isolation structure Barrier layer is formed in the fin exposed with the protective layer.
- 3. the forming method of semiconductor devices according to claim 2, it is characterised in that the top surface tool of the fin There is mask layer；Forming the method for the protective layer includes：Side wall protection is formed in the fin side wall that the initial isolation structure exposes Layer；The side wall protective layer and the mask layer form protective layer.
- 4. the forming method of semiconductor devices according to claim 3, it is characterised in that the material of the mask layer is nitrogen SiClx or fire sand；The material of the side wall protective layer is silicon nitride, fire sand or nitrogen carbon silicon boride.
- 5. the forming method of semiconductor devices according to claim 3, it is characterised in that the side wall protective layer is also located at The side wall of the mask layer；Forming the method for the side wall protective layer includes：On the initial isolation structure, the sidewall surfaces of fin and mask layer, And the top surface of mask layer forms initial sidewall protective layer；The initial sidewall protective layer is etched back to until exposing initial Isolation structure surface and the top surface of mask layer, form side wall protective layer.
- 6. the forming method of semiconductor devices according to claim 2, it is characterised in that the thickness of the protective layer is 15 Angstrom~50 angstroms.
- 7. the forming method of semiconductor devices according to claim 2, it is characterised in that the isolation structure and protective layer The fin exposed is 15 angstroms~300 angstroms in the size perpendicular to semiconductor substrate surface direction.
- 8. the forming method of semiconductor devices according to claim 2, it is characterised in that in the isolation structure and described The method on formation barrier layer is in the fin that protective layer exposes：Using the first ion implantation technology in the isolation structure and guarantor Injection stops ion in the fin that sheath exposes.
- 9. the forming method of semiconductor devices according to claim 8, it is characterised in that when leading for the anti-break-through ion When electric type is p-type, the conduction type for stopping ion is N-type.
- 10. the forming method of semiconductor devices according to claim 9, it is characterised in that it is described stop ion be phosphorus from Son；The parameter of first ion implantation technology includes：Implantation dosage is 1.0E12atom/cm2~5.0E13atom/cm2, note It is 5KeV~20KeV to enter energy, and implant angle is 10 degree~30 degree.
- 11. the forming method of semiconductor devices according to claim 9, it is characterised in that it is described stop ion be arsenic from Son；The parameter of first ion implantation technology includes：Implantation dosage is 1.0E12atom/cm2~5.0E13atom/cm2, note It is 8KeV~30KeV to enter energy, and implant angle is 10 degree~30 degree.
- 12. the forming method of semiconductor devices according to claim 8, it is characterised in that when the anti-break-through ion When conduction type is N-type, the conduction type for stopping ion is p-type.
- 13. the forming method of semiconductor devices according to claim 12, it is characterised in that it is described stop ion be boron from Son；The parameter of first ion implantation technology includes：Implantation dosage is 1.0E12atom/cm2~8.0E13atom/cm2, note It is 1KeV~10KeV to enter energy, and implant angle is 10 degree~30 degree.
- 14. the forming method of semiconductor devices according to claim 12, it is characterised in that it is described stop ion be indium from Son；The parameter of first ion implantation technology includes：Implantation dosage is 1.0E12atom/cm2~5.0E13atom/cm2, note It is 5KeV~50KeV to enter energy, and implant angle is 10 degree~30 degree.
- 15. the forming method of semiconductor devices according to claim 2, it is characterised in that form the anti-break-through layer Method includes：Anti- break-through ion is injected in the isolation structure using the second ion implantation technology, spreads anti-break-through ion Into in fin, anti-break-through layer is formed in the fin.
- 16. the forming method of semiconductor devices according to claim 15, it is characterised in that the anti-break-through ion diffusion Be oriented parallel to semiconductor substrate surface and perpendicular to fin bearing of trend.
- 17. the forming method of semiconductor devices according to claim 15, it is characterised in that the second ion implanting work The implant angle of skill is 0 degree.
- 18. the forming method of semiconductor devices according to claim 1, it is characterised in that the atom for stopping ion Percent concentration is the 5%~30% of the atom percentage concentration of anti-break-through ion.
- 19. the forming method of semiconductor devices according to claim 1, it is characterised in that the parameter of the annealing Including：The gas of use includes N2, annealing temperature is 950 degrees Celsius~1100 degrees Celsius.
- A kind of 20. semiconductor devices formed according to claim 1 to 19 any one method, it is characterised in that including：Semiconductor substrate, there is fin in the Semiconductor substrate；Anti- break-through layer, in the fin, there is anti-break-through ion in the anti-break-through layer；Barrier layer, in the fin, the top surface on the barrier layer is higher than or is flush to the top of the anti-break-through layer Surface, have in the barrier layer and stop ion, the conductive-type of the conduction type and the anti-break-through ion for stopping ion Type is opposite.
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| CN112151594A (en) * | 2019-06-28 | 2020-12-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113394104A (en) * | 2021-05-31 | 2021-09-14 | 上海华力集成电路制造有限公司 | Fin morphology design method in FinFET structure |
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| CN112151594A (en) * | 2019-06-28 | 2020-12-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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