CN110875371B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN110875371B CN110875371B CN201811000485.9A CN201811000485A CN110875371B CN 110875371 B CN110875371 B CN 110875371B CN 201811000485 A CN201811000485 A CN 201811000485A CN 110875371 B CN110875371 B CN 110875371B
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- 238000000034 method Methods 0.000 title claims abstract description 77
- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 150000002500 ions Chemical class 0.000 claims abstract description 167
- 238000002955 isolation Methods 0.000 claims abstract description 85
- 230000000903 blocking effect Effects 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 239000002131 composite material Substances 0.000 claims abstract description 24
- -1 carbon ions Chemical class 0.000 claims description 50
- 239000000463 material Substances 0.000 claims description 31
- 238000005468 ion implantation Methods 0.000 claims description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 20
- 238000009792 diffusion process Methods 0.000 claims description 18
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 15
- 150000004767 nitrides Chemical class 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 14
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- 229910001449 indium ion Inorganic materials 0.000 claims description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims description 8
- 239000011574 phosphorus Substances 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 7
- 229910052799 carbon Inorganic materials 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims 2
- 230000003071 parasitic effect Effects 0.000 description 13
- 230000000694 effects Effects 0.000 description 6
- 230000001105 regulatory effect Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Chemical group 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor device and a method of forming the same, wherein the method of forming includes: providing a substrate, wherein the substrate is provided with a fin structure, the fin structure comprises a bottom region and a top region positioned on the bottom region, the top region comprises a plurality of composite fin layers overlapped along the normal direction of the surface of the substrate, and each composite fin layer comprises a second fin layer and a first fin layer positioned on the surface of the second fin layer; forming a first isolation structure on the substrate, wherein the first isolation structure covers the bottom region side wall of the fin structure and at least part of the bottommost second fin side wall; forming a blocking doped region in the second fin part layer at the bottommost layer, wherein blocking ions are doped in the blocking doped region; and forming a threshold ion doping region at the top of the bottom region of the fin structure, wherein threshold voltage adjusting ions are doped in the threshold ion doping region. The semiconductor device formed by the method has better performance.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor device and a method of forming the same.
Background
With the rapid development of integrated circuit manufacturing technology, the semiconductor devices in the integrated circuits are continually reduced in size, so that the operation speed of the whole integrated circuit can be effectively improved. However, as the device size is further reduced, the control capability of the conventional planar MOS transistor to the channel current becomes weak, and the short channel effect (short channel effect, abbreviated SCE) becomes serious. Fin field effect transistors (Fin FETs) are an emerging multi-gate device with a gate having good channel control and are widely used in small-scale applications.
Semiconductor devices having a gate-all-around (GAA) structure are being sought after in the semiconductor industry for their device performance and special performance that can effectively control short channel effects.
However, the fully-enclosed gate device formed by the prior art has parasitic channels, is easy to generate leakage current, has poorer performance and needs to be further improved.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which aims to improve the performance of the semiconductor device.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the substrate is provided with a fin structure, the fin structure comprises a bottom region and a top region positioned on the bottom region, the top region comprises a plurality of composite fin layers overlapped along the normal direction of the surface of the substrate, and each composite fin layer comprises a second fin layer and a first fin layer positioned on the surface of the second fin layer; forming a first isolation structure on the substrate, wherein the first isolation structure covers the side wall of the bottom area of the fin structure and the side wall of a part of the bottommost second fin layer; forming a blocking doped region in the second fin part layer at the bottommost layer, wherein blocking ions are doped in the blocking doped region; and forming a threshold ion doping region at the top of the bottom region of the fin structure, wherein threshold voltage adjusting ions are doped in the threshold ion doping region.
Optionally, the method for forming the blocking doped region includes: performing first ion implantation on the first isolation structure, and implanting blocking ions in the first isolation structure; after the first ion implantation, performing first diffusion to drive blocking ions in the first isolation structure to diffuse into the second fin part layer, and forming a blocking doping region in the second fin part layer at the bottommost layer; the blocking ions include: carbon ions, germanium ions or nitrogen ions. .
Optionally, after forming the blocking doped region and before forming the threshold ion doped region, the method further includes: and etching the first isolation structure back to form a second isolation structure, wherein the top surface of the second isolation structure is lower than or flush with the top surface of the bottom region of the fin structure.
Optionally, the forming method of the threshold ion doped region includes: performing second ion implantation on the second isolation structure, and implanting threshold voltage adjusting ions into the second isolation structure; and after the second ion implantation, performing second diffusion, driving threshold voltage adjusting ions in the second isolation structure to diffuse into the second fin portion layer, and forming a threshold ion doping region at the top of the bottom region of the fin portion structure.
Optionally, a distance from the top surface of the second isolation structure to the top surface of the bottom region of the fin structure is: 35 nm-100 nm.
Optionally, the forming method of the first isolation structure includes: forming an initial isolation structure on a substrate, wherein the initial isolation structure covers the side wall of the fin structure; and etching the initial isolation structure until the side wall of the second fin part layer of the bottommost layer is exposed, and forming the first isolation structure.
Optionally, after forming the blocking doped region and the threshold ion doped region, the method further includes: performing second annealing treatment; the technological parameters of the second annealing treatment comprise: the temperature is 950-1050 ℃ and the time is 0.1-10 seconds.
Optionally, a preset distance is provided from the surface of the first isolation structure to the top surface of the second fin portion layer of the bottommost layer, and the preset distance is 1/4-2/3 of the thickness of the second fin portion layer of the bottommost layer.
Optionally, the method further comprises: after forming the blocking doped region and the threshold ion doped region, forming a device structure on the fin structure; when the device structure is P-type, the threshold voltage adjusting ions comprise N-type ions, and the N-type ions comprise phosphorus ions or arsenic ions; when the device structure is N-type, the threshold voltage adjusting ion comprises P-type ion, and the P-type ion comprises boron ion and BF 2- Ions or indium ions.
Optionally, a fin protection layer is arranged on the top of the fin structure; the fin protection layer comprises the following materials: silicon germanium, silicon nitride, silicon oxynitride, silicon carbide nitride, silicon oxycarbide nitride, silicon oxyboride nitride, or silicon oxyboride nitride.
Optionally, the material of the first fin portion layer is different from the material of the second fin portion layer; the material of the first fin portion layer is monocrystalline silicon or monocrystalline germanium silicon; the second fin portion layer is made of monocrystalline silicon or monocrystalline germanium silicon.
Optionally, after forming the blocking ion doped region and the threshold ion doped region, the method further includes: forming a pseudo gate structure and source-drain doped regions on a substrate, wherein the pseudo gate structure spans across the fin structure and covers part of the top surface and part of the side wall surface of the fin structure, the pseudo gate structure comprises a pseudo gate electrode layer, and the source-drain doped regions are located in the fin structures at two sides of the pseudo gate structure; after the source-drain doped region is formed, a dielectric layer is formed on the substrate and the fin part structure, the dielectric layer covers the side wall of the pseudo gate structure and exposes the top surface of the pseudo gate structure; removing the second fin part layer covered by the pseudo gate structure and the pseudo gate structure after forming the dielectric layer, and forming a gate opening in the dielectric layer, wherein the gate opening is also positioned between two adjacent first fin part layers; after the gate opening is formed, a gate structure is formed in the gate opening, and the gate structure surrounds the first fin layers of each layer.
Correspondingly, the invention also provides a semiconductor device, which comprises: the substrate is provided with a fin structure, the fin structure comprises a bottom area and a top area positioned on the bottom area, the top area comprises a plurality of composite fin layers overlapped along the normal direction of the surface of the substrate, and each composite fin layer comprises a second fin layer and a first fin layer positioned on the surface of the second fin layer; the first isolation structure is positioned on the substrate and covers the bottom region side wall of the fin structure and at least part of the bottommost second fin side wall; the blocking doped region is positioned at the bottom of the composite fin part layer of the top region and is internally doped with blocking ions; and a threshold ion doping region positioned at the top of the bottom region of the fin structure, wherein threshold voltage regulating ions are doped in the threshold ion doping region.
Optionally, the blocking ions include: carbon ions, germanium ions or nitrogen ions.
Optionally, the method further comprises: a device structure located on the fin structure; when the device structure is P-type, the threshold voltage adjusting ion includes N-type ion, such as: phosphorus ions or arsenic ions; when the device structure is N-type, the threshold voltage adjusting ionsIncluding P-type ions such as: boron ions, BF 2- Ions or indium ions.
Optionally, a fin protection layer is arranged on the top of the fin structure; the fin protection layer comprises the following materials: silicon germanium, silicon nitride, silicon oxynitride, silicon carbide nitride, silicon oxycarbide nitride, silicon oxyboride nitride, or silicon oxyboride nitride.
Optionally, the material of the first fin portion layer is different from the material of the second fin portion layer; the material of the first fin portion layer is monocrystalline silicon or monocrystalline germanium silicon; the second fin portion layer is made of monocrystalline silicon or monocrystalline germanium silicon.
Optionally, the method further comprises: the grid electrode structure is positioned on the fin part structure and is also positioned between the first fin part layers at two adjacent sides; source and drain doped regions in the fin structures on both sides of the gate structure; and the dielectric layer is positioned on the substrate and the fin part structure, covers the side wall of the gate structure, the side wall and the top surface of the source-drain doped region, and exposes the top surface of the gate structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor device, the gate structure formed later fully surrounds the first fin portion layer of each layer, and the parasitic device is easily formed between the gate structure and the bottom area of the fin portion structure. The threshold ion doped region is located at the top of the bottom region of the fin structure, and is doped with threshold voltage adjusting ions for increasing the threshold voltage of the channel region of the parasitic device, so that the parasitic device is difficult to turn on, the electric leakage of the semiconductor device to be formed is reduced, and the performance of the formed semiconductor device is improved. Meanwhile, the blocking doped region is doped with blocking ions, and the blocking doped region can effectively block threshold voltage adjusting ions in the threshold ion doped region from diffusing to the top region of the fin structure, so that the influence of the ion concentration of the first fin layer can be avoided, the first fin layer is subsequently used for forming an effective device channel region, the influence of carrier mobility in the channel region is avoided, and the performance of the formed semiconductor device is improved. In summary, the method can reduce the leakage of the parasitic channel of the semiconductor device and simultaneously can avoid the influence of the carrier mobility of the channel region of the semiconductor device, thereby improving the performance of the formed semiconductor device.
Further, the fin protection layer is located at the top of the fin structure, and can protect the first fin layer at the top of the top area of the fin structure in the ion implantation process, so that the influence of ion implantation on the first fin layer at the top of the top area of the fin structure is reduced, and the performance of the semiconductor device is improved.
In the semiconductor device provided by the technical scheme of the invention, the blocking doped region of the second fin portion layer is positioned at the bottom of the composite fin portion layer of the top region, and blocking ions are doped in the blocking doped region; and a threshold ion doping region positioned at the top of the bottom region of the fin structure, wherein threshold voltage regulating ions are doped in the threshold ion doping region. In the semiconductor device, the threshold ion doped region can effectively reduce the electric leakage of a parasitic channel of the semiconductor device to be formed, and meanwhile, the blocking doped region can effectively avoid the influence on the carrier mobility of the channel region of the semiconductor device, so that the semiconductor device has better performance.
Drawings
Fig. 1-6 are schematic structural diagrams of a fully-enclosed gate device formation process;
fig. 7 to 18 are schematic structural views of a semiconductor device forming process in an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the prior art semiconductor device with the fully surrounding gate structure is poor.
Fig. 1 to 6 are schematic structural views of a fully-enclosed gate device.
Referring to fig. 1, a semiconductor substrate 100 is provided, the semiconductor substrate 100 is provided with a fin structure 110 and an isolation structure 101, the fin structure 110 includes a bottom region and a top region located on the bottom region, the top region includes a plurality of composite fin layers overlapping along a surface normal direction of the semiconductor substrate 100, the composite fin layer includes a second fin layer 112 and a first fin layer 111 located on a surface of the second fin layer 112, the fin structure 110 is provided with a protection layer 102, and the isolation structure 101 covers a sidewall surface of the fin structure 110;
referring to fig. 2, a dummy gate structure 120 and a source-drain doped region 130 are formed on the isolation structure 101, where the dummy gate structure 120 spans across the fin structure 110 and covers a portion of the top surface and a portion of the sidewall surface of the fin structure 110, and the dummy gate structure 120 includes a dummy gate dielectric layer (not shown) and a dummy gate electrode layer (not shown); the source-drain doped regions 130 are located in the fin structures 110 at two sides of the dummy gate structure 120.
Referring to fig. 3, after the dummy gate structure 120 and the source-drain doped region 130 are formed, a dielectric layer 140 is formed on the isolation structure 101, and a top surface of the dielectric layer 140 is higher than a top surface of the fin structure 110.
Referring to fig. 4, after the dielectric layer 140 is formed, the dummy gate electrode layer is removed, and a first gate opening 121 is formed in the dielectric layer 140, where a portion of the surface of the isolation structure 101, and a portion of the top surface and a portion of the sidewall surface of the fin structure 110 are exposed by the first gate opening 121;
referring to fig. 5, after the first gate opening 121 is formed, ion implantation is performed on the isolation structure at the bottom of the first gate opening 121; after the ion implantation, an annealing treatment is performed to form a threshold ion doped region 150 on top of the fin structure 110 in the bottom region.
Referring to fig. 6, the second fin layer 112 exposed by the first gate opening 121 is removed to form a second gate opening; a gate structure 160 is formed within the second gate opening, and the gate structure 160 surrounds each layer of the first fin layer 111.
The gate structure 160 surrounds the first fin layer 111, and the gate structure 160, which replaces part of the structure of the second fin layer 112, and the bottom region of the fin structure 110 form parasitic devices. The threshold ion doped region 150 located at the top of the bottom region of the fin structure 110 can increase the threshold voltage of the parasitic device, make the parasitic device difficult to turn on, reduce the leakage of the semiconductor device to be formed, and thus improve the performance of the semiconductor device.
However, the fully-surrounding gate devices formed by the above method still have poor performance. The reason is that: ions doped in the threshold ion doped region 150 in the top portion of the bottom region of the fin structure 110 are diffused under the thermal drive of the annealing process, and as the diffusion is disordered, the ions in the threshold ion doped region are diffused in all directions, so that part of the ions are diffused upwards into the first fin layer 111 of the top region composite fin layer. Since the type of the threshold voltage adjusting ions is opposite to the type of the semiconductor device to be formed, the doped threshold voltage adjusting ions diffuse into the first fin layer 111 of the top-region composite fin layer, which can reduce the carrier mobility in the first fin layer 111 of the top-region composite fin layer, the first fin layer of the top-region composite fin layer will subsequently form an effective channel of the semiconductor device, so that the performance of the formed fully-enclosed gate device is poor.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 7 to 18 are schematic structural views of a semiconductor device forming process in an embodiment of the present invention.
Referring to fig. 7, a substrate 200 is provided, and the substrate 200 has a fin structure 210 thereon, where the fin structure 210 includes a bottom region and a top region on the bottom region, the top region includes a plurality of composite fin layers overlapping along a normal direction of a substrate surface, and each composite fin layer includes a second fin layer 212 and a first fin layer 211 on a surface of the second fin layer.
The substrate 200 may be monocrystalline silicon, polycrystalline silicon, or amorphous silicon; the substrate 200 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, etc.; in this embodiment, the substrate 200 is made of monocrystalline silicon.
The method of forming the fin structure 210 includes: forming a fin material film (not shown) on the substrate 200, where the fin material film includes a plurality of first fin films (not shown) and second fin films (not shown) that are stacked in a staggered manner in a direction normal to a surface of the substrate 200, and the second fin films are located between adjacent first fin films; the fin material film is patterned to form fin structures 210, with the first fin film forming first fin layer 211 and the second fin film forming second fin layer 212.
The first fin layer 211 and the second fin layer 212 are of different materials. Specifically, the material of the first fin layer 211 is monocrystalline silicon or monocrystalline germanium silicon; the material of the second fin layer 212 is monocrystalline silicon or monocrystalline silicon germanium.
The fin structure 210 has a fin protection layer 201 on top.
The fin protection layer 201 protects the first fin layer on top of the fin structure 210 during the subsequent ion implantation, reduces the influence of the ion implantation on the first fin layer 211 on top of the fin structure 210, and improves the performance of the semiconductor device.
The fin protection layer 201 comprises the following materials: silicon germanium, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxynitride or silicon oxycarbide.
Referring to fig. 8, a first isolation structure 202 is formed on the substrate, where the first isolation structure 202 covers a bottom region sidewall of the fin structure 210 and a portion of a bottommost second fin layer sidewall.
The material of the first isolation structure 202 includes silicon oxide.
The method for forming the first isolation structure 202 includes: forming an initial isolation structure (not shown) on the substrate, the initial isolation structure covering sidewalls of the fin structure 210; and etching the initial isolation structure until the side wall of the second fin layer 212 of the part of the bottommost layer is exposed, thereby forming the first isolation structure 202.
The process of forming the initial isolation structure is a deposition process, such as a fluid chemical vapor deposition process. The initial isolation structure is formed by adopting a fluid chemical vapor deposition process, so that the filling performance of the initial isolation structure is better.
The surface of the first isolation structure 202 has a preset distance from the surface of the first isolation structure to the top surface of the second fin layer 212 at the bottom layer, and the preset distance is 1/4-2/3 of the thickness of the second fin layer 212 at the bottom layer.
Subsequently, performing a first ion implantation on the first isolation structure 202, wherein the implanted ions are blocking ions, and the ions are blocked from entering the first isolation structure 202; in a subsequent diffusion process, the blocking ions are caused to diffuse into the underlying second fin layer 212 covered by the first isolation structure. The movement of the blocking ions is disordered in the diffusion process, and the blocking ions are diffused into the fin structure along the direction vertical to the extending direction of the fin and parallel to the surface of the semiconductor substrate, and are also diffused into the fin structure along the direction vertical to the surface of the semiconductor substrate and parallel to the height direction of the fin.
The meaning of selecting the preset distance is that: if the preset distance is too small, the top surface of the first isolation structure 202 is too close to the top surface of the second fin layer 212 at the bottommost layer, and then the top surface of the subsequently formed blocking doped region is too close to the top surface of the second fin layer 212 at the bottommost layer, so that the doped part of blocking ions in the blocking doped region are easy to diffuse into the first fin layer 211, thereby affecting the ion concentration of the effective device channel, and the performance of the formed semiconductor device is poor; if the preset distance is too large, the bottom of the first isolation structure 202 is too close to the bottom of the second fin layer 212 at the bottommost layer, then the bottom of the subsequently formed blocking doped region is too close to the top of the bottom region of the fin structure, and is easy to be connected with a threshold ion doped region subsequently formed in the bottom region of the fin structure 210, so that the effect that the blocking doped region blocks the threshold voltage to adjust the upward diffusion of ions is affected, the carrier mobility of the effective device channel is affected, and the performance of the formed semiconductor device is poor.
In this embodiment, after the first isolation structure 202 is formed, a blocking doped region is formed in the second fin portion layer at the bottom layer, and blocking ions are doped in the blocking doped region. The formation of the blocking doped region will be described later with reference to fig. 9 and 10.
Referring to fig. 9, a first ion implantation is performed on the first isolation structure 202, and blocking ions are implanted into the first isolation structure 202.
The blocking ions include: carbon ions, germanium ions or nitrogen ions.
In this embodiment, the parameters of the first ion implantation include: the implanted ions are carbon ions with a dosage range of 1.0E14atom/cm 2 ～5.0E16atom/cm 2 The energy range is 1 KeV-30 KeV, and the inclination angle is 0 degree; the tilt angle is the angle between the implantation direction and the normal to the plane of the substrate 200.
The blocking ions and crystal atoms form chemical bonds, so that lattice gaps are reduced, and threshold voltage regulating ions in a threshold ion doping region formed later are not easy to pass, so that the effect of blocking threshold voltage regulating ion diffusion is achieved.
The fin protection layer 201 protects the first fin layer 211 on top of the fin structure 210, reduces the influence of the first ion implantation on the first fin layer 211 on top of the fin structure 210, and improves the performance of the semiconductor device. Referring to fig. 10, after the first ion implantation, a first diffusion is performed to drive the blocking ions in the first isolation structure 202 to diffuse into the second fin layer 212, and a blocking doped region 220 is formed in the second fin layer 212 at the bottom layer.
In this embodiment, the first diffusion includes: a first annealing treatment is performed. The parameters of the first annealing treatment include: the annealing temperature is 850-1050 ℃ and the time is 0.1-20 seconds.
In other embodiments, the blocking doping region may be formed by reserving a certain diffusion time and a thermal process of a subsequent process to allow a portion of the blocking ions to diffuse laterally into the second fin layer. Because the implanted blocking ions carry energy and the ion implantation dosage is high, the unordered diffusion of the implanted blocking ions occurs in the isolation structure due to the existence of ion concentration differences. The width of the fin structure 210 is 5 nm to 15 nm, and the width of the fin structure 210 is very small and is within the free diffusion range of ions, so that the implanted partial blocking ions can laterally diffuse into the second fin layer to form a blocking doped region. The width is the dimension of fin structure 210 in the X-X1 direction (shown in fig. 10) parallel to the surface of substrate 200.
Referring to fig. 11, the first isolation structure 202 is etched back to form a second isolation structure 203, and a top surface of the second isolation structure 203 is lower than or flush with a top surface of the bottom region of the fin structure 210.
The method of etching back the first isolation structure 202 includes one or a combination of a dry etching process and a wet etching process.
Subsequently, performing a second ion implantation on the second isolation structure 203, wherein the implanted ions are threshold voltage adjusting ions, and the threshold voltage adjusting ions enter the second isolation structure 203; in a subsequent diffusion process, the threshold voltage adjusting ions are diffused into the bottom region of the fin structure 210 covered by the second isolation structure 203, and during the diffusion process, the movement of the threshold voltage adjusting ions is disordered, and the threshold voltage adjusting ions are diffused into the fin structure in a direction perpendicular to the extending direction of the fin and parallel to the surface of the semiconductor substrate, and are also diffused into the fin structure in a direction perpendicular to the surface of the semiconductor substrate and parallel to the height direction of the fin.
The distance from the top surface of the second isolation structure 203 to the surface of the bottom region of the fin structure 210 is 35 nm to 100 nm.
The significance of selecting the distance is: if the distance is less than 35 nanometers, threshold voltage adjusting ions enter the second fin portion layer, the second fin portion layer is removed later, and the concentration of the threshold voltage adjusting ions in a subsequent channel is insufficient; if the distance is greater than 100 nm, the threshold voltage adjusting ions cannot reach the top of the bottom region of the fin structure 210, doping of the channel region cannot be achieved, the threshold voltage adjusting effect on the parasitic device is weakened, leakage of the semiconductor device to be formed is enhanced, and the performance of the semiconductor device is reduced.
In this embodiment, after the second isolation structure 203 is formed, a threshold ion doped region 230 is formed on top of the bottom region of the fin structure 210, and threshold voltage adjusting ions are doped in the threshold ion doped region 230. The process of forming the threshold ion doped region 230 is described later with reference to fig. 12 and 13.
Referring to fig. 12, a second ion implantation is performed on the second isolation structure 203, and threshold voltage adjusting ions are implanted into the second isolation structure 203.
After forming the blocking doped region and the threshold ion doped region, forming a fin structureForming a device structure thereon; when the device structure is P-type, the threshold adjusting ions comprise N-type ions, and the N-type ions comprise phosphorus ions or arsenic ions; when the device structure is N-type, the threshold adjusting ion comprises P-type ion, and the P-type ion comprises boron ion and BF 2- Ions or indium ions.
In this embodiment, the device structure is P-type, and the parameters of the second ion implantation include: the threshold voltage regulating ion is phosphorus ion or arsenic ion, the energy range is 1 KeV-10 KeV, and the dosage range is 1.0E13atom/cm 2 ～1.0E16atom/cm 2 The inclination angle is 0 degree; the tilt angle is the angle between the implantation direction and the normal to the plane of the substrate 200.
In other embodiments, the device structure is N-type, and the parameters of the second ion implantation include: the threshold voltage regulating ion is boron ion or indium ion, the energy range is 0.5 KeV-8 KeV, and the dosage range is 1.0E13atom/cm 2 ～1.0E16atom/cm 2 The inclination angle is 0 degree; the tilt angle is the angle between the implantation direction and the normal to the plane of the substrate 200.
The fin protection layer 202 protects the first fin layer 211 on top of the fin structure 210, reduces the influence of the second ion implantation on the first fin layer 211 on top of the fin structure 210, and improves the performance of the semiconductor device.
After the second ion implantation, a second diffusion is performed to drive the threshold voltage adjusting ions in the second isolation structure 203 to diffuse into the fin structure 210 of the bottom region, and a threshold ion doped region 230 is formed on top of the fin structure 210 of the bottom region.
In this embodiment, the second annealing process may drive the threshold voltage adjusting ions in the second isolation structure 203 to diffuse into the fin structure 210 in the bottom region, thereby reducing the process and the time.
Referring to fig. 13, a second annealing process is performed after the second ion implantation.
The technological parameters of the second annealing treatment comprise: the temperature is 950-1050 ℃ and the time is 0.1-10 seconds.
The second anneal process is used to activate the implanted ions, on the one hand, threshold voltage adjusting ions within the threshold ion doped region 230 can be activated; on the other hand, blocking ions within the blocking doped region 220 can be activated. The threshold ion doped region 230 is located at the top of the bottom region of the fin structure 210, and the threshold ion doped region 230 after the threshold voltage adjusting ions are activated is used to increase the threshold voltage of the channel region of the parasitic device, so that the parasitic device is difficult to turn on, and the leakage of the semiconductor device to be formed is reduced, thereby improving the performance of the formed semiconductor device. Meanwhile, the blocking doped region 220 is doped with blocking ions, and the blocking doped region 220 after the blocking ions are activated can effectively block the threshold voltage adjusting ions from diffusing to the top region of the fin structure 210, so that the influence of the ion concentration of the first fin layer 211 can be avoided, and the first fin layer 211 is subsequently used for forming an effective device channel region, so that the influence of the carrier mobility in the channel region is avoided, and the performance of the formed semiconductor device is improved. In conclusion, the semiconductor device formed by the method has better performance.
In this embodiment, the second annealing process also serves to drive the diffusion of threshold voltage adjusting ions implanted in the second isolation structure 203 into the bottom region top region of the fin structure, thereby facilitating the formation of the threshold ion doped region 230.
In this embodiment, after the second annealing treatment, the method further includes: the fin protection layer 201 on top of the fin structure 210 is removed.
The process of removing the fin protection layer 201 includes one or a combination of a dry etching process and a wet etching process.
Referring to fig. 14 and 15, fig. 15 is a schematic cross-sectional view along a cutting line M-M1 in fig. 14, and after forming the blocking doped region 220 and the threshold ion doped region 230, the method further includes: a dummy gate structure 240 and a source-drain doped region 250 are formed on the substrate, the dummy gate structure 240 spans across the fin structure 210 and covers a portion of the top surface and a portion of the sidewall surface of the fin structure 210, the dummy gate structure 240 includes a dummy gate electrode layer (not shown), and the source-drain doped layer 250 is located in the fin structure 210 on both sides of the dummy gate structure 240.
The method for forming the dummy gate structure 240 includes: forming a dummy gate dielectric film (not shown) covering the fin structure 210 on the substrate 200, and forming a dummy gate electrode film (not shown) on the surface of the dummy gate dielectric film; forming a patterning layer (not shown) on the dummy gate electrode film, the patterning layer defining the position and size of the dummy gate structure; and etching the dummy gate dielectric film and the dummy gate electrode film by taking the patterned layer as a mask until the top surface of the fin structure 210 is exposed, and forming a dummy gate structure 240 on the fin structure 210.
The dummy gate structure 240 includes a dummy gate dielectric layer (not shown) crossing the fin structure 210 and a dummy gate electrode layer (not shown) on the dummy gate dielectric layer. The dummy gate structure further includes a dummy gate protection layer (not shown) on the surface of the dummy gate electrode layer, where the dummy gate protection layer protects the dummy gate electrode layer when the source/drain doped region 250 is formed, and also serves as a stop layer when the initial dielectric layer is subsequently planarized.
In this embodiment, the two sides of the dummy gate structure 240 have a first sidewall (not shown) and a second sidewall (not shown) located on the first sidewall.
The first side wall and the second side wall define the distance between the gate structure and the source-drain doped region which are formed later.
The method for forming the source-drain doped region 250 includes: grooves (not shown) are formed in the fin structures 210 at two sides of the dummy gate structure 240, the first sidewall and the second sidewall; after forming the recess, source drain doped regions 250 are formed in the recess.
The source-drain doped regions 250 are formed using an epitaxial growth process.
The source-drain doped region 250 has source-drain ions.
The process of forming the source-drain doped region 250 includes an epitaxial growth process; the process of doping source and drain ions in the source and drain doped region is an in-situ doping process.
When the semiconductor device is a P-type deviceThe source-drain doped layer 250 includes: silicon, germanium or silicon germanium, wherein the source and drain ions are P-type ions, and comprise boron ions and BF 2- Ions or indium ions; when the semiconductor device is an N-type device, the materials of the source-drain doped layer 250 include: silicon, gallium arsenide or indium gallium arsenide, wherein the source and drain ions are N-type ions, and the source and drain ions comprise phosphorus ions or arsenic ions.
In other embodiments, the source-drain doped regions are formed using an ion implantation process.
Referring to fig. 16, after forming the source-drain doped regions 250, the method further includes: a dielectric layer 260 is formed on the substrate and fin structure 210, the dielectric layer 260 covering sidewalls of the dummy gate structure 240 and exposing a top surface of the dummy gate structure 240.
The method for forming the dielectric layer 260 includes: forming an initial dielectric layer (not shown in the figure) on the source-drain doped region 250, the dummy gate structure 240, the first sidewall and the second sidewall, wherein the initial dielectric layer covers the top surface and the sidewall surface of the dummy gate structure 240; the initial dielectric layer is planarized until the top surface of the dummy gate protection layer on top of the dummy gate structure 240 is exposed, forming a dielectric layer 260.
The top surface of the dielectric layer 260 is flush with the surface of the dummy gate structure 240, and the top surface of the dielectric layer 260 is higher than the top surface of the fin protection layer 201.
The material of the dielectric layer 260 includes silicon oxide.
Referring to fig. 17, after forming the dielectric layer 260, the method further includes: the dummy gate structure 240 and the second fin layer 212 covered by the dummy gate structure 240 are removed, and a gate opening 261 is formed in the dielectric layer 260, where the gate opening 261 is further located between two adjacent first fin layers 211.
The method of removing the dummy gate structure 240 and the second fin layer 212 covered by the dummy gate structure 240 includes: removing the dummy gate structure 240 and forming an initial gate opening (not shown) in the dielectric layer 260; after the initial gate opening is formed, the second fin portion layer 212 exposed by the initial gate opening is removed, so as to form a gate opening 261.
Referring to fig. 18, after forming the gate opening 261, the method further includes: a gate structure 270 is formed within the gate opening 261, and the gate structure 270 surrounds the layers of the first fin layer 211.
In this embodiment, the gate structure 270 includes a gate structure body (not shown) and a gate protection layer (not shown) on a top surface of the gate structure body. In other embodiments, the gate structure includes only a gate structure body.
The gate structure 270 is further located between adjacent first fin layers 211, and in particular, the gate structure body is further located between adjacent first fin layers 211. This surrounds the gate structure body around the first fin layer 211, increasing the control capability of the gate structure over the channel.
Accordingly, the present embodiment further provides a semiconductor device formed by the above method, please continue to refer to fig. 13, including:
a substrate, on which a fin structure 210 is provided, where the fin structure 210 includes a bottom region and a top region located on the bottom region, the top region includes a plurality of composite fin layers overlapping along a normal direction of a substrate surface, and each composite fin layer includes a second fin layer 212 and a first fin layer 211 located on the surface of the second fin layer;
a first isolation structure 202 (shown in fig. 10) on the substrate, where the first isolation structure 202 covers a bottom region sidewall of the fin structure 210 and a portion of a bottom-most second fin layer 212 sidewall;
a blocking doped region 220 of the second fin layer 212 at the bottom of the top region composite fin layer, the blocking doped region 220 being doped with blocking ions;
a threshold ion doped region 230 located atop the bottom region of fin structure 210, the threshold ion doped region 230 being doped with threshold voltage adjusting ions.
The blocking ions include: carbon ions, germanium ions or nitrogen ions.
The semiconductor device further includes: a device structure located on fin structure 210; when the device structure is P-type, the threshold voltage adjusting ion includes N-type ion, such as: phosphorus ions or arsenic ions; when the device structure is N-type, theThreshold voltage adjusting ions include P-type ions such as: boron ions, BF 2- Ions or indium ions.
The fin structure 210 has a fin protection layer on top; the fin protection layer comprises the following materials: silicon germanium, silicon nitride, silicon oxynitride, silicon carbide nitride, silicon oxycarbide nitride, silicon oxyboride nitride, or silicon oxyboride nitride.
The material of the first fin portion layer is different from the material of the second fin portion layer; the material of the first fin portion layer is monocrystalline silicon or monocrystalline germanium silicon; the second fin portion layer is made of monocrystalline silicon or monocrystalline germanium silicon.
In the semiconductor device, the threshold ion doped region can effectively reduce the electric leakage of a parasitic channel of the semiconductor device to be formed, and meanwhile, the blocking doped region can effectively avoid the influence on the carrier mobility of the channel region of the semiconductor device, so that the semiconductor device has better performance.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (16)
1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate is provided with a fin structure, the fin structure comprises a bottom region and a top region positioned on the bottom region, the top region comprises a plurality of composite fin layers overlapped along the normal direction of the surface of the substrate, and each composite fin layer comprises a second fin layer and a first fin layer positioned on the surface of the second fin layer;
forming a first isolation structure on the substrate, wherein the first isolation structure covers the side wall of the bottom area of the fin structure and the side wall of a part of the bottommost second fin layer;
forming a blocking doped region in the second fin part layer at the bottommost layer, wherein blocking ions are doped in the blocking doped region;
forming a threshold ion doping region at the top of the bottom region of the fin structure, wherein threshold voltage adjusting ions are doped in the threshold ion doping region;
the blocking ions include: carbon ions, germanium ions or nitrogen ions.
2. The method of forming a semiconductor device of claim 1, wherein the method of forming a barrier doped region comprises: performing first ion implantation on the first isolation structure, and implanting blocking ions in the first isolation structure; and after the first ion implantation, performing first diffusion to drive blocking ions in the first isolation structure to diffuse into the second fin part layer, and forming a blocking doped region in the second fin part layer at the bottommost layer.
3. The method of forming a semiconductor device of claim 1, wherein after forming the blocking doped region and before forming the threshold ion doped region, further comprising: and etching the first isolation structure back to form a second isolation structure, wherein the top surface of the second isolation structure is lower than or flush with the top surface of the bottom region of the fin structure.
4. The method of forming a semiconductor device of claim 3, wherein the method of forming a threshold ion doped region comprises: performing second ion implantation on the second isolation structure, and implanting threshold voltage adjusting ions into the second isolation structure; and after the second ion implantation, performing second diffusion, driving threshold voltage adjusting ions in the second isolation structure to diffuse into the second fin portion layer, and forming a threshold ion doping region at the top of the bottom region of the fin portion structure.
5. The method of forming a semiconductor device of claim 3, wherein a distance from a top surface of the second isolation structure to a top surface of a bottom region of the fin structure is: 35 nm-100 nm.
6. The method of forming a semiconductor device of claim 1, wherein the method of forming a first isolation structure comprises: forming an initial isolation structure on a substrate, wherein the initial isolation structure covers the side wall of the fin structure; and etching the initial isolation structure until the side wall of the second fin part layer of the bottommost layer is exposed, and forming the first isolation structure.
7. The method of forming a semiconductor device of claim 1, further comprising, after forming the barrier doped region and the threshold ion doped region: performing second annealing treatment; the technological parameters of the second annealing treatment comprise: the temperature is 950-1050 ℃ and the time is 0.1-10 seconds.
8. The method of claim 1, wherein a surface of the first isolation structure has a predetermined distance from a top surface of the second fin layer of the bottommost layer, the predetermined distance being 1/4 to 2/3 of a thickness of the second fin layer of the bottommost layer.
9. The method of forming a semiconductor device according to claim 1, further comprising: after forming the blocking doped region and the threshold ion doped region, forming a device structure on the fin structure; when the device structure is P-type, the threshold voltage adjusting ions comprise N-type ions, and the N-type ions comprise phosphorus ions or arsenic ions; when the device structure is N-type, the threshold voltage adjusting ion comprises P-type ion, and the P-type ion comprises boron ion and BF 2- Ions or indium ions.
10. The method of forming a semiconductor device of claim 1, wherein a fin protection layer is provided on top of the fin structure; the fin protection layer comprises the following materials: silicon germanium, silicon nitride, silicon oxynitride, silicon carbide nitride, silicon oxycarbide nitride, silicon oxyboride nitride, or silicon oxyboride nitride.
11. The method of claim 1, wherein a material of the first fin layer and a material of the second fin layer are different; the material of the first fin portion layer is monocrystalline silicon or monocrystalline germanium silicon; the second fin portion layer is made of monocrystalline silicon or monocrystalline germanium silicon.
12. The method of forming a semiconductor device of claim 1, further comprising, after forming the blocking ion doped region and the threshold ion doped region: forming a pseudo gate structure and source-drain doped regions on a substrate, wherein the pseudo gate structure spans across the fin structure and covers part of the top surface and part of the side wall surface of the fin structure, the pseudo gate structure comprises a pseudo gate electrode layer, and the source-drain doped regions are located in the fin structures at two sides of the pseudo gate structure; after the source-drain doped region is formed, a dielectric layer is formed on the substrate and the fin part structure, the dielectric layer covers the side wall of the pseudo gate structure and exposes the top surface of the pseudo gate structure; removing the second fin part layer covered by the pseudo gate structure and the pseudo gate structure after forming the dielectric layer, and forming a gate opening in the dielectric layer, wherein the gate opening is also positioned between two adjacent first fin part layers; after the gate opening is formed, a gate structure is formed in the gate opening, and the gate structure surrounds the first fin layers of each layer.
13. A semiconductor device, comprising:
the substrate is provided with a fin structure, the fin structure comprises a bottom area and a top area positioned on the bottom area, the top area comprises a plurality of composite fin layers overlapped along the normal direction of the surface of the substrate, and each composite fin layer comprises a second fin layer and a first fin layer positioned on the surface of the second fin layer;
the first isolation structure is positioned on the substrate and covers the bottom region side wall of the fin structure and at least part of the bottommost second fin side wall;
the blocking doped region is positioned at the bottom of the composite fin part layer of the top region and is internally doped with blocking ions;
the threshold ion doping region is positioned at the top of the bottom region of the fin structure, and threshold voltage adjusting ions are doped in the threshold ion doping region; the blocking ions include: carbon ions, germanium ions or nitrogen ions.
14. The semiconductor device according to claim 13, further comprising: a device structure located on the fin structure; when the device structure is P-type, the threshold voltage adjusting ion includes N-type ion, such as: phosphorus ions or arsenic ions; when the device structure is N-type, the threshold voltage adjusting ion includes P-type ion, such as: boron ions, BF 2- Ions or indium ions.
15. The method of forming a semiconductor device of claim 13, wherein a fin protection layer is provided on top of the fin structure; the fin protection layer comprises the following materials: silicon germanium, silicon nitride, silicon oxynitride, silicon carbide nitride, silicon oxycarbide nitride, silicon oxyboride nitride, or silicon oxyboride nitride.
16. The semiconductor device of claim 13, wherein a material of the first fin layer and a material of the second fin layer are different; the material of the first fin portion layer is monocrystalline silicon or monocrystalline germanium silicon; the second fin portion layer is made of monocrystalline silicon or monocrystalline germanium silicon.
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| CN106601686A (en) * | 2015-10-16 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof, and electronic device |
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