CN113539828A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN113539828A CN113539828A CN202010312363.4A CN202010312363A CN113539828A CN 113539828 A CN113539828 A CN 113539828A CN 202010312363 A CN202010312363 A CN 202010312363A CN 113539828 A CN113539828 A CN 113539828A
- Authority
- CN
- China
- Prior art keywords
- ions
- layer
- fin
- forming
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 127
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000009792 diffusion process Methods 0.000 claims abstract description 17
- 150000002500 ions Chemical class 0.000 claims description 161
- 230000008569 process Effects 0.000 claims description 79
- 239000000463 material Substances 0.000 claims description 57
- 238000011049 filling Methods 0.000 claims description 48
- -1 gallium ions Chemical class 0.000 claims description 48
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 19
- 238000005468 ion implantation Methods 0.000 claims description 17
- 229910052799 carbon Inorganic materials 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- 229910001449 indium ion Inorganic materials 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims 2
- 230000009286 beneficial effect Effects 0.000 abstract description 14
- 239000010410 layer Substances 0.000 description 233
- 238000002955 isolation Methods 0.000 description 16
- 238000002513 implantation Methods 0.000 description 15
- 238000005530 etching Methods 0.000 description 10
- 125000006850 spacer group Chemical group 0.000 description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000004528 spin coating Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 239000003575 carbonaceous material Substances 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- 229910052582 BN Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a base, wherein the base comprises a substrate and a fin part protruding out of the substrate; forming a grid electrode structure crossing the fin part on the substrate, wherein the grid electrode structure covers part of the top and part of the side wall of the fin part; forming grooves in the fin parts on two sides of the grid electrode structure, wherein the bottom of each groove is lower than the bottom of the grid electrode structure, and the part, lower than the grid electrode structure, of each groove is used as a bottom groove; performing ion doping on the fin part below the grid structure through the bottom groove to form a diffusion-preventing doped region; and forming a source-drain doping layer in the groove after the anti-diffusion doping region is formed. The embodiment of the invention is beneficial to reducing the leakage current formed by the source-drain doped layer in the fin part below the grid structure, and further beneficial to improving the performance of the semiconductor structure.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the gradual development of semiconductor process technology, the development trend of semiconductor process nodes following moore's law is continuously reduced. In order to adapt to the reduction of process nodes, the channel length of the MOSFET field effect transistor is correspondingly and continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage Pinch-off (pincoff) channel is increased, and the sub-threshold leakage (SCE) phenomenon, namely the so-called Short-channel effect (SCE), is easier to occur.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar MOSFETs to three-dimensional devices with higher performance, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a forming method thereof, which can reduce leakage current formed by a source-drain doped layer in a fin part below a grid structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a fin part protruding out of the substrate; forming a grid electrode structure crossing the fin part on the substrate, wherein the grid electrode structure covers part of the top and part of the side wall of the fin part; forming grooves in the fin parts on two sides of the grid electrode structure, wherein the bottom of each groove is lower than the bottom of the grid electrode structure, and the part, lower than the grid electrode structure, of each groove is used as a bottom groove; performing ion doping on the fin part below the grid structure through the bottom groove to form a diffusion-preventing doped region; and forming a source-drain doping layer in the groove after the anti-diffusion doping region is formed.
Optionally, after the forming the groove, before performing ion doping on the fin portion located below the gate structure through the bottom groove, the method for forming the semiconductor structure further includes: forming a liner layer on the side wall of the groove, wherein the liner layer exposes the side wall of the bottom groove; performing ion doping on the fin portion located below the gate structure through the bottom groove by taking the liner layer as a mask; after the diffusion-preventing doped region is formed and before the source-drain doped layer is formed, the method for forming the semiconductor structure further comprises the following steps: the liner layer is removed.
Optionally, after forming the groove and before forming the pad layer, the method for forming the semiconductor structure further includes: forming a sacrificial layer in the bottom groove; the step of forming the pad layer includes: forming a layer of liner material conformally covering the top surface of the sacrificial layer, the sidewalls of the recess, and the sidewalls and top of the gate structure; and removing the liner material layer on the top surface of the sacrificial layer and the top of the gate structure, wherein the residual liner material layer on the side wall of the groove is used as the liner layer.
Optionally, after the forming the liner layer, before performing ion doping on the fin portion located below the gate structure through the bottom groove, the method for forming the semiconductor structure further includes: removing part of the sacrificial layer with partial thickness to form a filling layer, wherein the filling layer exposes part of the side wall of the bottom groove; the step of ion doping the fin portion below the gate structure through the bottom groove includes: performing ion doping on the fin parts exposed out of the filling layer and the liner layer; after the diffusion-preventing doped region is formed, the method for forming the semiconductor structure further comprises the following steps: and removing the filling layer.
Optionally, in the step of forming the filling layer, the height of the fin portion exposed by the filling layer and the liner layer is 30nm to 50 nm.
Optionally, the material of the filling layer includes spin-on carbon, an organic dielectric layer material, or spin-on silicon oxide.
Optionally, the process of removing the pad layer includes one or both of a wet etching process and a dry etching process.
Optionally, the material of the liner layer includes silicon nitride, silicon oxycarbide, silicon oxycarbonitride, or silicon oxide.
Optionally, in the step of performing ion doping on the fin portion located below the gate structure, the doped ions are inversion ions, and the doping type of the inversion ions is different from the doping type of the transistor; or, in the step of ion doping the fin portion located below the gate structure, the doped ions are impurity ions.
Optionally, the doped ions are counter ions; when an NMOS transistor is formed, the inversion ions are P-type ions and comprise gallium ions, boron ions or indium ions; when a PMOS transistor is formed, the inversion ions are N-type ions, and the inversion ions include phosphorus ions or arsenic ions.
Optionally, the doping ions are impurity ions, and the impurity ions include carbon ions, oxygen ions, or nitrogen ions.
Optionally, the step of performing ion doping on the fin portion located below the gate structure through the bottom groove includes: and carrying out ion doping on the fin part exposed out of the side wall of the bottom groove by adopting an ion implantation process.
Optionally, the number of the gate structures is multiple, and the multiple gate structures cross over the same fin portion.
Optionally, the depth of the bottom groove is 35nm to 60 nm.
Optionally, the step of forming the diffusion-preventing doped region further includes: and carrying out annealing treatment after carrying out ion doping on the fin part below the grid structure through the bottom groove.
Optionally, the bottom groove is a bowl-shaped groove.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: the substrate comprises a substrate and a fin part protruding out of the substrate; the grid structure is positioned on the substrate, stretches across the fin part and covers part of the top and part of the side wall of the fin part; the source-drain doping layer is positioned in the fin parts on two sides of the grid structure, and the bottom of the source-drain doping layer is lower than the bottom of the grid structure; and the anti-diffusion doped region is positioned in the fin part below the grid structure and is adjacent to the source-drain doped layer.
Optionally, the diffusion-preventing doped region is doped with inversion ions, and the doping type of the inversion ions is different from that of the transistor; or, impurity ions are doped in the diffusion-preventing doped region.
Optionally, the anti-diffusion doping region is doped with counter ions; when an NMOS transistor is formed, the inversion ions are P-type ions and comprise gallium ions, boron ions or indium ions; when a PMOS transistor is formed, the inversion ions are N-type ions, the inversion ions include phosphorus ions or arsenic ions, and the impurity ions include carbon ions, oxygen ions, or nitrogen ions.
Optionally, the impurity ions include carbon ions, oxygen ions, or nitrogen ions.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the embodiment of the invention, the fin part positioned below the grid structure is subjected to ion doping through the bottom groove to form the anti-diffusion doping area; by forming the diffusion-preventing doped region, the probability of ions in the source-drain doped layer diffusing into the fin part below the grid structure is favorably reduced, so that the leakage current formed by the source-drain doped layer in the fin part below the grid structure is favorably reduced, and the performance of the semiconductor structure is favorably improved; moreover, the fin part below the grid structure is subjected to ion doping to form the diffusion-preventing doped region, and the doping area of the diffusion-preventing doped region is smaller, so that the influence on the performance of the semiconductor structure is favorably reduced, for example: the problem of large parasitic capacitance of the transistor is prevented, and the process compatibility is improved.
Drawings
Fig. 1 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The currently formed fin field effect transistor (FinFET) still has a poor performance.
Specifically, in the FinFET, a gate structure crosses over a fin and covers part of the top and part of the sidewall of the fin, and source-drain doped layers are located in the fin on both sides of the gate structure. Leakage current is easily generated between adjacent source and drain doped layers through a part of fin parts which are not covered by the gate structure, that is, leakage current is also generated in the fin parts positioned at the bottom of the channel region, which easily causes poor performance of the formed semiconductor structure.
Some methods to improve the above problems are proposed, for example: and forming an inversion doping region in the bottom of the fin part in a solid source diffusion mode to improve a potential barrier and further reduce leakage current. However, the formation of the inversion-type doped region by solid-state source diffusion generally includes a step of forming a solid-state doped layer, and the solid-state doped layer is located between the source-drain doped region and the fin portion, which tends to increase the parasitic capacitance between the source-drain doped region and the fin portion.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate and a fin part protruding out of the substrate; forming a grid electrode structure crossing the fin part on the substrate, wherein the grid electrode structure covers part of the top and part of the side wall of the fin part; forming grooves in the fin parts on two sides of the grid electrode structure, wherein the bottom of each groove is lower than the bottom of the grid electrode structure, and the part, lower than the grid electrode structure, of each groove is used as a bottom groove; performing ion doping on the fin part below the grid structure through the bottom groove to form a diffusion-preventing doped region; and forming a source-drain doping layer in the groove after the anti-diffusion doping region is formed.
In the method for forming the semiconductor structure provided by the embodiment of the invention, the fin part positioned below the grid structure is subjected to ion doping through the bottom groove to form the anti-diffusion doping area; by forming the diffusion-preventing doped region, the probability of ions in the source-drain doped layer diffusing into the fin part below the grid structure is favorably reduced, so that the leakage current formed by the source-drain doped layer in the fin part below the grid structure is favorably reduced, and the performance of the semiconductor structure is favorably improved; moreover, the fin part below the grid structure is subjected to ion doping to form the diffusion-preventing doped region, and the doping area of the diffusion-preventing doped region is smaller, so that the influence on the performance of the semiconductor structure is favorably reduced, for example: the problem of large parasitic capacitance of the transistor is prevented, and the process compatibility is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 1 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1 and 2, fig. 2 is a cross-sectional view taken along a-a1 in fig. 1, and provides a base including a substrate 100 and a fin 110 protruding from the substrate 100.
The substrate is used for providing a process platform for forming a semiconductor structure.
In this embodiment, the substrate is used to provide a process platform for forming a fin field effect transistor, and the substrate is a three-dimensional substrate.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.
The fin 110 is used to subsequently provide a conduction channel for a finfet.
In this embodiment, the fin 110 and the substrate 100 are obtained by etching the same semiconductor layer. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
Therefore, in this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.
In this embodiment, an isolation layer 111 is further formed on the substrate 100 where the fin portion 110 is exposed, and a top surface of the isolation layer 111 is lower than a top surface of the fin portion 110.
The isolation layer 111 is used to electrically isolate adjacent devices.
In this embodiment, the isolation layer 111 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be an insulating material such as silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.
Referring to fig. 3 and 4, fig. 4 is a cross-sectional view taken along a-a1 in fig. 3, a gate structure 120 is formed on the substrate 100 and crosses the fin 110, and the gate structure 120 covers a portion of the top and a portion of the sidewall of the fin 110.
As an example, in the present embodiment, the gate structure 120 is a dummy gate structure, and the gate structure 120 is used to occupy a space for a metal gate structure to be formed subsequently. In other embodiments, the gate structure may also be a device gate structure, and is used to control the on or off of a conductive channel when the device operates.
In this embodiment, the gate structure 120 includes a dummy gate layer, and the material of the dummy gate layer includes polysilicon. In other embodiments, the gate structure may also be a stacked structure, and the gate structure includes a gate oxide layer and a dummy gate layer on the gate oxide layer.
In other embodiments, when the gate structure is a device gate structure, the gate structure is used to control the conduction channel to be turned on and off.
In this embodiment, the number of the gate structures 120 is plural, and a plurality of the gate structures 120 cross over the same fin 110.
In this embodiment, the gate structure 120 is formed on the isolation layer 111, and the gate 120 crosses over the fin 110 exposed by the isolation layer 111 and covers a portion of the sidewall of the fin 110 exposed by the isolation layer 111.
In this embodiment, after forming the gate structure 120, the method for forming the semiconductor structure further includes: and forming a side wall 130 on the side wall of the gate structure 120.
The sidewall spacers 130 are used for protecting the sidewalls of the gate structures 120, and the sidewall spacers 130 are further used for defining the formation positions of subsequent source-drain doping layers.
The material of the sidewall 130 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride, and the sidewall 130 may have a single-layer structure or a stacked-layer structure.
In this embodiment, the sidewall spacer 130 has a single-layer structure, and the material of the sidewall spacer 130 is silicon nitride.
Referring to fig. 5, a groove 200 is formed in the fin 110 on both sides of the gate structure 120, the bottom of the groove 200 is lower than the bottom of the gate structure 120, and a portion of the groove 200 lower than the gate structure 120 is used as a bottom groove 10.
The groove 200 is used for providing a spatial position for the subsequent formation of a source-drain doping layer. Specifically, the groove 200 is located in the fin 110 exposed by the gate structure 120 and the sidewall 130.
The portion of the recess 200 lower than the gate structure 120 serves as a bottom recess 10, and the bottom recess 10 exposes the fin 110 lower than the gate structure 120, so as to prepare for ion doping of the fin 110 below the gate structure 120 through the bottom recess 10. In this embodiment, the bottom groove 10 is a bowl-shaped groove.
The recess 200 further comprises a top recess 20 located above the bottom recess 10 and communicating with the bottom recess 10. The top recess 20 is also located in the fin 110, respectively.
After the groove 200 is formed, the bottom and the sidewall of the groove 200 and the adjacent gate structure 120 enclose a trench (not labeled), and the aspect ratio of the trench should not be too small or too large. If the depth-to-width ratio of the trench is too small, the height of the gate structure 120 is correspondingly low, or the portion of the bottom groove 10 lower than the gate structure 120 is too small; if the aspect ratio of the trench is too large, the difficulty of ion doping the fin 110 below the gate structure 120 through the bottom recess 10 is increased, for example: when the fin portion 110 below the gate structure 120 is subsequently ion-doped by an ion implantation process, the implanted ions are easily blocked by the adjacent gate structure 120, which makes it difficult to implant ions into the fin portion 110 below the gate structure 120, or the implanted ions into the fin portion 110 below the gate structure 120 are too few.
In this embodiment, a dry etching process is adopted, for example: and etching the fin part 110 exposed out of the gate structure 120 by using an anisotropic dry etching process, and forming the groove 200 in the fin part 110 exposed out of the gate structure 120. The anisotropic dry etching process has the characteristic of anisotropic etching, and is favorable for reducing the characteristic of transverse etching on the gate structure 120 or the fin part 110 covered by the gate structure 120, so that the length of a channel is favorable for meeting the process requirement, the process stability is correspondingly favorable for improving, and the profile controllability of the dry etching process is better.
The subsequent steps further comprise: the fin 110 under the gate structure 120 is ion-doped through the bottom recess 10 to form a diffusion-preventing doped region.
Referring to fig. 7 to 8, in the present embodiment, after forming the recess 200, before performing ion doping on the fin 110 located below the gate structure 120 through the bottom recess 10, the method for forming a semiconductor structure further includes: a liner layer 150 is formed on the sidewalls of the top recess 20 (as shown in fig. 8), and the liner layer 150 exposes the sidewalls of the bottom recess 10.
The liner layer 150 exposes the sidewalls of the bottom recess 10, so that the fin 110 under the gate structure 120 can be subsequently ion-doped through the bottom recess 10; moreover, the liner layer 150 may protect sidewalls of the gate structure 120 and sidewalls of the fin 110 exposed by the top recess 20 during a subsequent ion doping process of the fin 110 under the gate structure 120.
Specifically, in this embodiment, the liner layer 150 is formed on the sidewalls of the top groove 20 and the sidewalls of the sidewalls 130 higher than the bottom groove 10.
In this embodiment, the pad layer 150 is made of silicon nitride. In other embodiments, the material of the liner layer may also be silicon oxycarbide, silicon oxycarbonitride, or silicon oxide.
In this embodiment, according to the actual process of performing ion doping on the fin 110 below the gate structure 120 through the bottom recess 10, for example: when the ion implantation process is used for ion doping, the thickness of the liner layer 150 needs to be adjusted according to the implantation angle of the ion implantation process, so as to prevent implanted ions of the subsequent ion implantation process from being shielded by the liner layer 150.
In this embodiment, referring to fig. 6 in combination, after forming the groove 200 and before forming the liner layer 150, the method for forming the semiconductor structure further includes: a sacrificial layer 140 is formed in the bottom groove 10.
By forming the sacrificial layer 140 in the bottom groove 10, it is beneficial to prevent a subsequent liner layer 150 from being formed in the bottom groove 10, and the sacrificial layer 140 can also provide a flat surface for forming the liner layer 150, which is beneficial to reduce the difficulty of forming the liner layer 150.
The sacrificial layer 140 is subsequently removed, and therefore, in order to reduce the difficulty of subsequently removing the sacrificial layer 140, the sacrificial layer 140 is a material that can be easily removed. In this embodiment, the sacrificial layer 140 is Spin-On-Carbon (SOC). The filling performance of the spin-coating carbon material is good, the spin-coating carbon material can be formed in a spin-coating mode, the filling capacity of the sacrificial layer 140 in the bottom groove 10 is improved beneficially by selecting the spin-coating carbon material, the forming difficulty of the sacrificial layer 140 is reduced beneficially, and the spin-coating carbon material is easy to remove.
In other embodiments, the sacrificial layer may also be made of other materials with good filling performance and easy to remove, and in addition, the material of the sacrificial layer needs to have a selection ratio with the materials of the liner layer and the sidewall, for example: the sacrificial Layer may also be an Organic Dielectric Layer (ODL), Spin on silicon oxide (Spin on glass), or the like.
In this embodiment, the step of forming the sacrificial layer 140 includes: forming a sacrificial material layer (not shown) filling the recess 200 and filling between the gate structures 120; the sacrificial material layer higher than the bottom groove 10 is removed, and the remaining sacrificial material layer in the bottom groove 10 is used as the sacrificial layer 140.
In this embodiment, the sacrificial material layer is formed by a spin coating process.
In this embodiment, a dry etching process is used to remove the sacrificial material layer higher than the bottom groove 10.
Therefore, in this embodiment, the step of forming the pad layer 150 includes: forming a layer of liner material 145 conformally covering the top surface of the sacrificial layer 140, the sidewalls of the recess 200 exposed by the sacrificial layer 140, and the sidewalls and top of the gate structure 120, as shown in fig. 7; as shown in fig. 8, the liner material layer 145 on the top surface of the sacrificial layer 140 and on the top of the gate structure 120 is removed, and the remaining liner material layer 145 on the sidewall of the recess 200 is used as the liner layer 150.
In this embodiment, the liner material layer 145 is formed by an atomic layer deposition process. The atomic layer deposition process is a self-limiting reaction process based on the atomic layer deposition process, the deposited film can reach the thickness of a single layer of atoms, the atomic layer deposition process is selected, accurate control is facilitated, the thickness of the pad material layer 145 is good, the step coverage capacity of the atomic layer deposition process is good, improvement is facilitated, the pad material layer 145 is in the conformal coverage capacity on the top surface of the sacrificial layer 140, the side wall of the groove 200 and the side wall and the top of the gate structure 120, and in addition, improvement of the thickness uniformity of the pad material layer 145 is facilitated by selecting the atomic layer deposition process.
In this embodiment, an anisotropic dry etching process is used to remove the liner material layer 145 on the top surface of the sacrificial layer 140 and the top of the gate structure 120. The anisotropic dry etching process has anisotropic etching characteristics, can remove the liner material layer 145 on the top surface of the sacrificial layer 140 and on the top of the gate structure 120 in a mask-free environment, and is beneficial to reducing the lateral etching of the liner material layer 145 on the sidewall of the groove 200.
Referring to fig. 9, in this embodiment, after forming the liner layer 150, before performing ion doping on the fin 110 located below the gate structure 120 through the bottom recess 10, the method for forming a semiconductor structure further includes: removing part of the thickness of the sacrificial layer 140 to form a filling layer 160, wherein the filling layer 160 exposes part of the sidewall of the bottom groove 10.
The filling layer 160 exposes a portion of the sidewall of the bottom recess 10, that is, the filling layer 160 and the liner layer 150 expose a portion of the fin 110, so that the fin 110 exposed by the filling layer 160 and the liner layer 150 can be subsequently ion-doped.
In the step of forming the filling layer 160, the heights of the fins 110 exposed by the filling layer 160 and the liner layer 150 are not preferably too small or too large. If the heights of the fins 110 exposed by the filling layer 160 and the liner layer 150 are too small, that is, the areas of the fins 110 exposed by the filling layer 160 and the liner layer 150 are too small, which tends to increase the difficulty of ion doping the fins 110 located below the gate structure through the bottom recess 10; if the height of the fin 110 exposed by the filling layer 160 and the liner layer 150 is too large, the fin 110 subsequently exposed in the ion doping process environment is too large, which is easy to increase the process risk and reduce the process stability, and when the ion implantation process is adopted for ion doping, the too large exposed fin 110 is easy to cause the too large area of the fin 110 implanted with ions, which is easy to cause the large implantation damage area on the surface of the fin 110, which is easy to affect the quality of the source-drain doping layer subsequently formed in the groove 200. For this reason, in the present embodiment, the height of the fin 110 exposed by the filling layer 160 and the liner layer 150 is 30nm to 50 nm.
In this embodiment, an anisotropic dry etching process is adopted to remove a part of the thickness of the sacrificial layer 140. The anisotropic dry etching process has anisotropic etching characteristics, and is beneficial to accurately controlling the etching thickness of the sacrificial layer 140, so that the height of the fin 110 exposed by the filling layer 160 and the liner layer 150 is accurately controlled.
Referring to fig. 10, the fin 110 under the gate structure 120 is ion-doped through the bottom recess 10 to form a diffusion-preventing doped region (not shown).
The subsequent steps further comprise: in the embodiment of the present invention, the bottom groove 10 is used to perform ion doping on the fin portion 110 located below the gate structure 120 to form a diffusion-preventing doped region, which is beneficial to reducing the probability that ions in the source/drain doped layer diffuse into the fin portion 110 below the gate structure 120, thereby being beneficial to reducing the leakage current formed by the source/drain doped layer in the fin portion 110 below the gate structure 120, and further being beneficial to improving the performance of the semiconductor structure; furthermore, the fin portion 110 under the gate structure 120 is ion-doped to form a diffusion-preventing doped region, which has a smaller doping area and is beneficial to reducing the influence on the performance of the semiconductor structure, such as: the problem of increasing the parasitic capacitance of the transistor is prevented, and the process compatibility is improved.
In this embodiment, the fin 110 below the gate structure 120 refers to the fin 110 lower than the bottom of the gate structure 120, the fin 110 covered by the gate structure 120 is used to form a channel region, the fin 110 lower than the bottom of the gate structure 120 is not covered by the gate structure 120, so that the risk of generating leakage current is high, and the diffusion-preventing doped region is formed in the fin 110 lower than the bottom of the gate structure 120, so as to be beneficial to significantly reducing the leakage current.
In this embodiment, in the step of ion doping the fin 110 under the gate structure 120, the doped ions are inversion ions, and the doping type of the inversion ions is different from that of the transistor.
The fin portion 110 located below the gate structure 120 is doped with the inversion ions, so that the potential barrier of a PN junction formed between the source-drain doping layer and the fin portion 110 is improved, and further, the leakage current formed by the source-drain doping layer in the fin portion 110 below the gate structure 120 is reduced.
In this embodiment, the step of performing ion doping on the fin 110 located below the gate structure 120 through the bottom groove 10 includes: and performing ion doping on the fin portion 110 exposed from the side wall of the bottom groove 10 by using an ion implantation process.
In this embodiment, the substrate is used to form an NMOS transistor, and the counter ions are P-type ions, for example: gallium ions, boron ions, or indium ions. In other embodiments, when forming a PMOS transistor, the counter ions are N-type ions, including phosphorous ions or arsenic ions.
The implantation energy of the ion implantation process is not too small or too large. If the implantation energy of the ion implantation process is too small, it is easy to make it difficult to implant ions into the fin 110 under the gate structure 120; if the implantation energy of the ion implantation process is too large, large implantation damage is easily generated to the fin 110.
The implantation dosage of the ion implantation process is not required to be too small or too large. If the implantation dosage of the ion implantation process is too small, the ion doping concentration in the diffusion-preventing doping region is easily too low, and the effect of the diffusion-preventing doping region for reducing leakage current is easily reduced; if the implantation dosage of the ion implantation process is too large, the risk that ions in the diffusion-preventing doped region diffuse into the channel region is easily increased, and further, the electrical performance of the semiconductor device is easily affected, for example: easily affecting the threshold voltage of the device, etc.
The implantation angle of the ion implantation process is not too small or too large, so that the implantation angle can be matched with the depth-to-width ratio of the trench surrounded by the gate structure 120 and the fin portion 110, and the dose of ions implanted into the fin portion 110 below the gate structure 120 meets the process requirements. Wherein the implantation angle refers to an angle between an implantation direction and a normal of the substrate 100.
It should be noted that, in the present embodiment, the fin 110 under the gate structure 120 is doped with counter ions as an example.
In other embodiments, in the step of ion doping the fin portion under the gate structure, the doping ions may also be impurity ions.
The fin part below the grid structure is doped with the impurity ions, and the impurity ions can block the movement of carriers, so that the leakage current generated by the source-drain doped layer in the fin part below the grid structure is reduced. In this embodiment, the impurity ions include carbon ions, oxygen ions, or nitrogen ions.
In this embodiment, the liner layer 150 is used as a mask to perform ion doping on the fin 110 located below the gate structure 120 through the bottom groove 10.
Specifically, in this embodiment, the step of performing ion doping on the fin 110 located below the gate structure 120 through the bottom groove 10 includes: the fin 110 exposed by the fill layer 160 and the liner layer 150 is ion doped.
In this embodiment, the filling layer 160 and the liner layer 150 expose a portion of the sidewall of the bottom groove 10, so that the sidewall of the bottom groove 10 exposed by the filling layer 160 and the liner layer 150 is ion-doped.
By performing ion doping on the sidewalls of the bottom groove 10 exposed by the filling layer 160 and the liner layer 150, the areas of the fins 110 exposed by the filling layer 160 and the liner layer 150 are smaller, and in the process of performing ion doping on the fins 110 exposed by the filling layer 160 and the liner layer 150, the structure of the fins 110 is less affected by the ion doping, for example: when an ion implantation process is used for ion doping, the fin portion 110 is less damaged by implantation, and the subsequent process for forming the source/drain doping layer in the groove 200 generally includes an epitaxial process, so that the influence on the subsequent process for forming the source/drain doping layer is reduced, and the process compatibility and the process stability are improved.
It should be noted that in the present embodiment, ion doping is performed on the fin 110 exposed by the filling layer 160 and the liner layer 150 as an example.
In other embodiments, the step of ion doping the fin under the gate structure through the bottom recess may further include: and carrying out ion doping on the filling layer positioned in the bottom groove. The surface area of the filling layer is larger, and ion doping is performed on the filling layer in the bottom groove, so that the difficulty of ion doping is reduced, for example: when the ion implantation process is adopted for ion doping, the included angle between the implantation direction and the normal line of the surface of the substrate can be properly reduced.
Accordingly, in this embodiment, after the ion doping, an annealing process may be performed to diffuse the doped ions in the filling layer into the fin portion under the gate structure.
In this embodiment, the step of forming the diffusion-preventing doped region further includes: after ion doping is performed on the fin 110 located below the gate structure 120 through the bottom groove 10, an annealing process is performed.
By performing the annealing process, the doped ions are diffused into the fin portion 110 under the gate structure 120, which is beneficial to improving the profile morphology quality of the diffusion-preventing doped region, and further improving the effect of the diffusion-preventing doped region for reducing the leakage current.
Specifically, the annealing process may include a rapid thermal annealing process, a spike annealing process, a laser annealing process, or the like.
With reference to fig. 11, in this embodiment, after the forming the diffusion-preventing doped region, the method for forming the semiconductor structure further includes: the liner layer 150 is removed.
The liner layer 150 is removed to expose the sidewalls of the top recess 20 in preparation for the subsequent formation of source drain doping layers in the recess 200.
In this embodiment, the process of removing the liner layer 150 includes a wet etching process.
Specifically, in this embodiment, the liner layer 150 is made of silicon nitride, and the etching solution of the wet etching process may be a hot phosphoric acid solution.
It should be further noted that, with reference to fig. 11, in this embodiment, after the forming of the diffusion-preventing doped region, the forming method of the semiconductor structure further includes: the filling layer 160 is removed.
And removing the filling layer 160 to expose the surface of the bottom groove 10, so as to prepare for forming a source-drain doping layer in the groove 200 subsequently.
In this embodiment, the material of the filling layer 160 is spin-on carbon, and therefore, an ashing process is used to remove the filling layer 160.
As an example, in the present embodiment, the filling layer 160 is removed before the liner layer 150 is removed. The filling layer 160 is made of an organic material, and the filling layer 160 is removed before the liner layer 150 is removed, so that the organic material is prevented from polluting a wet etching machine for removing the liner layer 150. In other embodiments, according to an actual process, the filling layer may be removed after the liner layer is removed, or the filling layer and the liner layer may be removed in the same step.
Referring to fig. 12, after the diffusion preventing doped region is formed, a source-drain doped layer 170 is formed in the groove 200.
The source-drain doped layer 170 is used to provide stress to the channel when the device is in operation, thereby being beneficial to improving the mobility of carriers.
In this embodiment, the source-drain doping layer 170 is formed by epitaxy and doping processes, and the source-drain doping layer 170 includes a stress layer. When a PMOS transistor is formed, the stress layer is made of Si or SiGe, and doped ions in the stress layer are P-type ions; when an NMOS transistor is formed, the stress layer is made of Si or SiC, and doped ions in the stress layer are N-type ions.
In this embodiment, the step of forming the source-drain doping layer 170 includes: and filling a stress material into the groove 200 by adopting a selective epitaxial process to form a stress layer, and in the process of forming the stress layer, self-doping ions of corresponding types in situ to form the source-drain doping layer 170.
As an example, in this embodiment, the gate structure 120 is a dummy gate structure, and therefore, the following steps generally further include: forming interlayer dielectric layers covering the source-drain doping layers 170 on two sides of the gate structure 120; removing the gate structure 120, and forming a gate opening in the interlayer dielectric layer; a metal gate structure is formed in the gate opening.
The following process steps are not described in detail here.
Correspondingly, the invention also provides a semiconductor structure, and the semiconductor structure is used for forming a transistor.
Specifically, the transistor may be a PMOS transistor or an NMOS transistor.
Referring to fig. 12, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a base including a substrate 100 and a fin 110 protruding from the substrate 100; a gate structure 120 located on the substrate 100, wherein the gate structure 120 crosses over the fin 110 and covers a portion of the top and a portion of the sidewall of the fin 110; the source-drain doping layer 170 is positioned in the fin portions 110 on two sides of the gate structure 120, and the bottom of the source-drain doping layer 170 is lower than the bottom of the gate structure 120; and a diffusion-preventing doped region (not shown) located in the fin 110 under the gate structure 120 and adjacent to the source-drain doped layer 170.
The semiconductor structure provided by the embodiment of the invention further comprises a diffusion-preventing doped region which is positioned in the fin part 110 below the gate structure 120 and is adjacent to the source-drain doped layer 170, and the diffusion-preventing doped region is arranged, so that the probability of ions in the source-drain doped layer 170 diffusing into the fin part 110 below the gate structure 120 is favorably reduced, the leakage current formed by the source-drain doped layer 170 in the fin part 110 below the gate structure 120 is favorably reduced, and the performance of the semiconductor structure is favorably improved.
The substrate is used for providing a process platform for forming a semiconductor structure.
In this embodiment, the substrate is used to provide a process platform for forming a fin field effect transistor, and the substrate is a three-dimensional substrate.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.
The fin 110 is used to subsequently provide a conduction channel for a finfet.
In this embodiment, the fin 110 and the substrate 100 are obtained by etching the same semiconductor layer. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
Therefore, in this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.
In this embodiment, the semiconductor structure further includes: and an isolation layer 111 located on the substrate 100 and covering a portion of the sidewall of the fin 110, wherein a top surface of the isolation layer 111 is lower than a top surface of the fin 110.
The isolation layer 111 is used to electrically isolate adjacent devices.
In this embodiment, the isolation layer 111 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be an insulating material such as silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.
In this embodiment, the gate structure 120 is formed on the isolation layer 111, and the gate 120 crosses over the fin 110 exposed by the isolation layer 111 and covers a portion of the sidewall of the fin 110 exposed by the isolation layer 111.
As an example, in the present embodiment, the gate structure 120 is a dummy gate structure, and the gate structure 120 is used to occupy a space for a metal gate structure to be formed subsequently. In other embodiments, the gate structure may also be a device gate structure, and is used to control the on or off of a conductive channel when the device operates.
In this embodiment, the gate structure 120 includes a dummy gate layer, and the material of the dummy gate layer includes polysilicon. In other embodiments, the gate structure may also be a stacked structure, and the gate structure may include a gate oxide layer and a dummy gate layer on the gate oxide layer.
In other embodiments, when the gate structure is a device gate structure, the gate structure is used to control the conduction channel to be turned on and off.
In this embodiment, the number of the gate structures 120 is plural, and a plurality of the gate structures 120 cross over the same fin 110.
In this embodiment, the semiconductor structure further includes: and a sidewall spacer 130 on a sidewall of the gate structure 120.
The sidewall spacer 130 is used to protect the sidewall of the gate structure 120, and the sidewall spacer 130 is further used to define a formation position of the source-drain doping layer 170.
The material of the sidewall 130 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride, and the sidewall 130 may have a single-layer structure or a stacked-layer structure.
In this embodiment, the sidewall spacer 130 has a single-layer structure, and the material of the sidewall spacer 130 is silicon nitride.
The source-drain doped layer 170 is used to provide stress to the channel when the device is in operation, thereby being beneficial to improving the mobility of carriers.
In this embodiment, the material of the source-drain doping layer 170 includes a stress layer doped with ions. When a PMOS transistor is formed, the stress layer is made of Si or SiGe, and doped ions in the stress layer are P-type ions; when an NMOS transistor is formed, the stress layer is made of Si or SiC, and doped ions in the stress layer are N-type ions.
The diffusion-preventing doped region is used for reducing leakage current formed by the source-drain doped layer 170 in the fin portion 110 below the gate structure 120, thereby facilitating the improvement of the performance of the semiconductor structure.
In this embodiment, the anti-diffusion doping region is located in the fin 110 below the gate structure 120, which means that the anti-diffusion doping region is located in the fin 110 lower than the bottom of the gate structure 120, the fin 110 covered by the gate structure 120 is used to form a channel region, and the fin 110 lower than the bottom of the gate structure 120 is not covered by the gate structure 120, so that a leakage current is easily formed, and the anti-diffusion doping region is disposed in the fin 110 lower than the bottom of the gate structure 120, so that the leakage current is favorably and significantly reduced.
In this embodiment, the diffusion-preventing doped region is adjacent to the source-drain doped layer 170, so that the probability that the doped ions in the source-drain doped layer 170 diffuse into the fin portion 110 lower than the gate structure 120 is reduced.
In this embodiment, the anti-diffusion doped region is doped with inversion ions, and the doping type of the inversion ions is different from the doping type of the transistor.
The fin portion 110 located below the gate structure 120 is doped with the inversion ions, so that the potential barrier of the PN junction formed between the source-drain doping layer 170 and the fin portion 110 is improved, and further, the leakage current formed by the source-drain doping layer 170 in the fin portion 110 below the gate structure 120 is reduced.
In this embodiment, the substrate is used to form an NMOS transistor, and the counter ions are P-type ions, for example: gallium ions, boron ions, or indium ions. In other embodiments, when forming a PMOS transistor, the inversion ions are N-type ions, and the inversion ions include phosphorous ions or arsenic ions.
In this embodiment, the diffusion-preventing doped region is doped with counter ions as an example.
In other embodiments, the diffusion preventing doping region may be further doped with impurity ions. The fin part below the grid structure is doped with the impurity ions, and the impurity ions can block the movement of current carriers, so that the leakage current generated by the source-drain doped layer in the fin part below the grid structure is reduced. In this embodiment, the impurity ions include carbon ions, oxygen ions, or nitrogen ions.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (20)
1. A method for forming a semiconductor structure for forming a transistor, comprising:
providing a base, wherein the base comprises a substrate and a fin part protruding out of the substrate;
forming a grid electrode structure crossing the fin part on the substrate, wherein the grid electrode structure covers part of the top and part of the side wall of the fin part;
forming grooves in the fin parts on two sides of the grid electrode structure, wherein the bottom of each groove is lower than the bottom of the grid electrode structure, and the part, lower than the grid electrode structure, of each groove is used as a bottom groove;
performing ion doping on the fin part below the grid structure through the bottom groove to form a diffusion-preventing doped region;
and forming a source-drain doping layer in the groove after the anti-diffusion doping region is formed.
2. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the recess, the recess further comprises a top recess located above the bottom recess and in communication with the bottom recess;
after the forming the groove, before ion doping is performed on the fin portion located below the gate structure through the bottom groove, the forming method of the semiconductor structure further includes: forming a liner layer on the side wall of the top groove, wherein the liner layer exposes the side wall of the bottom groove;
performing ion doping on the fin portion located below the gate structure through the bottom groove by taking the liner layer as a mask;
after the diffusion-preventing doped region is formed and before the source-drain doped layer is formed, the method for forming the semiconductor structure further comprises the following steps: the liner layer is removed.
3. The method of forming a semiconductor structure of claim 2, wherein after forming the recess and before forming the liner layer, the method of forming a semiconductor structure further comprises: forming a sacrificial layer in the bottom groove;
the step of forming the pad layer includes: forming a liner material layer conformally covering the top surface of the sacrificial layer, the side wall of the groove exposed by the sacrificial layer and the side wall and the top of the gate structure; and removing the liner material layer on the top surface of the sacrificial layer and the top of the gate structure, wherein the residual liner material layer on the side wall of the groove is used as the liner layer.
4. The method of claim 3, wherein after forming the liner layer and before ion doping the fin under the gate structure through the bottom recess, the method further comprises: removing part of the sacrificial layer with partial thickness to form a filling layer, wherein the filling layer exposes part of the side wall of the bottom groove;
the step of ion doping the fin portion below the gate structure through the bottom groove includes: performing ion doping on the fin parts exposed out of the filling layer and the liner layer;
after the diffusion-preventing doped region is formed, the method for forming the semiconductor structure further comprises the following steps: and removing the filling layer.
5. The method of claim 4, wherein a height of the fin exposed by the fill layer and the liner layer in the step of forming the fill layer is between 30nm and 50 nm.
6. The method of claim 4, wherein the material of the fill layer comprises spin-on carbon, an organic dielectric layer material, or spin-on silicon oxide.
7. The method of claim 2, wherein the process of removing the liner layer comprises one or both of a wet etching process and a dry etching process.
8. The method of claim 2, wherein the liner layer comprises a material selected from the group consisting of silicon nitride, silicon oxycarbide, silicon oxycarbonitride, and silicon oxide.
9. The method of claim 1, wherein in the step of ion doping the fin under the gate structure, the doped ions are inversion ions, and a doping type of the inversion ions is different from a doping type of the transistor;
or, in the step of ion doping the fin portion located below the gate structure, the doped ions are impurity ions.
10. The method of forming a semiconductor structure of claim 1, wherein the dopant ions are counter ions;
when an NMOS transistor is formed, the inversion ions are P-type ions and comprise gallium ions, boron ions or indium ions; when a PMOS transistor is formed, the inversion ions are N-type ions, and the inversion ions include phosphorus ions or arsenic ions.
11. The method of claim 1, wherein the dopant ions are impurity ions comprising carbon ions, oxygen ions, or nitrogen ions.
12. The method of claim 1, wherein the step of ion doping the fin under the gate structure through the bottom recess comprises: and carrying out ion doping on the fin part exposed out of the side wall of the bottom groove by adopting an ion implantation process.
13. The method of claim 1, wherein a plurality of gate structures are provided, and wherein a plurality of gate structures span the same fin.
14. The method of forming a semiconductor structure of claim 1, wherein the bottom recess has a depth of 35nm to 60 nm.
15. The method of forming a semiconductor structure of claim 1, wherein the step of forming the diffusion-preventing doped region further comprises: and carrying out annealing treatment after carrying out ion doping on the fin part below the grid structure through the bottom groove.
16. The method of claim 1, wherein the undercut is a bowl-shaped undercut.
17. A semiconductor structure for forming a transistor, comprising:
the substrate comprises a substrate and a fin part protruding out of the substrate;
the grid structure is positioned on the substrate, stretches across the fin part and covers part of the top and part of the side wall of the fin part;
the source-drain doping layer is positioned in the fin parts on two sides of the grid structure, and the bottom of the source-drain doping layer is lower than the bottom of the grid structure;
and the anti-diffusion doped region is positioned in the fin part below the grid structure and is adjacent to the source-drain doped layer.
18. The semiconductor structure of claim 17, wherein said diffusion-preventing doped region is doped with an inversion ion, said inversion ion being doped with a type different from a type of a transistor;
or, impurity ions are doped in the diffusion-preventing doped region.
19. The semiconductor structure of claim 18, wherein said diffusion-preventing doped region is doped with counter-type ions;
when an NMOS transistor is formed, the inversion ions are P-type ions and comprise gallium ions, boron ions or indium ions; when a PMOS transistor is formed, the inversion ions are N-type ions, the inversion ions include phosphorus ions or arsenic ions, and the impurity ions include carbon ions, oxygen ions, or nitrogen ions.
20. The semiconductor structure of claim 18, wherein the impurity ions comprise carbon ions, oxygen ions, or nitrogen ions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010312363.4A CN113539828A (en) | 2020-04-20 | 2020-04-20 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010312363.4A CN113539828A (en) | 2020-04-20 | 2020-04-20 | Semiconductor structure and forming method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113539828A true CN113539828A (en) | 2021-10-22 |
Family
ID=78123624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010312363.4A Pending CN113539828A (en) | 2020-04-20 | 2020-04-20 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113539828A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448986A (en) * | 2014-08-15 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | N type fin type field effect transistor and formation method thereof |
| CN105489652A (en) * | 2014-09-19 | 2016-04-13 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN106558614A (en) * | 2015-09-30 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN107591447A (en) * | 2016-07-08 | 2018-01-16 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN107785422A (en) * | 2016-08-29 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its manufacture method |
| US20180122896A1 (en) * | 2016-10-31 | 2018-05-03 | Semiconductor Manufacturing International (Shanghai) Corporation | Novel channel stop imp for the finfet device |
| CN108573869A (en) * | 2017-03-07 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect pipe and forming method thereof |
| CN108630548A (en) * | 2017-03-21 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect pipe and forming method thereof |
| CN108695253A (en) * | 2017-04-07 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110718464A (en) * | 2018-07-12 | 2020-01-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
-
2020
- 2020-04-20 CN CN202010312363.4A patent/CN113539828A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105448986A (en) * | 2014-08-15 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | N type fin type field effect transistor and formation method thereof |
| CN105489652A (en) * | 2014-09-19 | 2016-04-13 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN106558614A (en) * | 2015-09-30 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN107591447A (en) * | 2016-07-08 | 2018-01-16 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN107785422A (en) * | 2016-08-29 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its manufacture method |
| US20180122896A1 (en) * | 2016-10-31 | 2018-05-03 | Semiconductor Manufacturing International (Shanghai) Corporation | Novel channel stop imp for the finfet device |
| CN108573869A (en) * | 2017-03-07 | 2018-09-25 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect pipe and forming method thereof |
| CN108630548A (en) * | 2017-03-21 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | Fin field effect pipe and forming method thereof |
| CN108695253A (en) * | 2017-04-07 | 2018-10-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN110718464A (en) * | 2018-07-12 | 2020-01-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10396070B2 (en) | Fin-shaped field effect transistor and capacitor structures | |
| US9023715B2 (en) | Methods of forming bulk FinFET devices so as to reduce punch through leakage currents | |
| US11114551B2 (en) | Fin field-effect transistor having counter-doped regions between lightly doped regions and doped source/drain regions | |
| US8143671B2 (en) | Lateral trench FETs (field effect transistors) | |
| CN110047908B (en) | Semiconductor device and method for manufacturing the same | |
| CN107785313B (en) | Semiconductor structure and forming method thereof | |
| CN112825327A (en) | Semiconductor structure and forming method thereof | |
| CN110047754A (en) | Semiconductor devices and its manufacturing method | |
| US20140120677A1 (en) | Methods of forming enhanced mobility channel regions on 3d semiconductor devices, and devices comprising same | |
| CN114388439A (en) | Uniform implanted regions in semiconductor ridges of FinFETs | |
| CN104425520B (en) | Semiconductor devices and forming method | |
| CN110364570B (en) | Semiconductor device, forming method thereof and semiconductor structure | |
| US20080073730A1 (en) | Semiconductor device and method for formimg the same | |
| CN108122850B (en) | Semiconductor structure and forming method thereof | |
| CN112582265B (en) | Semiconductor structure and forming method thereof | |
| US6566680B1 (en) | Semiconductor-on-insulator (SOI) tunneling junction transistor | |
| CN112768407B (en) | Semiconductor structure and forming method thereof | |
| CN109087939B (en) | Forming method of semiconductor structure, LDMOS transistor and forming method thereof | |
| CN113539828A (en) | Semiconductor structure and forming method thereof | |
| CN112951765A (en) | Semiconductor structure and forming method thereof | |
| CN111863725A (en) | Semiconductor structure and forming method thereof | |
| US11742207B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20230402457A1 (en) | Transistor structure and method for fabricating the same | |
| US11374002B2 (en) | Transistors with hybrid source/drain regions | |
| US20240014319A1 (en) | Semiconductor structure and transistor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |