CN112908853B - GAA transistor, preparation method thereof and electronic equipment - Google Patents
GAA transistor, preparation method thereof and electronic equipment Download PDFInfo
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- CN112908853B CN112908853B CN202110114036.2A CN202110114036A CN112908853B CN 112908853 B CN112908853 B CN 112908853B CN 202110114036 A CN202110114036 A CN 202110114036A CN 112908853 B CN112908853 B CN 112908853B
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- 238000002360 preparation method Methods 0.000 title abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 98
- 239000000758 substrate Substances 0.000 claims abstract description 95
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
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- 238000000034 method Methods 0.000 claims description 23
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- 125000006850 spacer group Chemical group 0.000 claims description 6
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- 239000010410 layer Substances 0.000 description 167
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides a GAA transistor, a preparation method thereof and electronic equipment, wherein the preparation method comprises the following steps: providing a substrate; forming an epitaxial layer on the substrate, wherein the epitaxial layer comprises a sacrificial layer and a silicon layer which are alternately stacked, and one layer of the epitaxial layer, which is in contact with the substrate, is a bottom sacrificial layer; etching the substrate and the epitaxial layer to form a fin; etching the residual epitaxial layer in the fin to etch a source electrode area and a drain electrode area on the first side and the second side of the fin, wherein the final etching end point is lower than the highest position of the bottom sacrificial layer in the residual epitaxial layer and is not lower than the connecting position of the substrate and the bottom sacrificial layer; the first side and the second side of the fin are two opposite sides of the fin pair; and manufacturing a source electrode in the source electrode area, and manufacturing a drain electrode in the drain electrode area.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a GAA transistor, a preparation method thereof and electronic equipment.
Background
A transistor is understood to be a current switching structure made of semiconductor material. For example: between the source (semiconductor) and the drain (semiconductor), a gate (metal) may be disposed, and the gate may be used to control the on/off of the current between the source and the drain. One of the transistors is a GAA transistor. GAA is known collectively as Gate-All-Around, a wrap Around Gate technology, and GAA transistors are also known as GAAFET.
In the current mainstream GAA process, a Fin structure with a sacrificial layer may be fabricated first, and then the sacrificial layer is removed to form a suspended GAA scheme, however, in the process route, a parasitic transistor is inevitably formed on a substrate below the GAA transistor, and the generated parasitic transistor affects the gate control capability.
Disclosure of Invention
The invention provides a GAA transistor, a preparation method thereof and electronic equipment, which aim to solve the problem that the generated parasitic transistor influences the grid control capability.
According to a first aspect of the present invention, there is provided a method of manufacturing a GAA transistor, comprising:
providing a substrate;
forming an epitaxial layer on the substrate, wherein the epitaxial layer comprises a sacrificial layer and a silicon layer which are alternately stacked, and one layer of the epitaxial layer, which is in contact with the substrate, is a bottom sacrificial layer;
etching the substrate and the epitaxial layer to form a fin;
etching the residual epitaxial layer in the fin to etch a source electrode area and a drain electrode area on the first side and the second side of the fin, wherein the final etching end point is lower than the highest position of the bottom sacrificial layer in the residual epitaxial layer and is not lower than the connecting position of the substrate and the bottom sacrificial layer; the first side and the second side of the fin are two opposite sides of the fin pair;
and manufacturing a source electrode in the source electrode area, and manufacturing a drain electrode in the drain electrode area.
Optionally, etching the remaining epitaxial layer in the fin to etch a source region and a drain region on the first side and the second side of the fin includes:
etching the residual epitaxial layer in the fin for the first time;
and carrying out secondary etching on the residual epitaxial layer in the fin, detecting the change of the corresponding etching depth, and stopping etching after the final end point is etched.
Optionally, performing first etching on the remaining epitaxial layer in the fin, including: carrying out the first etching by adopting a plasma etching means;
and performing second etching on the residual epitaxial layer in the fin, wherein the second etching comprises the following steps: and performing the second etching by adopting at least one of a plasma etching means, a gas etching means and a wet etching means.
Optionally, detecting a change of a corresponding etching depth includes: and detecting the change of the etching depth by adopting an OES or IEP detection means.
Optionally, the etching end point of the first etching is higher than the highest point of the corresponding bottom sacrificial layer.
Optionally, the final end point of the second etching is matched with the joint of the substrate and the bottom sacrificial layer.
Optionally, etching the remaining epitaxial layer in the fin to etch the source region and the drain region on the two sides of the fin, further includes:
forming isolation layers on the substrate outside the third side and the fourth side of the fin; wherein the third side and the fourth side of the fin are the two opposite sides of the other pair of fins;
forming a dummy gate stack on the spacer and the fin spanning the top, third and fourth sidewalls of the fin;
forming a dielectric layer on an outer wall of the dummy gate stack, the dielectric layer being distributed over the isolation layer and the fin.
Optionally, forming a dielectric layer on an outer wall of the dummy gate stack includes:
forming a dielectric layer surrounding the outer wall of the dummy gate stack on the dummy gate stack, the isolation layer and the fin;
and grinding off the part of the dielectric layer higher than the dummy gate stack.
Optionally, the isolation layer is SiO 2 A layer.
Optionally, the sacrificial layer is a SiGe layer.
According to a second aspect of the present invention, there is provided a GAA transistor comprising: the semiconductor device comprises a fin, a source electrode arranged in a source electrode area and a drain electrode arranged in a drain electrode area, wherein the fin comprises a substrate in the fin and an epitaxial layer arranged on the substrate in the fin, the epitaxial layer comprises a sacrificial layer and a silicon layer which are alternately stacked, and the sacrificial layer which is in contact with the substrate in the fin is a bottom sacrificial layer; the source electrode and the drain electrode are arranged on the first side and the second side of the fin, the bottoms of the source electrode region and the drain electrode region are not lower than the joint of the substrate in the fin and the bottom sacrificial layer, the bottoms of the source electrode region and the drain electrode region are lower than the top of the bottom sacrificial layer, and the first side and the second side of the fin are two opposite sides of the fin.
Optionally, the GAA transistor further includes a transistor substrate, the transistor substrate includes a transistor substrate, the substrate in the fin is located on the transistor substrate, and the substrate in the fin and the transistor substrate are integrated.
Optionally, the transistor substrate further includes an isolation layer disposed on the transistor substrate and located outside the third side and the fourth side of the fin, where the third side and the fourth side of the fin are two opposite sides of another pair of fins.
Optionally, the GAA transistor further includes a dummy gate stack and a dielectric layer, the dummy gate stack crosses over the top, the third side wall, and the fourth side wall of the fin, and the dielectric layer is disposed on an outer wall of the dummy gate stack and is separated between the outer wall of the dummy gate stack and the source region, and between the outer wall of the dummy gate stack and the drain region.
Optionally, the GAA transistor is prepared by the preparation method according to the first aspect and the optional aspect thereof.
According to a third aspect of the present invention there is provided an electronic device comprising the GAA transistor of the second aspect and its alternatives.
In the GAA transistor, the preparation method thereof, and the electronic device provided by the present invention, since the bottoms of the source region and the drain region are not lower than the joint between the substrate and the bottom sacrificial layer in the fin, over-etching (etching beyond the bottom sacrificial layer) when the source region and the drain region are formed is avoided, and thus parasitic transistors generated thereby are avoided, that is: the generation of parasitic FinFET source and drain is physically avoided, so that parasitic current cannot be led out, and the gate control capability is effectively improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a parasitic transistor formed by source-drain etching in the prior art;
FIG. 2 is a first simulation graph of a conventional GAA transistor;
FIG. 3 is a schematic diagram of a simulation curve of a conventional GAA transistor;
FIG. 4 is a schematic diagram of a portion of a GAA transistor according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a GAA transistor according to an embodiment of the present invention;
FIG. 6 is a first flowchart illustrating a method of fabricating a GAA transistor according to an embodiment of the present invention;
FIG. 7 is a flowchart illustrating step S14 according to an embodiment of the present invention;
FIG. 8 is a second schematic flow chart illustrating a method for fabricating a GAA transistor according to an embodiment of the present invention;
FIG. 9 is a flowchart illustrating step S18 according to an embodiment of the present invention;
FIG. 10 is a schematic structural diagram after step S12 is implemented according to an embodiment of the present invention;
FIGS. 11a and 11b are schematic structural diagrams after step S13 is implemented according to an embodiment of the present invention;
FIG. 12 is a schematic structural diagram after step S16 is implemented according to an embodiment of the present invention;
fig. 13a and 13b are schematic structural diagrams illustrating the step S17 according to an embodiment of the present invention;
FIG. 14 is a schematic structural diagram after step S181 is performed according to an embodiment of the present invention;
FIGS. 15a and 15b are schematic structural diagrams illustrating the step S182 according to an embodiment of the present invention;
FIG. 16 is a schematic structural diagram after step S141 is performed according to an embodiment of the present invention;
fig. 17 is a schematic structural diagram after the step S142 is implemented in an embodiment of the present invention.
Description of reference numerals:
101-a fin mid-substrate;
102-a source region;
103-a drain region;
104-a bottom sacrificial layer;
105-a silicon layer;
106-a sacrificial layer;
107-a silicon layer;
108-sacrificial layer retention layer;
109-sacrificial layer retention layer;
110-dummy gate stack;
111-a dielectric layer;
112-an isolation layer;
113-a transistor substrate;
114-a substrate;
201-epitaxial layer;
202-fin middle base;
203-transistor substrate.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
In order to accurately illustrate the solution of the embodiment of the present invention, some of the defects existing in the prior art will be described in detail below with reference to fig. 1 to 3.
Referring to fig. 1, a transistor substrate 203 and a fin are illustrated, wherein the fin includes a substrate 202 and an epitaxial layer 201 thereon, and silicon in the transistor substrate 203 may be integrated with the substrate 202. During the fabrication process, by etching the epitaxial layer and the substrate, a source region and a drain region for fabricating a source and a drain may be formed on two sides (e.g., left and right sides in fig. 1) of the fin, and further, a source-drain over-etching situation as shown in fig. 1 may be formed, where a distance between the bottom of the epitaxial layer and an etching end point may be represented as an etching depth Hsd.
The structural characteristics of the parasitic transistor depend on the shape of the substrate and different gate/source-drain heights, and the parasitic transistor is manufactured into a FinFET structure in the current mainstream process route, so that the gate control capability of the parasitic transistor is enhanced, and the influence of the parasitic transistor on the performance is reduced. This means that the resulting structure from this process route becomes a parallel connection of the parasitic FinFET and the GAA MOSFET as a whole, thereby overwhelming the outstanding performance of the GAA transistor by inevitably reducing the gating capability of the overall device as compared to a pure GAA transistor.
In simulation using the conventional Transistor, as shown in fig. 2, which illustrates a relationship between an etching depth Hsd and a source line signal SSLin, as shown in fig. 3, which illustrates a relationship between an etching depth Hsd and a switching current ratio (i.e., Ion/offset), it can be seen that, based on an etching depth Hsd of a source-drain region, a Parasitic Transistor PT (which may be understood as a Parasitic Transistor) may be formed, and as the etching depth of the source-drain region is deeper (i.e., the etching depth Hsd is larger), the effect of the Parasitic Transistor is more obvious, and the larger the source line signal SSLin is, the smaller the switching source line signal SSLin is (i.e., the gating capability is weakened).
Furthermore, the embodiment of the invention creatively discovers the relation between the etching depth and the grid control capability in the preparation process of the GAA transistor, thereby forming a technical scheme capable of limiting the etching depth.
Referring to fig. 4, an embodiment of the invention provides a GAA transistor, including: the semiconductor device comprises a fin, a source arranged in a source region 102 and a drain arranged in a drain region 103, wherein the fin comprises a substrate 101 in the fin and an epitaxial layer arranged on the substrate 101 in the fin, and the epitaxial layer comprises a sacrificial layer and a silicon layer which are alternately laminated.
The sacrificial layer in contact with the base in the fin is a bottom sacrificial layer 104, and the remaining sacrificial layers may be, for example, a sacrificial layer 106 shown in fig. 4, and the silicon layers may be, for example, a silicon layer 105 and a silicon layer 107 shown in fig. 4. In other examples, the number of the silicon layers and the sacrificial layers may not be limited to those shown in fig. 4 and other figures, and the thickness thereof may also not be limited thereto.
The source (see the source region 102 in fig. 4) and the drain (see the drain region 103 in fig. 4) are disposed on the first side and the second side of the fin (i.e., along the two sides of the first direction, such as the left-right direction in fig. 4 and 5), the bottom of the source region 102 and the drain region 103 is not lower than the junction of the substrate 101 and the bottom sacrificial layer 104 in the fin, and the bottom of the source region 102 and the drain region 103 is lower than the top of the bottom sacrificial layer 104.
The source region 102 may be understood as a region etched to receive and form a source, and the drain region 103 may be understood as a region etched to receive and form a drain. The source region may include only the source, or may include other structures, and if the number of sources is plural, the sources may be provided at intervals or may not be provided at intervals, and the drain region may include only the drain, or may include other structures, and if the number of drains is plural, the drains may be provided at intervals or may not be provided at intervals.
In an example, when the bottoms of the source region 102 and the drain region 103 are higher than the connection between the base 101 and the bottom sacrificial layer 104 in the fin, as shown in fig. 4, two sides (i.e., a first side and a second side) of the bottom sacrificial layer 104 along the first direction may have a sacrificial layer retaining layer 108 and a sacrificial layer retaining layer 109, the sacrificial layer retaining layer 108 is disposed between the source region 102 and the base 101 in the fin, and the sacrificial layer retaining layer 109 is disposed between the drain region 103 and the base 101 in the fin, in another example, the bottoms of the source region 102 and the drain region 103 may also be flush with the top of the base 101 in the fin (or may be understood to be flush with the connection between the base 101 and the bottom sacrificial layer 104 in the fin).
The sacrificial layer material may be, for example, SiGe, but is not limited thereto, and any material that can facilitate the implementation of the channel layer may be used without departing from the scope of the embodiments of the present invention.
In the above solution, because the bottoms of the source region and the drain region are not lower than the joint between the substrate in the fin and the bottom layer sacrificial layer, over-etching (etching beyond the bottom layer sacrificial layer) when forming the source and drain regions is avoided, and thus a parasitic transistor is avoided, that is: the generation of parasitic FinFET source and drain is physically avoided, so that parasitic current cannot be led out, and the gate control capability is effectively improved.
In addition, the inventive contribution of the embodiments of the present invention is not only that the bottoms of the source region and the drain region are not lower than the junction of the substrate and the bottom sacrificial layer in the fin, but also that the process for realizing the structure is: the embodiment of the invention creatively discovers that: the deeper the etching depth of the source-drain region is, the more obvious the effect of the parasitic transistor is, the larger the source line signal is, the smaller the switching current ratio is (namely, the gate control capability is weakened), and the problem of the phenomenon is solved by a thought of physically avoiding the generation of the parasitic FinFET source-drain. The technical problem is not specified in any way, and a scheme for solving the technical problem is not stated in any way, so that corresponding technical suggestions are difficult to give.
In one embodiment, the GAA transistor further includes a transistor substrate, the transistor substrate includes a transistor substrate 113, the substrate 101 in the fin is located on the transistor substrate 113, the substrate 101 in the fin and the transistor substrate 113 are integrated, and the substrate 101 in the fin and the transistor substrate 113 may specifically be different structures formed by etching the substrate.
The material of the transistor base, the base in the fin, and the substrate may be silicon or other materials based on silicon, or may be other materials, for example, the substrate may be a silicon substrate, a silicon germanium substrate, or a substrate formed by other semiconductor materials, and meanwhile, the transistor base, the base in the fin, and the substrate may be doped or undoped specifically.
Further, the transistor substrate further includes an isolation layer 112, the isolation layer 112 is disposed on the transistor substrate 113 and located outside a third side and a fourth side of the fin, wherein the third side and the fourth side of the fin are opposite sides of another pair of the fins, and the fin may have four sides, wherein the first side, the third side, the second side and the fourth side are sequentially connected and enclosed.
The isolation layer 112 can be understood as any structure capable of achieving the isolation effect, and in a specific example, the material of the isolation layer 112 may beBeing an oxide, further, the material of the isolation layer 112 may be, for example, silicon dioxide (SiO) 2 ) Germanium dioxide (GeO) 2 ) Etc., but are not limited thereto.
In one embodiment, the GAA transistor further includes a dummy gate stack 110 and a dielectric layer 111, the dummy gate stack 110 spans over the top, the third side wall, and the fourth side wall of the fin, and the dielectric layer 111 is disposed on an outer wall of the dummy gate stack 110 and is spaced between the outer wall of the dummy gate stack 110 and the source region 102, and between the outer wall of the dummy gate stack 110 and the drain region 103.
The dummy gate stack may comprise polysilicon, for example, although other materials may be used. The material of the dielectric layer 11 may be a dielectric material such as silicon oxycarbonitride (SiOCN), silicon nitride (Si3N4), and may have a single-layer structure or a multi-layer structure.
The above GAA transistor can be prepared based on the preparation method provided in the embodiment of the present invention, and the scheme of preparing by using other preparation methods is not excluded.
Referring to fig. 6, a method for fabricating a GAA transistor includes:
s11: providing a substrate;
s12: forming an epitaxial layer on the substrate, wherein the epitaxial layer comprises a sacrificial layer and a silicon layer which are alternately stacked, and one layer of the epitaxial layer, which is in contact with the substrate, is a bottom sacrificial layer;
s13: etching the substrate and the epitaxial layer to form a fin;
s14: etching the residual epitaxial layer in the fin to etch a source electrode area and a drain electrode area on the first side and the second side of the fin, wherein the final etching end point is lower than the highest position of the bottom sacrificial layer in the residual epitaxial layer and is not lower than the connecting position of the substrate and the bottom sacrificial layer; the first side and the second side of the fin are two opposite sides of the fin pair;
s14: and manufacturing a source electrode in the source electrode area, and manufacturing a drain electrode in the drain electrode area.
Referring to fig. 10, in an example of step S12, an epitaxial layer may be epitaxially grown on the substrate 114, and in the step of performing the outer delay, a sacrificial layer of SiGe and a silicon layer (Si layer) may be sequentially epitaxially grown as a cycle to complete one or more cycles to form a SiGe/Si multilayer stack, where the thickness of the sacrificial layer of SiGe may be in an interval of 3nm to 30nm, the thickness of the silicon layer may also be in an interval of 3nm to 30nm, and the thickness, material and number of stacks of each sacrificial layer and each silicon layer may also be limited to the above examples.
In a further example, in the multi-cycle epitaxy process, doping techniques such as ion implantation or in-situ epitaxy doping may be further used to dope the upper surface of the substrate (the doping concentration may range from 1e15 to 1e 19), so as to change the characteristics of the upper surface of the substrate, and to help improve the selectivity of the post-etching.
For step S13, portions of the material on both sides of the substrate and the epitaxial layer along the second direction (the second direction is perpendicular to the aforementioned first direction, i.e., the left-right direction shown in fig. 11 a) may be etched away, so that: the epitaxial layer and the substrate (i.e., the substrate-in-fin 101) remaining at the middle position on the transistor substrate 113 form the desired fin. Furthermore, two sides of the fin along the second direction (i.e. the left and right sides shown in fig. 11 a) can be regarded as the third side and the fourth side of the fin mentioned above.
In one embodiment, referring to fig. 8, after step S13 and before step S14, the method may further include:
s16: forming isolation layers on the substrate outside the third side and the fourth side of the fin; wherein the third side and the fourth side of the fin are the two opposite sides of the other pair of fins;
s17: forming a dummy gate stack on the spacer and the fin spanning the top, third and fourth sidewalls of the fin;
s18: forming a dielectric layer on an outer wall of the dummy gate stack, the dielectric layer being distributed over the isolation layer and the fin.
Referring to fig. 12, regarding step S16, the third side and the fourth side of the fin are the left side and the right side of the fin in fig. 12. The manner of forming the isolation layer 112 can be understood with reference to any manner of forming an isolation layer in the art, and any suitable process can be selected to achieve the purpose according to the material used.
Referring to fig. 13a and 13b, in step S17, referring to fig. 13a and 13b, the third side and the fourth side of the fin are the left side and the right side of the fin in fig. 13a, the left-right direction is the second direction, the first side and the second side of the fin are the left side and the right side of the fin in fig. 13b, the left-right direction is the first direction, the dummy gate stack 110 may form a structure, for example, a Contraband shape, two ends of the Contraband shape may be connected to the isolation layer 112, inner sides of the Contraband shape dummy gate stack 110 may be connected to the upper surface of the epitaxial layer, two side walls of the epitaxial layer, and two side walls of the substrate 101 in a part of the fins, wherein the two side walls may be two side walls perpendicular to the second direction, and may also be two side walls parallel to the first direction.
In a further embodiment, referring to fig. 9, step S18 may include:
s181: forming a dielectric layer surrounding the outer wall of the dummy gate stack on the dummy gate stack, the isolation layer and the fin;
s182: and grinding off the part of the dielectric layer higher than the dummy gate stack.
Referring to fig. 14, in step S181, a dielectric layer 111 may specifically surround and be connected to the top of the dummy gate stack 110, the sidewall of the first side along the second direction, and the sidewall of the second side along the second direction, and the bottom of the dielectric layer 111 may be connected to the isolation layer 112. Further, the dielectric layer 111 may also surround a sidewall of a first side of the dummy gate stack 110 along the first direction and a sidewall of a second side along the first direction.
Referring to fig. 15a and 15b, after the portion of the dielectric layer 111 higher than the dummy gate stack is ground away, the top of the dummy gate stack and the top of the dielectric layer 111 may be leveled with each other in step S182.
In one embodiment, referring to fig. 7 for step S14, step S141 may include:
s141: etching the residual epitaxial layer in the fin for the first time;
s142: and carrying out secondary etching on the residual epitaxial layer in the fin, detecting the change of the corresponding etching depth, and stopping etching after the final end point is etched.
In the embodiment of the invention, for the purpose of physically avoiding the generation of parasitic FinFET source-drain, so that parasitic current cannot be led out, and effectively improving the gate control capability, a requirement is creatively provided for the etching depth (namely, the bottoms of the source region and the drain region are not lower than the joint of the substrate and the bottom sacrificial layer in the fin), so in the above scheme, in order to accurately meet the special requirement of the etching depth, the schemes of the step S141 and the step S142 are introduced, and the etching depth can be effectively and accurately ensured not to be lower than the joint of the substrate and the bottom sacrificial layer in the fin.
The first etching of the remaining epitaxial layer in the fin may include: and carrying out the first etching by adopting a plasma etching means.
In a specific embodiment, taking fig. 16 as an example, the etching end point of the first etching may be higher than the highest position of the corresponding bottom layer sacrificial layer 104 (which may also be understood as not etching the bottom layer sacrificial layer), for example, only etching the silicon layer 105 on the bottom layer sacrificial layer 104, and further, during the first etching, etching to the bottom layer sacrificial layer may be avoided, on the basis, excessive etching during the first etching may be avoided and etching directly to the bottom layer sacrificial layer may be avoided, and sufficient margin may also be provided for the second more precise etching. In other embodiments, the etching endpoint of the first etching may be lower than the highest point of the bottom sacrificial layer 104.
In one example, the first etch may be performed by using a highly directional and highly selective plasma etching technique (using a gas including one or more of fluoroalkyl, chloro, hydrogen, oxygen, and inert gas) to etch away a substantial portion of the fin above the spacer.
And etching the residual epitaxial layer in the fin for the second time, wherein the etching comprises the following steps: performing the second etching by adopting at least one of a plasma etching means, a gas etching means and a wet etching means; detecting a change in a corresponding etch depth, comprising: and detecting the change of the etching depth by adopting an OES or IEP detection means.
Wherein the OES, specifically, Optical Emission Spectroscopy, can be understood as: an optical emission spectrum; the IEP is specifically referred to as interferrometric EndPoint, and can be understood as follows: the endpoint was measured interferometrically.
In some embodiments, the final endpoint of the second etch is matched to the junction of the substrate and the underlying sacrificial layer, e.g., exactly at the junction, or close to the junction (e.g., less than a threshold difference from the junction). Taking fig. 17 as an example, the sacrificial layer retention layer 108 and the sacrificial layer retention layer 109 may be formed after the second etching.
In one example, during the second etching, the second etching can be performed by a combination of techniques such as an end point detection technique (including OES, IEP, etc.) of the plasma gas etching process, a high-selectivity gas etching, a high-selectivity wet etching, etc., so that the final etching depth is not lower than the highest point of the lowermost substrate and not higher than the highest point of the underlying sacrificial layer.
With respect to step S15, the source and drain may be fabricated by any suitable technique and combination, such as deposition, epitaxy, etc., without departing from the scope of embodiments of the invention.
After step S15, a process step of filling dielectric and planarizing may be further included.
Embodiments of the present invention further provide an electronic device, including a GAA transistor according to the above alternative schemes, for example, the GAA transistor according to fig. 4 and 5, and further, for example, any GAA transistor prepared by the above preparation method.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (14)
1. A method for manufacturing a GAA transistor, comprising:
providing a substrate;
forming an epitaxial layer on the substrate, wherein the epitaxial layer comprises a sacrificial layer and a silicon layer which are alternately stacked, and one layer of the epitaxial layer, which is in contact with the substrate, is a bottom sacrificial layer;
etching the substrate and the epitaxial layer to form a fin;
etching the residual epitaxial layer in the fin to etch a source electrode region and a drain electrode region on the first side and the second side of the fin, wherein the final end point of etching is lower than the highest position of the bottom sacrificial layer in the residual epitaxial layer and higher than the connection position of the substrate and the bottom sacrificial layer; the first side and the second side of the fin are two opposite sides of the fin pair;
manufacturing a source electrode in the source electrode area, and manufacturing a drain electrode in the drain electrode area;
etching the residual epitaxial layer in the fin to etch a source region and a drain region on the first side and the second side of the fin, specifically comprising:
etching the residual epitaxial layer in the fin for the first time;
and carrying out secondary etching on the residual epitaxial layer in the fin, detecting the change of the corresponding etching depth, and stopping etching after the final end point is etched.
2. The method of manufacturing a GAA transistor according to claim 1,
and etching the residual epitaxial layer in the fin for the first time, wherein the etching comprises the following steps: carrying out the first etching by adopting a plasma etching means;
and performing second etching on the residual epitaxial layer in the fin, wherein the second etching comprises the following steps: and performing the second etching by adopting at least one of a plasma etching means, a gas etching means and a wet etching means.
3. The method of manufacturing a GAA transistor according to claim 1,
detecting a change in a corresponding etch depth, comprising: and detecting the change of the etching depth by adopting an OES or IEP detection means.
4. The method of claim 1, wherein the etching end point of the first etching is higher than the highest point of the corresponding bottom sacrificial layer.
5. The method of claim 2, wherein a final end point of the second etching is matched to a junction of the substrate and the underlying sacrificial layer.
6. The method of manufacturing a GAA transistor according to any one of claims 1 to 5,
etching the residual epitaxial layer in the fin so as to further comprise, before etching the source region and the drain region on the two sides of the fin:
forming spacers on the substrate outside the third side and outside the fourth side of the fin; wherein the third side and the fourth side of the fin are the two opposite sides of the other pair of fins;
forming a dummy gate stack on the spacer and the fin spanning the top, third and fourth sidewalls of the fin;
forming a dielectric layer on an outer wall of the dummy gate stack, the dielectric layer being distributed over the isolation layer and the fin.
7. The method of manufacturing a GAA transistor according to claim 6,
forming a dielectric layer on sidewalls of the dummy gate stack, including:
forming a dielectric layer surrounding the outer wall of the dummy gate stack on the dummy gate stack, the isolation layer and the fin;
and grinding off the part of the dielectric layer higher than the dummy gate stack.
8. The method of claim 6, wherein the isolation layer is SiO 2 A layer.
9. The method according to any of claims 1 to 5, wherein the sacrificial layer is a SiGe layer.
10. A GAA transistor produced by the method for producing a GAA transistor according to any one of claims 1 to 9, comprising: the semiconductor device comprises a fin, a source electrode arranged in a source electrode area and a drain electrode arranged in a drain electrode area, wherein the fin comprises a substrate in the fin and an epitaxial layer arranged on the substrate in the fin, the epitaxial layer comprises a sacrificial layer and a silicon layer which are alternately stacked, and the sacrificial layer which is in contact with the substrate in the fin is a bottom sacrificial layer; the source region and the drain region are distributed on the first side and the second side of the fin and are positioned on the upper side of the substrate in the fin, the bottoms of the source region and the drain region are higher than the joint of the substrate in the fin and the bottom sacrificial layer, the bottoms of the source region and the drain region are lower than the top of the bottom sacrificial layer, and the first side and the second side of the fin are two opposite sides of the fin.
11. The GAA transistor of claim 10, further comprising a transistor substrate, the transistor substrate comprising a substrate-in-fin, the substrate-in-fin being on the transistor substrate, and the substrate-in-fin being integral with the transistor substrate.
12. The GAA transistor of claim 11, wherein the transistor substrate further comprises spacers disposed on the transistor substrate and outside third and fourth sides of the fin, wherein the third and fourth sides of the fin are opposite sides of another pair of the fins.
13. The GAA transistor of claim 10, further comprising a dummy gate stack spanning the top, third and fourth sidewalls of the fin and a dielectric layer disposed on an outer wall of the dummy gate stack and spaced between the outer wall of the dummy gate stack and the source region and between the outer wall of the dummy gate stack and the drain region.
14. An electronic device comprising the GAA transistor of any one of claims 10 to 13.
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| CN111223779A (en) * | 2018-11-23 | 2020-06-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| KR20120093731A (en) * | 2011-02-15 | 2012-08-23 | 에스케이하이닉스 주식회사 | Method of fabricating storage node contact in semiconductor device and method of fabricating capacitor using the same |
| US9793378B2 (en) * | 2013-05-31 | 2017-10-17 | Stmicroelectronics, Inc. | Fin field effect transistor device with reduced overlap capacitance and enhanced mechanical stability |
| CN109216454A (en) * | 2017-07-07 | 2019-01-15 | 中芯国际集成电路制造(北京)有限公司 | Nano-wire transistor and forming method thereof |
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| US10615256B2 (en) * | 2018-06-27 | 2020-04-07 | International Business Machines Corporation | Nanosheet transistor gate structure having reduced parasitic capacitance |
| US11430868B2 (en) * | 2018-06-27 | 2022-08-30 | Intel Corporation | Buried etch-stop layer to help control transistor source/drain depth |
| US11043578B2 (en) * | 2018-08-30 | 2021-06-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Nanowire stack GAA device with inner spacer |
| CN110875371B (en) * | 2018-08-30 | 2023-10-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
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