CN104576379A - MOSFET structure and manufacturing method - Google Patents

MOSFET structure and manufacturing method Download PDF

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Publication number
CN104576379A
CN104576379A CN201310477078.8A CN201310477078A CN104576379A CN 104576379 A CN104576379 A CN 104576379A CN 201310477078 A CN201310477078 A CN 201310477078A CN 104576379 A CN104576379 A CN 104576379A
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source
substrate
gate stack
drain
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CN104576379B (en
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尹海洲
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to PCT/CN2013/085671 priority patent/WO2015051565A1/en
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/0843—Source or drain regions of field-effect devices
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
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    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Abstract

The invention provides a MOSFET manufacturing method, which comprises the following steps of a, providing a substrate (100); b, forming a pseudo gate stack (200) on the substrate; c, forming source and drain expansion areas (101a and 101b) on the two sides of the pseudo gate stack (200); d, forming a diffusion barrier area (105) in the substrate on one side of the drain expansion area (101b); e, forming sidewalls (201) on the two sides of the pseudo gate stack (200), forming source and drain areas (102) on the two sides of the sidewalls (201), and performing annealing; f, forming interlayer dielectric layers (500), and removing the pseudo gate stack (200) to form a pseudo gate vacancy; g, sequentially depositing a gate dielectric layer (601), a work function regulation layer (602) and a gate metal layer (603) in the pseudo gate vacancy. According to the MOSFET structure manufactured by adopting the method, GIDL (Gate Induced Drain Leakage) current caused by band-to-band tunneling in an off state of the device can be effectively reduced.

Description

A kind of MOSFET structure and manufacture method thereof
Technical field
The present invention relates to a kind of MOSFET structure and manufacture method thereof.More specifically, a kind of MOSFET structure for reducing OFF leakage current and manufacture method thereof is related to.
Technical background
Along with device is more and more thinner, gate-induced drain leakage (GIDL) electric current caused by band-to-band-tunneling during device OFF state is increasing, and it has become one of problem of serious restriction MOSFET and FLASH memory.GIDL electric current itself just introduces hot hole and injects, and it makes hole to be trapped in gate oxide thus causes the unsteadiness of device and grid oxide layer can be caused to puncture.Therefore along with the reduction of oxidated layer thickness, the reliability of OFF state oxide layer will be more and more important, caused increasing concern in this respect.
The routine techniques reducing GIDL is that the temperature of raising gate oxide formation is to about 1000 DEG C to 1100 DEG C.Improve the surface density of states of oxidizing temperature mainly less substrate, to reduce GIDL.Present prevailing technology mainly grows gate oxide by rapid thermal oxidation effect technique (RTO) and insitu moisture generating process (In-situ steam generation, ISSG).But the oxidation of RTO ratio oxidation furnace can cause the worse uniformity of gate oxide, this uneven threshold voltage variation of device that causes is large, and this is undesirable; In addition utilize ISSG to grow oxide layer, narrow down to below 55nm processing procedure along with device size, the control ability that GIDL electric current reduces also is lowered gradually.
The technology of the another kind of GIDL of reduction is the concentration reducing lightly doped drain (LDD).Because device size reduces, short-channel effect becomes day by day serious problem.The main purpose of LDD is in order to this suppression short-channel effect.In order to reduce short-channel effect, LDD must adopt for ultra-shallow junctions.But in order to avoid the reduction of drive current, the concentration of LDD also strengthens day by day.If adopt the method reducing LDD concentration simply to reduce GIDL electric current, channel region resistance will be increased, reduce drive current simultaneously, allow the degradation of device.Therefore, it is also worthless for reducing integrated circuit (IC) device of GIDL electric current to future by the concentration reducing LDD simply.
Therefore, how a kind of metal-oxide-semiconductor manufacture method effectively reducing MOS device GIDL electric current is provided, has become the technical problem that industry is urgently to be resolved hurrily.
Summary of the invention
The invention provides a kind of metal-oxide-semiconductor manufacture method effectively reducing MOS device GIDL electric current, effectively inhibit the short-channel effect of device, improve device performance.Particularly, manufacture method provided by the invention comprises the following steps:
A kind of MOSFET manufacture method, comprising:
A. substrate is provided;
B. on substrate, pseudo-gate stack is formed;
C. in formation source and drain extension, pseudo-gate stack both sides;
D. in the substrate leaking side, expansion area, diffusion barrier region is formed;
E. form side wall in pseudo-gate stack both sides, form source-drain area in side wall both sides and anneal;
F. form the interlayer dielectric layer covering source-drain area, remove pseudo-gate stack to form pseudo-grid room;
G. in described pseudo-grid room, gate stack is formed.
Wherein, described scope Nei Bao extended drain region, diffusion barrier region, the impurity element forming described diffusion barrier region is carbon, and the impurity concentration of described diffusion barrier region is greater than le18cm -3.
Wherein, the method for the diffusion barrier region described in formation is ion implantation, the direction of described ion implantation and substrate transverse, and uses mask plate to cover the substrate of source; Or the angle of described ion implantation is greater than α, wherein tan α=L/H, L are the length of expansion area, source, and H is the thickness of pseudo-gate stack.
Wherein, after annealing, expansion area, described source length is greater than leaks expansion area.
Accordingly, present invention also offers a kind of MOSFET structure, comprising:
Substrate;
Be positioned at the gate stack of described types of flexure;
Be arranged in the source-drain area of described gate stack both sides substrate;
Cover the interlayer dielectric layer of described source-drain area;
Be positioned at the source and drain extension below gate stack both sides of the edge;
Be arranged in the diffusion barrier region of the substrate of source-drain area,
Wherein, the length of expansion area, described source is greater than the length of leaking expansion area.
Wherein, described diffusion impervious layer is arranged in the substrate of side, drain region, and the impurity element forming described diffusion barrier region is carbon, and the impurity concentration of described diffusion barrier region is greater than l018cm -3.
According to mos transistor structure provided by the invention, by forming diffusion block area in the Semiconductor substrate of drain terminal side, suppress after source and drain extension is formed, the Impurity Diffusion caused due to factors such as the annealing in subsequent technique, reduce the length that Lou expansion area is spread in the substrate below grid, namely reduce the region of GIDL effect effect, thus efficiently reduce the leakage current caused by GIDL effect.Compared with prior art, the present invention restrained effectively the harmful effect of short-channel effect, reduces process complexity, improves device performance.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 ~ Figure 11 is the profile according to each fabrication stage of MOSFET in a specific embodiment of the present invention.
In accompanying drawing, same or analogous Reference numeral represents same or analogous parts.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiments of the invention are described in detail.
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
The invention provides a kind of MOSFET structure, comprising:
Substrate 100;
Be positioned at the gate stack 600 above described substrate 100;
Be arranged in the source-drain area 102 of described gate stack 600 both sides substrate;
Cover the interlayer dielectric layer 500 of described source-drain area;
Be positioned at source and drain extension 101a, the 101b below gate stack 600 both sides of the edge;
Be arranged in the diffusion barrier region 105 of the substrate of source-drain area 102,
Wherein, the length of described source expansion area 101a is greater than the length of leaking expansion area 101b.
Wherein, described diffusion impervious layer 105 is arranged in the substrate 100 of side, drain region, and the impurity element forming described diffusion barrier region 105 is carbon, and the impurity concentration of described diffusion barrier region 105 is greater than le18cm -3.
Semiconductor channel area is positioned at the surface of substrate, and its preferred material is monocrystalline silicon or monocrystalline germanium alloy firm, and its thickness is 5 ~ 20nm.This region is that pole light dope is even unadulterated.When adulterating, its doping type adulterates contrary with source-drain area.
Source region and drain region lay respectively at gate stack 600 both sides, in the semiconductor layer of types of flexure.The thickness in source region is greater than the thickness in drain region.Channel part thickness near side, source region is greater than the channel thickness near drain terminal side, is 10nm ~ 60nm.
Below in conjunction with accompanying drawing, manufacture method of the present invention is described in detail, comprises the following steps.It should be noted that, the accompanying drawing of each embodiment of the present invention is only the object in order to illustrate, so there is no necessity and draws in proportion.
First provide substrate 100, described backing material can be element semiconductor, as silicon, germanium, also can be compound semiconductor, as gallium nitride, GaAs, indium phosphide etc.Consider processing compatibility, in the present embodiment, preferably, adopt silicon as the material of substrate 100.
Next, described substrate 100 forms pseudo-grid structure 200, as shown in Figure 1.Described pseudo-grid structure 200 can be individual layer, also can be multilayer.Pseudo-grid structure 200 can comprise polymeric material, amorphous silicon, polysilicon or TiN, and thickness can be 10nm ~ 200nm.In the present embodiment, pseudo-grid structure comprises polysilicon and titanium dioxide, concrete, the method of chemical vapor deposition is adopted to fill polysilicon in grid room, its height is a little less than side wall 10 ~ 20nm, then square one-tenth layer of silicon dioxide dielectric layer on the polysilicon, formation method can be epitaxial growth, oxidation, CVD etc.Then the pseudo-gate stack of stand CMOS photoetching and the deposit of etching institute is adopted to form gate electrode figure.In SiGe channel layer 101 part that covers by gate dielectric layer form the channel region of transistor.It should be noted that, below unless otherwise noted, in the embodiment of the present invention, the deposit of various dielectric material all can adopt the above-mentioned cited same or similar method of formation gate dielectric layer, therefore repeats no more.
Next, the substrate of pseudo-grid structure 200 both sides is adulterated, to form source and drain extension 101a, 101b, as shown in Figure 2.Halo injection can also be carried out, to form Halo injection region.Wherein the dopant type of source and drain extension is consistent with type of device, and the dopant type that Halo injects is contrary with type of device.
Next, deposit photoresist on described semiconductor structure, then by steps such as exposure, developments, make it expose the semiconductor structure of drain terminal side, as shown in Figure 3.Next, the ion implantation in vertical direction is carried out to described semiconductor structure, to form diffusion barrier region at drain terminal, as shown in Figure 3.The element forming described diffusion barrier region is carbon, because carbon is neutral impurity, the carrier concentration in drain region can not be affected inject carbon in leakage expansion area after, but substantially increase the impurity concentration of side, drain region, thus the scattering frequency be subject to when increasing carrier diffusion, efficiently reduce the diffusion length of charge carrier in Lou expansion area.Concrete, the impurity concentration of described diffusion barrier region 105 is greater than le18cm -3.Device architecture profile after ion implantation completes as shown in Figure 4.
Optionally, when forming diffusion barrier region 105, pseudo-gate stack also can be used to replace photoresist as mask, being realized the injection of carbon by the method for the ion implantation tilted.Concrete, as shown in Figure 5, the minimum angles of ion implantation is α, and wherein tan α=L/H, L are the length of expansion area, source 101a, and H is the thickness of pseudo-gate stack 200.Same, the impurity concentration of the diffusion barrier region 105 of formation is greater than le18cm -3.Device architecture profile after ion implantation completes as shown in Figure 6.
Next, the sidewall of gate stack forms side wall 201, for being separated by grid.Concrete, with the sacrifice side wall medium layer silicon nitride that LPCVD deposit 40nm ~ 80nm is thick, then form the silicon nitride spacer 201 that width is 35nm ~ 75nm in gate electrode both sides again by the technology of receiving a visitor.Side wall 201 can also by silica, silicon oxynitride, carborundum and combination thereof, and/or other suitable materials are formed.Side wall 201 can have sandwich construction.Side wall 201 can also be formed by comprising deposition-etch technique, and its thickness range can be 10nm-100nm, as 30nm, 50nm or 80nm.
Next, on described semiconductor structure, deposit a layer thickness is the silica dioxide medium layer that 10nm ~ 35nm is thick, and with this dielectric layer for resilient coating, ion implantation source-drain area.For P-type crystal, dopant is boron or boron fluoride or indium or gallium etc.For N-type crystal, dopant is phosphorus or arsenic or antimony etc.Doping content is 5e10 19cm -3~ le10 20cm -3.After source-drain area has adulterated, described semiconductor structure forms interlayer dielectric layer 500.In the present embodiment, the material of interlayer dielectric layer 500 is silicon dioxide.The semiconductor structure of the complete interlayer dielectric layer 500 of deposit as shown in Figure 7.
After source and drain has been injected, described semiconductor structure is annealed, to eliminate the damage produced in described semiconductor structure in ion implantation process, eliminate defect and interfacial state.Concrete, temperature range during annealing is 600 DEG C ~ 900 DEG C.In the process of annealing, the impurity in semiconductor source drain region 102 and source and drain extension 101a, 101b can carry out spreading distributing in high temperature again.Due to the existence of diffusion barrier region in semiconductor 105, the impurity leaking expansion area 101b when spreading suffered scattering much larger than the impurity of expansion area, source 101a, therefore its diffusion length greatly reduces, and the distance extended below grid because Impurity Diffusion distributes again is less than source side.As shown in Figure 9, the length of leaking expansion area 101b, much smaller than the length of source and drain extension 101a, effectively reduces the area of drain region and grid overlapping region, thus effectively reduces the leakage current caused due to GIDL effect.
Next, deposit silicon dioxide on described semiconductor structure, forms interlayer dielectric layer 500.Concrete, the methods such as CVD, epitaxial growth, oxidation can be adopted to carry out silicon dioxide growth, described silicon dioxide layer is being carried out to chemico-mechanical polishing, exposing pseudo-gate stack, as shown in Figure 10.Next, remove described pseudo-grid structure 200, form pseudo-grid room.Removing pseudo-grid structure 200 can adopt wet etching and/or dry quarter to remove, as shown in Figure 10.In the present embodiment, using plasma etching.
Next, as shown in figure 11, in grid room, gate stack 600 is formed.Gate stack can be only metal gates, also can be metal/Polysilicon Composite Structures grid, wherein polysilicon upper surface have silicide.
Concrete, preferably, gate dielectric layer 601 in pseudo-grid room, next deposition work function regulating course 602, forms gate metal layer 603 afterwards again on workfunction layers.Described gate dielectric layer 601 can be thermal oxide layer, comprises silica, silicon oxynitride; Also can be high K dielectric, such as HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al 2o 3, La 2o 3, ZrO 2, one in LaAlO or its combination, the thickness of gate dielectric layer 601 can be 1nm-10nm, such as 3nm, 5nm or 8nm.The techniques such as thermal oxidation, chemical vapour deposition (CVD) (CVD) or ald (ALD) can be adopted to form gate dielectric layer 601.
Workfunction layers can adopt the materials such as TiN, TaN to make, and its thickness range is 3nm ~ 15nm.Metal conductor layer can be one deck or sandwich construction.Its material can be TaN, TaC, TiN, TaAlN, TiAlN, MoAlN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x, NiTa xin one or its combination.Its thickness range can be such as 10nm-40nm, as 20nm or 30nm.
Finally enter the honest and kind technique of conventional cmos, comprise and click passivation layer, opening contact hole and metallization etc., the described ultra-thin SOI MOS transistor that can make.
The present invention is spreading by what form in the semiconductor structure leaking 101b side, expansion area that diffusion barrier region 105 increases charge carrier when scattering that charge carrier is subject to suppresses to anneal the leakage current reduced because GIDL causes.In the present invention, the element forming described diffusion barrier region is carbon, because carbon is neutral impurity, the carrier concentration in drain region can not be affected inject carbon in leakage expansion area after, but substantially increase the impurity concentration of side, drain region, thus the scattering frequency be subject to when increasing carrier diffusion, efficiently reduce the diffusion length of charge carrier in Lou expansion area, make the length of Lou expansion area 101b much smaller than the length of source and drain extension 101a, effectively reduce the area of drain region and grid overlapping region, thus effectively reduce the leakage current caused due to GIDL effect.Improve device performance.
Although describe in detail about example embodiment and advantage thereof, being to be understood that when not departing from the protection range of spirit of the present invention and claims restriction, various change, substitutions and modifications can being carried out to these embodiments.For other examples, those of ordinary skill in the art should easy understand maintenance scope in while, the order of processing step can change.
In addition, range of application of the present invention is not limited to the technique of the specific embodiment described in specification, mechanism, manufacture, material composition, means, method and step.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technique existed at present or be about to develop, mechanism, manufacture, material composition, means, method or step later, wherein their perform the identical function of the corresponding embodiment cardinal principle that describes with the present invention or obtain the identical result of cardinal principle, can apply according to the present invention to them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.

Claims (12)

1. a MOSFET manufacture method, comprising:
A., substrate (100) is provided;
B. on substrate, form pseudo-gate stack (200);
C. in formation source and drain extension, pseudo-gate stack (200) both sides (101a, 101b);
D. in the substrate leaking expansion area (101b) side, diffusion barrier region (105) is formed;
E. form side wall (201) in pseudo-gate stack (200) both sides, form source-drain area (102) in side wall (201) both sides and anneal;
F. form the interlayer dielectric layer (500) covering source-drain area (102), remove pseudo-gate stack (200) to form pseudo-grid room;
G. in described pseudo-grid room, gate stack is formed.
2. manufacture method according to claim 1, is characterized in that, described diffusion barrier region (105) scope Nei Bao extended drain region (101b).
3. manufacture method according to claim 1 and 2, is characterized in that, the impurity element forming described diffusion barrier region (105) is carbon.
4. the manufacture method according to claim 1,2 or 3, is characterized in that, the impurity concentration of described diffusion barrier region (105) is greater than le18cm -3.
5. manufacture method according to claim 1, is characterized in that, the method for the diffusion barrier region (105) described in formation is ion implantation.
6. manufacture method according to claim 5, is characterized in that, the direction of described ion implantation and substrate transverse, and uses mask plate to cover the substrate (100) of source.
7. manufacture method according to claim 5, is characterized in that, the angle of described ion implantation is greater than α, and wherein tan α=L/H, L are the length of expansion area, source (101a), and H is the thickness of pseudo-gate stack (200).
8. manufacture method according to claim 1, is characterized in that, after annealing, expansion area, described source (101a) length is greater than leaks expansion area (101b).
9. a MOSFET structure, comprising:
Substrate (100);
Be positioned at the gate stack (600) of described substrate (100) top;
Be arranged in the source-drain area (102) of described gate stack (600) both sides substrate;
Cover the interlayer dielectric layer (500) of described source-drain area;
Be positioned at the source and drain extension (101a, 101b) below gate stack (600) both sides of the edge;
Be arranged in the diffusion barrier region (105) of the substrate of source-drain area (102),
Wherein, the length of expansion area, described source (101a) is greater than the length of leaking expansion area (101b).
10. manufacture method according to claim 9, is characterized in that, described diffusion impervious layer (105) is arranged in the substrate (100) of side, drain region.
11. manufacture methods according to claim 10, is characterized in that, the impurity element forming described diffusion barrier region (105) is carbon.
12. manufacture methods according to claim 11, is characterized in that, the impurity concentration of described diffusion barrier region (105) is greater than le18cm -3.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5882974A (en) * 1998-04-08 1999-03-16 Advanced Micro Devices, Inc. High-performance PMOS transistor using a barrier implant in the source-side of the transistor channel
CN101087003A (en) * 2006-06-09 2007-12-12 台湾积体电路制造股份有限公司 Semiconductor element and its forming method
US20090298249A1 (en) * 2008-05-30 2009-12-03 Jan Hoentschel Drive current increase in transistors by asymmetric amorphization implantation
CN102148162A (en) * 2010-02-08 2011-08-10 台湾积体电路制造股份有限公司 Laterally diffused metal oxide semiconductor transistor and method of fabricating the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6855436B2 (en) * 2003-05-30 2005-02-15 International Business Machines Corporation Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal
CN102237277B (en) * 2010-04-27 2014-03-19 中国科学院微电子研究所 Semiconductor device and method for forming same
CN102543761A (en) * 2012-02-28 2012-07-04 上海华力微电子有限公司 Method for reducing grid induced drain leakage of semiconductor device, and MOS device manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5882974A (en) * 1998-04-08 1999-03-16 Advanced Micro Devices, Inc. High-performance PMOS transistor using a barrier implant in the source-side of the transistor channel
CN101087003A (en) * 2006-06-09 2007-12-12 台湾积体电路制造股份有限公司 Semiconductor element and its forming method
US20090298249A1 (en) * 2008-05-30 2009-12-03 Jan Hoentschel Drive current increase in transistors by asymmetric amorphization implantation
CN102148162A (en) * 2010-02-08 2011-08-10 台湾积体电路制造股份有限公司 Laterally diffused metal oxide semiconductor transistor and method of fabricating the same

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