CN102543761A - Method for reducing grid induced drain leakage of semiconductor device, and MOS device manufacturing method - Google Patents
Method for reducing grid induced drain leakage of semiconductor device, and MOS device manufacturing method Download PDFInfo
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- CN102543761A CN102543761A CN2012100507835A CN201210050783A CN102543761A CN 102543761 A CN102543761 A CN 102543761A CN 2012100507835 A CN2012100507835 A CN 2012100507835A CN 201210050783 A CN201210050783 A CN 201210050783A CN 102543761 A CN102543761 A CN 102543761A
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Abstract
The invention discloses a method for reducing grid induced drain leakage of a semiconductor device, a MOS device manufacturing method and a MOS device. The method for reducing the grid induced drain leakage of the semiconductor device comprises the following steps of: a grid sidewall film formation step, for depositing on a grid sidewall to form the grid sidewall film, wherein the introducing direction of the plasma inclines towards one side of the grid, which results in that the sidewall film formed on the grid sidewall at one side of the grid is thicker, and the sidewall film formed on the sidewall at the other side of the grid is thinner; and a sidewall film etching step, for etching the sidewall film so as to form a sidewall of which the sidewall width at a source side decreases and a sidewall of which the sidewall width at the drain side increases. The MOS device manufacturing method further comprises a source and drain doping step for doping of the source and the drain. According to the invention, the distance between doped ion of the drain and a channel is drawn farther, and the distance between the doped ion of the source and the channel is drawn closer, the longitudinal electric field strength of the drain is reduced while the effective length of the channel remains unchanged, thus, the grid induced drain leakage of the semiconductor device is reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture; More particularly, the present invention relates to a kind of semiconductor device gate that reduces induces the method for drain leakage, has adopted this to reduce MOS device making method and the MOS device of being processed by this MOS device making method that semiconductor device gate is induced the method for drain leakage.
Background technology
Gate-induced drain leaks (GIDL, Gate-Induced Drain Leakage) and is meant, is turn-offing when device under the situation of (off-state); (being Vg=0) is if drain electrode links to each other (being Vd=Vdd) with Vdd; Because the overlapping between grid and the drain electrode; Can there be highfield in overlapping region between grid and drain electrode, and band-to-band-tunneling effect (band to band tunneling) can take place under the highfield effect charge carrier, thereby causes the leakage current between the drain-to-gate.
The gate-induced drain leakage current has become the one of the main reasons of aspects such as influencing small size MOS device reliability, power consumption, and it also has material impact to the erasable operation of memory devices such as EEPROM simultaneously.When technology gets into sub-micro after the epoch, owing to device size dwindles day by day, numerous integrity problems of GIDL electric current initiation become serious further.
For reducing the gate-induced drain leakage current of device, the present invention is in side wall (Spacer) film deposition process, and reactive plasma is introduced at the oblique angle; Make post-depositional film, the side wall film on the drain terminal sidewall is thicker, and the side wall film on the distolateral wall in source is thinner; Make that the lateral wall width of drain terminal increases after the etching; And the lateral wall width of source end reduces, and after highly doped injection and annealing process were leaked in ensuing source, the dopant ion of drain terminal was zoomed out from channel distance; The dopant ion of source end and the distance of raceway groove are furthered; Keeping having reduced the longitudinal electric field intensity of drain terminal under the constant situation of raceway groove effective length (Effective Channel Length), cause drain leakage current thereby reduced semiconductor device gate.
Summary of the invention
Technical problem to be solved by this invention is to having above-mentioned defective in the prior art, provides a kind of semiconductor device gate that can reduce effectively to induce the semiconductor device gate that reduces of drain leakage current to induce the method for drain leakage, adopted this to reduce MOS device making method and the MOS device of being processed by this MOS device making method that semiconductor device gate is induced the method for drain leakage.
According to a first aspect of the invention; A kind of method that semiconductor device gate is induced drain leakage that reduces is provided; It comprises: the grid curb wall film forms step, is used for forming the grid curb wall film on the gate lateral wall through being deposited on, and wherein the incoming direction of reactant plasma is to the grid lopsidedness; So that the grid curb wall film that forms on the gate lateral wall of said grid one side is thicker, and the grid curb wall film that forms on the sidewall of grid opposite side is thinner; And grid curb wall film etch step; Be used for said grid curb wall film is carried out etching; To form the gate lateral wall that gate lateral wall that the source side lateral wall width reduces and drain side lateral wall width increase, make the source side gate sidewall thus less than the drain side gate lateral wall.
Preferably, form in the step,, make the grid curb wall film thickness of source side and the grid curb wall film thickness sum of drain side equal predetermined value through regulating the side wall film deposition conditions at said grid curb wall film.
Preferably, in said grid curb wall film etch step, make the width sum of grid curb wall of width and drain side of the grid curb wall of source side equal predetermined value.
According to the method that semiconductor device gate is induced drain leakage that reduces that first aspect present invention provided, can realize that the thickness of the grid curb wall on the gate lateral wall of grid both sides is different.
According to a second aspect of the invention; A kind of MOS device making method is provided; It comprises: the grid curb wall film forms step, is used for forming the grid curb wall film on the gate lateral wall through being deposited on, and wherein the incoming direction of reactant plasma tilts to drain terminal; So that the grid curb wall film that forms on the gate lateral wall of drain side is thicker, and the grid curb wall film that forms on the sidewall of source side is thinner; Grid curb wall film etch step is used for said grid curb wall film is carried out etching, to form the gate lateral wall that gate lateral wall that the source side lateral wall width reduces and drain side lateral wall width increase, makes the source side gate sidewall less than the drain side gate lateral wall thus; The doping step is leaked in the source, is used for after said grid curb wall film etch step, doping being carried out in drain electrode and source electrode.
Preferably, form in the step,, make the grid curb wall film thickness of source side and the grid curb wall film thickness sum of drain side equal predetermined value through regulating the side wall film deposition conditions at said grid curb wall film.
Preferably, in said grid curb wall film etch step, make the width sum of grid curb wall of width and drain side of the grid curb wall of source side equal predetermined value.
Preferably.Said MOS device making method also comprises annealing steps.
According to a third aspect of the invention we, a kind of MOS device of processing according to the described MOS device making method of second aspect present invention is provided.
According to the present invention; Induce the problem of drain leakage current to the grid of MOS device in the prior art, the present invention introduces reactive plasma with the oblique angle mode in the grid curb wall film deposition process; Make that the grid curb wall film on the gate lateral wall of drain terminal is thicker; Grid curb wall film on the gate lateral wall of source end is thinner, make that the grid curb wall width of drain terminal increases after the etching, and the grid curb wall width of source end reduces.After highly doped injection and annealing process are leaked in ensuing source; The dopant ion of drain terminal is zoomed out from channel distance; The dopant ion of source end and the distance of raceway groove are furthered; Keeping having reduced the longitudinal electric field intensity of drain terminal under the constant situation of raceway groove effective length (Effective ChannelLength), induce drain leakage (GIDL) electric current thereby reduced semiconductor device gate.
Description of drawings
In conjunction with accompanying drawing, and, will more easily more complete understanding be arranged and more easily understand its attendant advantages and characteristic the present invention through with reference to following detailed, wherein:
Fig. 1 to Fig. 3 schematically shows the MOS device making method according to prior art.
Fig. 4 to Fig. 6 schematically shows the MOS device making method according to the embodiment of the invention.
Need to prove that accompanying drawing is used to explain the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure possibly not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.
Embodiment
In order to make content of the present invention clear more and understandable, content of the present invention is described in detail below in conjunction with specific embodiment and accompanying drawing.
In the MOS device making method of prior art, to shown in Figure 3, at first be formed with shallow trench isolation execution deposition on the side wall of the grid 1 on the Semiconductor substrate 2 of (shown in the oblique line part) like Fig. 1.The cross section of deposition back device is as shown in Figure 1, and wherein grid 1 both sides have formed the side wall film 10 of deposition.
Next carry out anisotropic dry etching, the grid curb wall that the etching opisthogenesis leaks becomes symmetrical structure, and is as shown in Figure 2.Then, heavy doping and annealing process are leaked in the execution source, and the dopant ion that drain electrode 3 and source electrode 4 places form distributes as shown in Figure 3, and the dopant ion of drain electrode 3 and source electrode 4 both sides determines apart from the distance of the device channel width by grid curb wall.
With the prior art contrast of Fig. 1 to Fig. 3, the MOS device making method according to the embodiment of the invention is described with reference now to Fig. 4 to Fig. 6.
At first, on the side wall that is formed with the grid 1 on the Semiconductor substrate 2 that shallow trench isolation leaves, carry out deposition, to form side wall film 10.But different with prior art shown in Figure 1 is, in embodiments of the present invention, in the deposition process of the side wall film 10 of grid, introduces the reactant plasma with the mode at oblique angle.More particularly; Make the incoming direction of the reactant plasma in the deposition process of grid curb wall film 10 (be called reactant plasma incoming direction X; As shown in Figure 4) tilt to drain terminal; The grid curb wall film that forms on the gate lateral wall of 3 one sides (being called drain terminal) so that drain is thicker, and simultaneously, the grid curb wall film that forms on the gate lateral wall of source electrode 4 one sides (being called the source end) is thin (as shown in Figure 4).
Form in the step at the grid curb wall film; Conditioned reaction thing plasma incoming direction X as the case may be; If thickness differs big more between the grid curb wall film that forms on the gate lateral wall of grid curb wall film of promptly hoping to form on the gate lateral wall of drain terminal and source end, then the angle of reactant plasma incoming direction X and vertical direction (vertical direction) is big more; Otherwise; If thickness differs more little between the grid curb wall film that forms on the gate lateral wall of grid curb wall film of hoping to form on the gate lateral wall of drain terminal and source end, then the angle of reactant plasma incoming direction X and vertical direction (vertical direction) is more little.
And; Form in the step at this grid curb wall film, preferably, through suitable adjusting side wall film deposition conditions (the for example conditions such as energy of reactant plasma); To realize that the thickness that the side wall film increases on the drain terminal sidewall equals the thickness that the side wall film reduces on the distolateral wall in source; Grid curb wall film thickness sum on the gate lateral wall at realization source leakage two ends remains unchanged thus, that is, make the grid curb wall film thickness sum that two ends are leaked in the source equal predetermined value.
Next carry out the grid curb wall etch step, be used for grid curb wall film 10 is carried out etching, with the gate lateral wall of formation source side and the gate lateral wall of drain side, the result after the etching is as shown in Figure 5.That is, the grid curb wall film 10 after the etching remains on the grid side walls as gate lateral wall.
In this grid curb wall etch step, because the side wall film on the gate lateral wall of source end is thinner, the final grid curb wall that forms is also thinner, and the grid curb wall film on the gate lateral wall of drain terminal is thicker, and the final grid curb wall that forms is also thicker.The cross section of the device after the grid curb wall etching technics is as shown in Figure 5.
And; Because grid curb wall film thickness sum remain unchanged (as shown in Figure 4) is leaked on total gate lateral wall at two ends in the source that is preferably such that; Equal the width that the grid curb wall of source end reduces so preferably can realize width that the grid curb wall of drain terminal increases; The width sum that side wall is leaked in total source still remains unchanged promptly, makes the width sum of grid curb wall of source drain terminal equal predetermined value.
Heavy doping and annealing process are leaked in the source of next carrying out; Because the distance of heavy doping ion and device channel is determined by the width of side wall; Therefore after mixing; The heavy doping ion of drain terminal and the distance of device channel are zoomed out, the heavy doping ion of source end and the distance of device channel furthered (as shown in Figure 6).But remain unchanged because the width sum of side wall is leaked in the source, so the distance that leak between the heavy doping ion in the source remains unchanged.
At drain terminal; Because the distance between heavy doping ion and raceway groove is zoomed out, drain when gate turn-off when meeting Vdd, weaken in the electric field strength of grid and drain terminal overlapping region; Thereby reduced the band-to-band-tunneling effect of charge carrier, reduced semiconductor device gate and caused drain leakage current.
Therefore; Induce the comparatively serious semiconductor device of drain leakage current problem for grid; Can make that thickness differs big more between the grid curb wall film that forms on the gate lateral wall of the grid curb wall film that forms on the gate lateral wall of drain terminal and source end, thereby make the grid curb wall film form the reactant plasma incoming direction X inclination more serious in the step as described in the front with respect to vertical direction; And induce the drain leakage current problem for grid is not so serious semiconductor device comparatively speaking; Can make that thickness differs less between the grid curb wall film that forms on the gate lateral wall of the grid curb wall film that forms on the gate lateral wall of drain terminal and source end, thereby make the grid curb wall film form reactant plasma incoming direction X in the step as described in the front with respect to the littler crustal inclination of vertical direction.
In addition; Because when the distance of the heavy doping ion of drain terminal and raceway groove is zoomed out; The heavy doping ion of source end and the distance of raceway groove are furthered; The distance that leak between the heavy doping ion in total source remains unchanged, so the length of effective channel of device remains unchanged basically, and other performances of device are able to keep.
Other step of MOS device making method of the present invention (for example annealing steps etc.) is identical with prior art, therefore repeats no more at this.
In a word, the MOS device making method according to the embodiment of the invention at least also has following advantage:
1. do not increase original processing step.
2. through in the side wall thin film deposition processes; The reactant plasma is introduced at the oblique angle, makes that the side wall film thickness is thicker on the gate lateral wall of drain terminal after the deposition; The side wall film thickness is thinner on the gate lateral wall of source end, and the grid curb wall overall width at leakage two ends, source remains unchanged.
3. after the side wall etching, the grid curb wall of the final source end that forms is thinner, and the grid curb wall of drain terminal is thicker, and the side wall thicknesses sum remains unchanged on the gate lateral wall at total leakage two ends, source.
4. after heavy doping injection and annealing process are leaked in the source; The heavy doping ion of drain terminal and channel distance are zoomed out; The longitudinal electric field strength reduction of drain terminal, the grid current that therefore forms owing to the hot carrier injection reduces, thereby has reduced the damage that the semiconductor device hot carrier is injected.
5. at drain terminal; Because the distance between heavy doping ion and raceway groove is zoomed out, drain when gate turn-off when meeting Vdd, weaken in the electric field strength of grid and drain terminal overlapping region; Thereby reduced the band-to-band-tunneling effect of charge carrier, reduced semiconductor device gate and caused drain leakage current.
6. when the distance of the heavy doping ion of drain terminal and raceway groove is zoomed out; The heavy doping ion of source end and the distance of raceway groove are furthered; The distance that leak between the heavy doping ion in the source remains unchanged, so the length of effective channel of device remains unchanged basically, and other performances of device are able to keep.
Need to prove; For example; Though to be formed with the semiconductor structure that shallow trench isolation leaves principle of the present invention is shown, the present invention is not limited to this, but can carry out MOS device making method of the present invention not being formed with on the semiconductor structure that shallow trench isolation leaves.
In another embodiment of the present invention, a kind of semiconductor device of being processed by this MOS device making method is provided, for example MOS device, perhaps cmos device.
It is understandable that though the present invention with the preferred embodiment disclosure as above, yet the foregoing description is not in order to limit the present invention.For any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the technology contents of above-mentioned announcement capable of using is made many possible changes and modification to technical scheme of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (8)
1. one kind reduces the method that semiconductor device gate is induced drain leakage, it is characterized in that comprising:
The grid curb wall film forms step; Be used for forming the grid curb wall film on the gate lateral wall through being deposited on; Wherein the incoming direction of reactant plasma is to the grid lopsidedness; So that the grid curb wall film that forms on the gate lateral wall of said grid one side is thicker, and the grid curb wall film that forms on the sidewall of grid opposite side is thinner; And
Grid curb wall film etch step is used for said grid curb wall film is carried out etching, to form the gate lateral wall that gate lateral wall that the source side lateral wall width reduces and drain side lateral wall width increase, makes the source side gate sidewall less than the drain side gate lateral wall thus.
2. according to claim 1ly reduce the method that semiconductor device gate is induced drain leakage; It is characterized in that; Form in the step at said grid curb wall film; Through regulating the side wall film deposition conditions, make the grid curb wall film thickness of source side and the grid curb wall film thickness sum of drain side equal predetermined value.
3. according to claim 2ly reduce the method that semiconductor device gate is induced drain leakage; It is characterized in that; In said grid curb wall film etch step, make the width sum of grid curb wall of width and drain side of the grid curb wall of source side equal predetermined value.
4. MOS device making method is characterized in that comprising:
The grid curb wall film forms step; Be used for forming the grid curb wall film on the gate lateral wall through being deposited on; Wherein the incoming direction of reactant plasma tilts to drain side; So that the grid curb wall film that forms on the gate lateral wall of drain side is thicker, and the grid curb wall film that forms on the sidewall of source side is thinner;
Grid curb wall film etch step is used for said grid curb wall film is carried out etching, to form the gate lateral wall that gate lateral wall that the source side lateral wall width reduces and drain side lateral wall width increase, makes the source side gate sidewall less than the drain side gate lateral wall thus;
The doping step is leaked in the source, is used for after said grid curb wall film etch step, doping being carried out in drain electrode and source electrode.
5. MOS device making method according to claim 4; It is characterized in that; Form in the step at said grid curb wall film,, make the grid curb wall film thickness of source side and the grid curb wall film thickness sum of drain side equal predetermined value through regulating the side wall film deposition conditions.
6. MOS device making method according to claim 5 is characterized in that, in said grid curb wall film etch step, makes the width sum of grid curb wall of width and drain side of the grid curb wall of source side equal predetermined value.
7. according to the described MOS device making method of one of claim 4 to 6, it is characterized in that also comprising annealing steps.
8. MOS device of processing according to the described MOS device making method of one of claim 4 to 7.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015051565A1 (en) * | 2013-10-13 | 2015-04-16 | 中国科学院微电子研究所 | Mosfet structure and manufacturing method therefor |
| CN108268717A (en) * | 2018-01-18 | 2018-07-10 | 上海华虹宏力半导体制造有限公司 | A kind of novel grid induced drain leakage current model |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04186732A (en) * | 1990-11-21 | 1992-07-03 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| US20100029082A1 (en) * | 2008-08-04 | 2010-02-04 | International Business Machines Corporation | Method and apparatus for angular high density plasma chemical vapor deposition |
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2012
- 2012-02-28 CN CN2012100507835A patent/CN102543761A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04186732A (en) * | 1990-11-21 | 1992-07-03 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| US20100029082A1 (en) * | 2008-08-04 | 2010-02-04 | International Business Machines Corporation | Method and apparatus for angular high density plasma chemical vapor deposition |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015051565A1 (en) * | 2013-10-13 | 2015-04-16 | 中国科学院微电子研究所 | Mosfet structure and manufacturing method therefor |
| CN108268717A (en) * | 2018-01-18 | 2018-07-10 | 上海华虹宏力半导体制造有限公司 | A kind of novel grid induced drain leakage current model |
| CN108268717B (en) * | 2018-01-18 | 2021-07-23 | 上海华虹宏力半导体制造有限公司 | Novel grid-induced drain leakage current model |
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Application publication date: 20120704 |