CN102737995B - The manufacture method of semiconductor device - Google Patents
The manufacture method of semiconductor device Download PDFInfo
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- CN102737995B CN102737995B CN201110082046.9A CN201110082046A CN102737995B CN 102737995 B CN102737995 B CN 102737995B CN 201110082046 A CN201110082046 A CN 201110082046A CN 102737995 B CN102737995 B CN 102737995B
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Abstract
The invention discloses a kind of method making semiconductor device, comprising: the Semiconductor substrate that the first grid structure being formed and being positioned at nucleus and the second grid structure being positioned at neighboring area are provided; The first photoresist layer is formed at nucleus; Halo ion implantation and shallow doped drain ion implantation is performed to form the second halo ion implanted region and the second shallow doped region in the Semiconductor substrate of second grid structure both sides in neighboring area; Remove the first photoresist layer; Perform pre-amorphous ion implantation, to form amorphous layer in the Semiconductor substrate do not covered by first grid structure and second grid structure; The second photoresist layer is formed in neighboring area; Halo ion implantation and shallow doped drain ion implantation is performed to form the first halo ion implanted region and the first shallow doped region in the Semiconductor substrate of first grid structure both sides at nucleus.Method of the present invention reduces knot mutability and the junction capacitance of nucleus when can ensure the hot electron injection reliability of peripheral devices.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of manufacture method of semiconductor device.
Background technology
Increase gradually along with to very lagre scale integrated circuit (VLSIC) high integration and high performance demand, the critical size of semiconductor device is more and more less.But, when channel length shorten to can comparable with the depletion width sum of source electrode and drain electrode time, trench edges (as source electrode, drain electrode and edge, insulation layer) the disturbance that causes become more remarkable, the performance of semiconductor device will depart from original long channel characteristic.Such as, in short channel condition, threshold voltage (i.e. the cut-in voltage of grid) can reduce along with the increase of drain voltage, thus control the threshold voltage of semiconductor device and the characteristic such as electric leakage causes adverse effect.The impact of the above-mentioned characteristic on semiconductor device occurred because channel length shortens is called as short-channel effect (Short Channel Effect).
Along with the shortening of the characteristic size of semiconductor device, process for fabrication of semiconductor device introduces for ultra-shallow junctions (shallower junction) technology, avoids short-channel effect.The pre-amorphous ion implantation (PAI) of germanium is one of effective ways forming for ultra-shallow junctions, but needs to be optimized this technique, to realize the Performance And Reliability of semiconductor device.
Summary of the invention
The present invention proposes a kind of method making semiconductor device, comprising: a) provide Semiconductor substrate, described Semiconductor substrate is formed with the first grid structure being positioned at nucleus and the second grid structure being positioned at neighboring area; B) on described nucleus, the first photoresist layer is formed, to cover the described Semiconductor substrate and described first grid structure that are positioned at described nucleus; C) halo ion implantation and shallow doped drain ion implantation is performed, to form the second halo ion implanted region and the second shallow doped region in the described Semiconductor substrate of the both sides of described second grid structure in described neighboring area; D) described first photoresist layer is removed; E) pre-amorphous ion implantation is performed, to form amorphous layer in the described Semiconductor substrate do not covered by described first grid structure and described second grid structure; F) on described neighboring area, the second photoresist layer is formed, to cover the described Semiconductor substrate and described second grid structure that are positioned at described neighboring area; G) halo ion implantation and shallow doped drain ion implantation is performed, to form the first halo ion implanted region and the first shallow doped region in the described Semiconductor substrate of the both sides of described first grid structure at described nucleus.
Preferably, described c) step comprises following two kinds of executive modes: first perform halo ion implantation to form described second halo ion implanted region in the described Semiconductor substrate of the both sides of described second grid structure, then perform shallow doped drain ion implantation to form described second shallow doped region in the described Semiconductor substrate of the both sides of described second grid structure; Or first perform shallow doped drain ion implantation to form described second shallow doped region in the described Semiconductor substrate of the both sides of described second grid structure, then perform halo ion implantation to form described second halo ion implanted region in the described Semiconductor substrate of the both sides of described second grid structure.
Preferably, described second grid structure is the grid structure of nmos device and/or the grid structure of PMOS device.
Preferably, described second grid structure is the grid structure of nmos device, and the ion adulterated in described second shallow doped region is phosphonium ion and/or arsenic ion.
Preferably, the implantation dosage of described phosphonium ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of described phosphonium ion is 5-40keV.
Preferably, the implantation dosage of described arsenic ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of described arsenic ion is 1-10keV.
Preferably, described second grid structure is the grid structure of nmos device, and the ion adulterated in described halo ion implanted region is boron ion and/or indium ion.
Preferably, the implantation dosage of described boron ion is 1 × 10
13-1 × 10
14cm
-2, the Implantation Energy of described boron ion is 4-12keV.
Preferably, the implantation dosage of described indium ion is 1 × 10
12-1 × 10
14cm
-2, the Implantation Energy of described indium ion is 20-80keV.
Preferably, perform in described pre-amorphous ion implantation process, the ion of injection is germanium ion.
Preferably, the implantation dosage of described germanium ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of described germanium ion is 5-30keV.
Preferably, described g) step comprises following two kinds of executive modes: first perform halo ion implantation to form described first halo ion implanted region in the described Semiconductor substrate of the both sides of described first grid structure, then perform shallow doped drain ion implantation to form described first shallow doped region in the described Semiconductor substrate of the both sides of described first grid structure; Or first perform shallow doped drain ion implantation to form described first shallow doped region in the described Semiconductor substrate of the both sides of described first grid structure, then perform halo ion implantation to form described first halo ion implanted region in the described Semiconductor substrate of the both sides of described first grid structure.
Preferably, described first grid structure is the grid structure of nmos device and/or the grid structure of PMOS device.
Preferably, described first grid structure is the grid structure of nmos device, and the ion adulterated in described first shallow doped region is phosphonium ion and/or arsenic ion.
Preferably, the implantation dosage of described phosphonium ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of described phosphonium ion is 5-40keV.
Preferably, the implantation dosage of described arsenic ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of described arsenic ion is 1-10keV.
Preferably, described first grid structure is the grid structure of nmos device, and the ion adulterated in described halo ion implanted region is boron ion and/or indium ion.
Preferably, the implantation dosage of described boron ion is 1 × 10
13-1 × 10
14cm
-2, the Implantation Energy of described boron ion is 1-10keV.
Preferably, the implantation dosage of described indium ion is 1 × 10
12-1 × 10
14cm
-2, the Implantation Energy of described indium ion is 20-80keV.
Preferably, described method also comprises the step removing described second photoresist layer.
Preferably, after removing described second photoresist layer, also comprise the step forming source electrode and drain electrode.
Method of the present invention is by before the shallow Doped ions injection and halo ion implantation of nucleus, and inject at the shallow Doped ions of neighboring area and perform pre amorphous ion injection process after halo ion implantation, can at the doping profile not affecting neighboring area, while ensureing the hot electron injection reliability of peripheral devices, reduce the knot mutability of nucleus, reduce junction capacitance.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 makes semiconductor device technology flow chart according to one embodiment of the present invention;
Fig. 2 A-2K is for making the cutaway view of the device that each step obtains in semiconductor device technology flow process according to one embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it will be apparent to one skilled in the art that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Fig. 1 shows and makes semiconductor device technology flow chart according to one embodiment of the present invention, and Fig. 2 A-2K shows the cutaway view making the device that each step obtains in semiconductor device technology flow process according to one embodiment of the present invention.Manufacture method of the present invention is described in detail below in conjunction with Fig. 1 and Fig. 2 A-2K.
Perform step 101, Semiconductor substrate is provided, this Semiconductor substrate is formed with the first grid structure being positioned at nucleus and the second grid structure being positioned at neighboring area (I/O region).As shown in Figure 2 A, provide Semiconductor substrate 200, Semiconductor substrate 200 comprises nucleus M and neighboring area N.In nucleus M, be formed with first grid structure 201A, in the N of neighboring area, be formed with second grid structure 201B.
Semiconductor substrate 200 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
First grid structure 201A and second grid structure 201B can comprise gate oxide layers (not shown) and gate material layers (not shown) respectively.Exemplarily, gate oxide layers can be the silicon dioxide layer formed at the temperature of about 800 ~ 1000 degrees Celsius in oxygen steam ambient by oxidation technology.Exemplarily, gate material layers can be the doped polysilicon layer adopting chemical vapour deposition technique to be formed.
Although Fig. 2 A only uses first grid structure 201A to represent the grid structure being positioned at nucleus M, second grid structure 201B is only used to represent the grid structure being positioned at neighboring area N, but those skilled in the art should be understood that, nucleus M and neighboring area N can comprise multiple grid structure.First grid structure 201A can be the grid structure of nmos device, also can be the grid structure of PMOS device.When nucleus M comprises multiple grid structure, described multiple grid structure can be the grid structure of nmos device, also can be the grid structure of PMOS device, or comprise the grid structure of nmos device and the grid structure of PMOS device simultaneously.Similarly, second grid structure 201B can be the grid structure of nmos device, also can be the grid structure of PMOS device.When neighboring area N comprises multiple grid structure, described multiple grid structure can be the grid structure of nmos device, also can be the grid structure of PMOS device, or comprise the grid structure of nmos device and the grid structure of PMOS device simultaneously.
Perform step 102, nucleus forms the first photoresist layer, to cover the Semiconductor substrate and first grid structure that are positioned at nucleus.As shown in Figure 2 B, the first photoresist layer 202 covers Semiconductor substrate 200 in nucleus M and first grid structure 201A.Exemplarily, the first photoresist layer 202 can be adopt the techniques such as coating, exposure, development to be formed.In addition, before coating photoresist, anti-reflecting layer can also be formed at nucleus M, to reduce in exposure process light in the reflection on photoresist surface.
Perform step 103, halo ion implantation (Pocket implantation) and shallow doped drain (LDD) ion implantation is performed, to form the second halo ion implanted region and the second shallow doped region in the Semiconductor substrate of the both sides of second grid structure in neighboring area.Wherein, the execution sequence that halo ion implantation and shallow Doped ions inject can exchange.Specifically, this step comprises following two kinds of executive modes: the first, first perform halo ion implantation to form the second halo ion implanted region in the Semiconductor substrate of the both sides of second grid structure, then perform shallow doped drain ion implantation to form the second shallow doped region in the Semiconductor substrate of the both sides of second grid structure; The second, first perform shallow doped drain ion implantation to form the second shallow doped region in the Semiconductor substrate of the both sides of second grid structure, then perform halo ion implantation to form the second halo ion implanted region in the Semiconductor substrate of the both sides of second grid structure.
Below in conjunction with accompanying drawing 2C-2D, the second executive mode is described in detail.
As shown in Figure 2 C, with second grid structure 201B for mask performs shallow doped drain ion implantation to neighboring area N, to form the second shallow doped region 203B in the Semiconductor substrate of second grid structure 201B both sides.When second grid structure 201B is the grid structure of nmos device, the dopant type of adulterating in the second shallow doped region 203B is N-type, such as arsenic (As) and/or phosphorus (P); When second grid structure 201B is the grid structure of PMOS device, the dopant type of adulterating in the second shallow doped region 203B is P type, such as boron (B) and/or indium (In).Similarly, when namely neighboring area comprises the grid structure of nmos device, when comprising again the grid structure of PMOS device, this step can comprise further carries out ion implantation to form the shallow doped region of N-type and to carry out ion implantation to form the shallow doped region of P type to PMOS device to nmos device respectively.Wherein, the dopant type of adulterating in the shallow doped region of N-type is N-type, such as arsenic and/or phosphorus; The dopant type of adulterating in the shallow doped region of P type is P type, such as boron and/or indium.According to one embodiment of the invention, second grid structure 201B is the grid structure of nmos device, and the ion adulterated in the second shallow doped region 203B is phosphonium ion, and wherein, the implantation dosage of phosphonium ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of phosphonium ion is 5-40keV.According to a further embodiment of the invention, second grid structure 201B is the grid structure of nmos device, and the ion adulterated in the second shallow doped region 203B is arsenic ion, and wherein, the implantation dosage of arsenic ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of described arsenic ion is 1-10keV.
As shown in Figure 2 D, halo ion implantation is performed to form the second halo ion implanted region 204B in the Semiconductor substrate 200 of the both sides at second grid structure 201B to neighboring area N.Under normal circumstances, the impurity be injected in the second halo ion implanted region 204B has the contrary type of impurity in doped region 203B shallow with second.When second grid structure 201B is the grid structure of nmos device, when the dopant type of adulterating in the second shallow doped region 203B is N-type, the dopant type of adulterating in the second halo ion implanted region 204B is P type, such as boron (B) and/or indium (In); When second grid structure 201B is the grid structure of PMOS device, when the dopant type of adulterating in the second shallow doped region 203B is P type, the dopant type of adulterating in the second halo ion implanted region 204B is N-type, such as arsenic (As) and/or phosphorus (P).Those skilled in the art is appreciated that equally, when namely neighboring area comprises the grid structure of nmos device, when comprising again the grid structure of PMOS device, this step can comprise further carries out halo ion implantation to form P type halo ion implanted region and to carry out ion implantation to form N-type halo ion implanted region to PMOS device to nmos device respectively.Wherein, the dopant type of adulterating in N-type halo ion implanted region is N-type, such as arsenic and/or phosphorus; The dopant type of adulterating in P type halo ion implanted region is P type, such as boron and/or indium.According to one embodiment of the invention, second grid structure 201B is the grid structure of nmos device, and the ion adulterated in the second halo ion implanted region 204B is boron ion, and wherein, the implantation dosage of boron ion is 1 × 10
13-1 × 10
14cm
-2, the Implantation Energy of boron ion is 4-12keV.According to a further embodiment of the invention, second grid structure 201B is the grid structure of nmos device, and the ion adulterated in the second halo ion implanted region 204B is indium ion, and wherein, the implantation dosage of indium ion is 1 × 10
12-1 × 10
14cm
-2, the Implantation Energy of indium ion is 20-80keV.
Perform step 104, remove the first photoresist layer.As shown in Figure 2 E, the first photoresist layer 202 on nucleus M is removed.
Perform step 105, perform pre-amorphous ion implantation, to form amorphous layer in the Semiconductor substrate do not covered by first grid structure and second grid structure.As shown in Figure 2 F, pre-amorphous ion implantation (PAI) is carried out to the semiconductor device structure obtained through above-mentioned steps, in the Semiconductor substrate 200 do not covered by first grid structure 201A and second grid structure 201B, form amorphous layer 205.Inject at the shallow Doped ions of neighboring area due to pre amorphous ion injection process and perform after halo ion implantation, therefore can not affect the doping profile of neighboring area, ensureing the hot electron injection reliability (HCI) of peripheral devices.In addition, amorphous layer 205 is positioned at the surf zone of Semiconductor substrate 200, and the concentration at knot place when can make to carry out halo ion implantation to nucleus in subsequent technique reduces, thus reduces knot mutability and reduce junction capacitance.
Exemplarily, perform in pre-amorphous ion implantation process, the ion of injection is germanium ion.Exemplarily, the implantation dosage of germanium ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of germanium ion is 5-30keV.
Perform step 106, neighboring area forms the second photoresist layer, to cover the Semiconductor substrate and second grid structure that are positioned at neighboring area.As shown in Figure 2 G, the second photoresist layer 206 covers Semiconductor substrate 200 in the N of neighboring area and second grid structure 201B.Exemplarily, the second photoresist layer 206 can be adopt the techniques such as coating, exposure, development to be formed.In addition, before coating photoresist, anti-reflecting layer can also be formed at neighboring area N, to reduce in exposure process light in the reflection on photoresist surface.
Perform step 107, perform halo ion implantation and shallow doped drain ion implantation, to form the first halo ion implanted region and the first shallow doped region in the Semiconductor substrate of the both sides of first grid structure at nucleus.Wherein, the execution sequence that halo ion implantation and shallow Doped ions inject can exchange.Specifically, this step comprises following two kinds of executive modes: the first, first perform halo ion implantation to form the first halo ion implanted region in the Semiconductor substrate of the both sides of first grid structure, then perform shallow doped drain ion implantation to form the first shallow doped region in the Semiconductor substrate of the both sides of first grid structure; The second, first perform shallow doped drain ion implantation to form the first shallow doped region in the Semiconductor substrate of the both sides of first grid structure, then perform halo ion implantation to form the first halo ion implanted region in the Semiconductor substrate of the both sides of first grid structure.
Below in conjunction with accompanying drawing 2H-2I, the second executive mode is described in detail.
As illustrated in figure 2h, with first grid structure 201A for mask performs shallow doped drain ion implantation to nucleus M, to form the first shallow doped region 203A in the Semiconductor substrate of first grid structure 201A both sides.When first grid structure 201A is the grid structure of nmos device, the dopant type of adulterating in the first shallow doped region 203A is N-type, such as arsenic (As) and/or phosphorus (P); When first grid structure 201A is the grid structure of PMOS device, the dopant type of adulterating in the first shallow doped region 203A is P type, such as boron (B) and/or indium (In).Similarly, when namely nucleus comprises the grid structure of nmos device, when comprising again the grid structure of PMOS device, this step can comprise further carries out ion implantation to form the shallow doped region of N-type and to carry out ion implantation to form the shallow doped region of P type to PMOS device to nmos device respectively.Wherein, the dopant type of adulterating in the shallow doped region of N-type is N-type, such as arsenic and/or phosphorus; The dopant type of adulterating in the shallow doped region of P type is P type, such as boron and/or indium.According to one embodiment of the invention, first grid structure 201A is the grid structure of nmos device, and the ion adulterated in the first shallow doped region 203A is phosphonium ion, and wherein, the implantation dosage of phosphonium ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of phosphonium ion is 5-40keV.According to a further embodiment of the invention, first grid structure 201A is the grid structure of nmos device, and the ion adulterated in the first shallow doped region 203A is arsenic ion, and wherein, the implantation dosage of arsenic ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of described arsenic ion is 1-10keV.
As shown in figure 2i, halo ion implantation is performed to form the first halo ion implanted region 204A in the Semiconductor substrate 200 of the both sides at first grid structure 201A to nucleus M.Under normal circumstances, the impurity be injected in the first halo ion implanted region 204A has the contrary type of impurity in doped region 203A shallow with first.When first grid structure 201A is the grid structure of nmos device, when the dopant type of adulterating in the first shallow doped region 203A is N-type, the dopant type of adulterating in the first halo ion implanted region 204A is P type, such as boron (B) and/or indium (In); When second grid structure 201B is the grid structure of PMOS device, when the dopant type of adulterating in the first shallow doped region 203A is P type, the dopant type of adulterating in the first halo ion implanted region 204A is N-type, such as arsenic (As) and/or phosphorus (P).Those skilled in the art is appreciated that equally, when namely nucleus comprises the grid structure of nmos device, when comprising again the grid structure of PMOS device, this step can comprise further carries out halo ion implantation to form P type halo ion implanted region and to carry out halo ion implantation to form N-type halo ion implanted region to PMOS device to nmos device respectively.Wherein, the dopant type of adulterating in N-type halo ion implanted region is N-type, such as arsenic and/or phosphorus; The dopant type of adulterating in P type halo ion implanted region is P type, such as boron and/or indium.According to one embodiment of the invention, first grid structure 201A is the grid structure of nmos device, and the ion adulterated in the second halo ion implanted region 204B is boron ion, and wherein, the implantation dosage of boron ion is 1 × 10
13-1 × 10
14cm
-2, the Implantation Energy of boron ion is 1-10keV.According to a further embodiment of the invention, first grid structure 201A is the grid structure of nmos device, and the ion adulterated in the second halo ion implanted region 204B is indium ion, and wherein, the implantation dosage of indium ion is 1 × 10
12-1 × 10
14cm
-2, the Implantation Energy of indium ion is 20-80keV.
Further, method of the present invention also comprises removal second photoresist layer.As shown in fig. 2j, the second photoresist layer 206 on the N of neighboring area is removed.
In addition, method of the present invention also comprises the step forming source electrode and drain electrode.As shown in figure 2k, in nucleus M, in the Semiconductor substrate of first grid structure 201A both sides, form source, drain electrode 207A.In neighboring area, in the Semiconductor substrate of second grid structure 201B both sides, form source, drain electrode 207B.The method that source, drain electrode 207A and 207B can adopt this area conventional makes.Exemplarily, the method can comprise respectively at first grid structure 201A and second grid structure 201B both sides formation clearance wall, and carries out ion implantation etc. to nucleus M and neighboring area N respectively.
Method of the present invention is by before the shallow Doped ions injection and halo ion implantation of nucleus, and inject at the shallow Doped ions of neighboring area and perform pre amorphous ion injection process after halo ion implantation, can at the doping profile not affecting neighboring area, while ensureing the hot electron injection reliability of peripheral devices, reduce the knot mutability of nucleus, reduce junction capacitance.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (21)
1. make a method for semiconductor device, comprising:
A) provide Semiconductor substrate, described Semiconductor substrate is formed with the first grid structure being positioned at nucleus and the second grid structure being positioned at neighboring area;
B) on described nucleus, the first photoresist layer is formed, to cover the described Semiconductor substrate and described first grid structure that are positioned at described nucleus;
C) halo ion implantation and shallow doped drain ion implantation is performed, to form the second halo ion implanted region and the second shallow doped region in the described Semiconductor substrate of the both sides of described second grid structure in described neighboring area;
D) described first photoresist layer is removed;
E) pre-amorphous ion implantation is performed, to form amorphous layer in the described Semiconductor substrate do not covered by described first grid structure and described second grid structure;
F) on described neighboring area, the second photoresist layer is formed, to cover the described Semiconductor substrate and described second grid structure that are positioned at described neighboring area;
G) halo ion implantation and shallow doped drain ion implantation is performed, to form the first halo ion implanted region and the first shallow doped region in the described Semiconductor substrate of the both sides of described first grid structure at described nucleus.
2. the method for claim 1, it is characterized in that, c) step comprises following two kinds of executive modes: first perform halo ion implantation to form described second halo ion implanted region in the described Semiconductor substrate of the both sides of described second grid structure, then perform shallow doped drain ion implantation to form described second shallow doped region in the described Semiconductor substrate of the both sides of described second grid structure; Or first perform shallow doped drain ion implantation to form described second shallow doped region in the described Semiconductor substrate of the both sides of described second grid structure, then perform halo ion implantation to form described second halo ion implanted region in the described Semiconductor substrate of the both sides of described second grid structure.
3. the method for claim 1, is characterized in that, described second grid structure is the grid structure of nmos device and/or the grid structure of PMOS device.
4. the method for claim 1, is characterized in that, described second grid structure is the grid structure of nmos device, and the ion adulterated in described second shallow doped region is phosphonium ion and/or arsenic ion.
5. method as claimed in claim 4, it is characterized in that, the implantation dosage of described phosphonium ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of described phosphonium ion is 5-40keV.
6. method as claimed in claim 4, it is characterized in that, the implantation dosage of described arsenic ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of described arsenic ion is 1-10keV.
7. the method for claim 1, is characterized in that, described second grid structure is the grid structure of nmos device, and the ion adulterated in described halo ion implanted region is boron ion and/or indium ion.
8. method as claimed in claim 7, it is characterized in that, the implantation dosage of described boron ion is 1 × 10
13-1 × 10
14cm
-2, the Implantation Energy of described boron ion is 4-12keV.
9. method as claimed in claim 7, it is characterized in that, the implantation dosage of described indium ion is 1 × 10
12-1 × 10
14cm
-2, the Implantation Energy of described indium ion is 20-80keV.
10. the method for claim 1, is characterized in that, performs in described pre-amorphous ion implantation process, and the ion of injection is germanium ion.
11. methods as claimed in claim 10, is characterized in that, the implantation dosage of described germanium ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of described germanium ion is 5-30keV.
12. the method for claim 1, it is characterized in that, g) step comprises following two kinds of executive modes: first perform halo ion implantation to form described first halo ion implanted region in the described Semiconductor substrate of the both sides of described first grid structure, then perform shallow doped drain ion implantation to form described first shallow doped region in the described Semiconductor substrate of the both sides of described first grid structure; Or first perform shallow doped drain ion implantation to form described first shallow doped region in the described Semiconductor substrate of the both sides of described first grid structure, then perform halo ion implantation to form described first halo ion implanted region in the described Semiconductor substrate of the both sides of described first grid structure.
13. the method for claim 1, is characterized in that, described first grid structure is the grid structure of nmos device and/or the grid structure of PMOS device.
14. the method for claim 1, is characterized in that, described first grid structure is the grid structure of nmos device, and the ion adulterated in described first shallow doped region is phosphonium ion and/or arsenic ion.
15. methods as claimed in claim 14, is characterized in that, the implantation dosage of described phosphonium ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of described phosphonium ion is 5-40keV.
16. methods as claimed in claim 14, is characterized in that, the implantation dosage of described arsenic ion is 1 × 10
13-1 × 10
15cm
-2, the Implantation Energy of described arsenic ion is 1-10keV.
17. the method for claim 1, is characterized in that, described first grid structure is the grid structure of nmos device, and the ion adulterated in described halo ion implanted region is boron ion and/or indium ion.
18. methods as claimed in claim 17, is characterized in that, the implantation dosage of described boron ion is 1 × 10
13-1 × 10
14cm
-2, the Implantation Energy of described boron ion is 1-10keV.
19. methods as claimed in claim 17, is characterized in that, the implantation dosage of described indium ion is 1 × 10
12-1 × 10
14cm
-2, the Implantation Energy of described indium ion is 20-80keV.
20. the method for claim 1, is characterized in that, described method also comprises the step removing described second photoresist layer.
21. methods as claimed in claim 20, is characterized in that, after removing described second photoresist layer, also comprise the step forming source electrode and drain electrode.
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| CN107634061B (en) * | 2016-07-18 | 2020-07-28 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN107706097B (en) * | 2017-09-14 | 2019-03-22 | 长鑫存储技术有限公司 | Semiconductor device structure and preparation method thereof |
| CN112928067B (en) * | 2021-01-22 | 2024-02-02 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing CMOS integrated device |
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