CN103545257A - Production method of Complementary Metal-Oxide-Semiconductor (CMOS) transistor - Google Patents

Production method of Complementary Metal-Oxide-Semiconductor (CMOS) transistor Download PDF

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Publication number
CN103545257A
CN103545257A CN201210241827.2A CN201210241827A CN103545257A CN 103545257 A CN103545257 A CN 103545257A CN 201210241827 A CN201210241827 A CN 201210241827A CN 103545257 A CN103545257 A CN 103545257A
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China
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described
grid structure
cmos
manufacture method
characterized
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CN201210241827.2A
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Chinese (zh)
Inventor
李凤莲
倪景华
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中芯国际集成电路制造(上海)有限公司
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Priority to CN201210241827.2A priority Critical patent/CN103545257A/en
Publication of CN103545257A publication Critical patent/CN103545257A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

A production method of a Complementary Metal-Oxide-Semiconductor (CMOS) transistor includes steps of providing a substrate, wherein the substrate comprises a first region corresponding to an N-channel Metal Oxide Semiconductor (NMOS) transistor and a second region corresponding to a P-channel Metal Oxide Semiconductor (PMOS) transistor; forming a first grid structure on the upper surface of the first region and forming a second grid structure on the upper surface of the second region; forming stretching stress layers on the surfaces of the first grid structure, the second grid structure and the substrate; performing ion injection on the stretching stress layer corresponding to the second region; performing annealing; etching the stretching stress layers and leading the etched stretching stress layers to serve as the side wall of the first grid structure and the side wall of the second grid structure. The production method is simple in process and low in cost, and can improve the electronic mobility of the NMOS transistors.

Description

The transistorized manufacture method of CMOS

Technical field

The present invention relates to technical field of semiconductors, in particular the transistorized manufacture method of a kind of CMOS.

Background technology

Along with the develop rapidly of semiconductor fabrication, the transistorized grid of complementary metal oxide semiconductors (CMOS) (Complementary Metal Oxide Semiconductor is called for short CMOS) becomes more and more carefully and length becomes than in the past shorter.In order to obtain better electric property, conventionally need to improve performance of semiconductor device by controlling carrier mobility, specifically can adopt strain memory technique (Stress Memorizaiton Technique, be called for short SMT) in transistorized channel region, form stable stress, thus improve the carrier mobility in raceway groove.Described stress is parallel to orientation, can be for extending stress or compression stress.Conventionally tensile stress can be so that the atomic arrangement in channel region be more loose, thereby improves the mobility of electronics, is applicable to nmos pass transistor; And compression stress makes the Atomic Arrangement in channel region tightr, thereby improve the mobility in hole, be applicable to PMOS transistor.

Prior art, when having made CMOS transistor, in order to improve the wherein channel stress of nmos pass transistor, can be taked following steps:

On CMOS transistor, form tension stress layer;

The tension stress layer upper surface corresponding at nmos transistor region forms photoresist layer;

Remove tension stress layer corresponding to PMOS transistor area;

Remove described photoresist layer;

Carry out annealing in process, the effect that makes remaining tension stress layer performance improve electron mobility;

Remove remaining tension stress layer.

But there is following defect in prior art:

1) described tension stress layer is removed again after need to first forming in batches, thereby causes technique more complicated, and production cost is higher;

2) described tension stress layer need to be formed on the transistorized grid structure of CMOS and substrate simultaneously, owing to now having formed side wall, can cause grid structure and the distance between the transistorized grid structure of PMOS of nmos pass transistor very little, thereby make the tension stress layer substrate top surface between overlies gate structure completely, there is cavity or space (Gap-fill), finally affect the electron mobility of nmos pass transistor.

Summary of the invention

The problem that the present invention solves is to provide the transistorized manufacture method of a kind of CMOS, and technique is simple, and cost is low, and can improve the electron mobility of nmos pass transistor.

For addressing the above problem, the invention provides the transistorized manufacture method of a kind of CMOS, comprising:

Substrate is provided, and described substrate comprises the first area corresponding with nmos pass transistor and second area corresponding to PMOS transistor;

At described first area upper surface, form first grid structure, and form second grid structure at described second area upper surface;

In described first grid structure, second grid structure and substrate top surface, form tension stress layer;

In tension stress layer corresponding to second area, carry out Implantation;

Carry out annealing in process;

Tension stress layer described in etching, the tension stress layer after etching is as the side wall of first grid structure and the side wall of second grid structure.

Compared with prior art, technical solution of the present invention has the following advantages: before forming side wall, form tension stress layer, thereby can guarantee that the tension stress layer forming can not produce cavity or void defects; By Implantation, eliminate the tensile stress of the tension stress layer that PMOS transistor is corresponding, and tension stress layer described in etching after annealing in process, make tension stress layer after etching as the side wall of first grid structure and the side wall of second grid structure, thereby realized the combination of strain memory technique and side wall technique, save the step of removing tension stress layer and depositing new spacer material layer, finally when improving nmos pass transistor electron mobility, can save processing step, reduce production costs.

Accompanying drawing explanation

Fig. 1 is the schematic flow sheet of the transistorized manufacture method of CMOS in the embodiment of the present invention;

Fig. 2 to Fig. 5 is the schematic diagram of the transistorized manufacture method of CMOS in the embodiment of the present invention.

Embodiment

For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.

Set forth in the following description a lot of details so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here, implement, so the present invention has not been subject to the restriction of following public specific embodiment.

Just as described in the background section, during the electron mobility of prior art nmos pass transistor in improving CMOS transistor, there is complex process, production cost is high and tension stress layer is filled the problem that has space or cavity.

For above-mentioned defect, the invention provides the transistorized manufacture method of a kind of CMOS, first in first grid structure and second grid structure, form tension stress layer, owing to now not yet forming side wall, therefore the distance between first grid structure and second grid structure is larger, and the tension stress layer of formation can not produce cavity or void defects; Then by Implantation, eliminate the tensile stress of the tension stress layer that PMOS transistor is corresponding, and the effect that makes the tension stress layer performance of nmos pass transistor improve carrier mobility by annealing in process; Then tension stress layer described in etching, make tension stress layer after etching as the side wall of first grid structure and the side wall of second grid structure, thereby pass through in conjunction with side wall technique and strain memory technique, without the step of removing tension stress layer, save again the step that deposits new spacer material layer, finally, when improving nmos pass transistor electron mobility, can save processing step, reduce production costs.

Below in conjunction with accompanying drawing, be elaborated.

Shown in figure 1, the present embodiment provides the transistorized manufacture method of a kind of CMOS, comprising:

Step S1, provides substrate, and described substrate comprises the first area corresponding with nmos pass transistor and second area corresponding to PMOS transistor;

Step S2, forms first grid structure at described first area upper surface, and forms second grid structure at described second area upper surface;

Step S3, forms tension stress layer in described first grid structure, second grid structure and substrate top surface;

Step S4 carries out Implantation in tension stress layer corresponding to second area;

Step S5, carries out annealing in process;

Step S6, tension stress layer described in etching, the tension stress layer after etching is as the side wall of first grid structure and the side wall of second grid structure.

Shown in figure 2, first substrate is provided, described substrate comprises the first area corresponding with nmos pass transistor 100 and the second area 200 corresponding with PMOS transistor, between described first area 100 and second area 200, can be isolated by fleet plough groove isolation structure (STI) 300.

Then, in described first area, 100 upper surfaces form first grid structure, and form second grid structure at described second area 200 upper surfaces.

Described first grid structure can comprise the first grid dielectric layer 110 that is positioned at first area 100 upper surfaces and the first grid electrode 120 that is positioned at first grid dielectric layer 110 upper surfaces.Particularly, the material of described first grid dielectric layer 110 can be silica, and the material of first grid electrode 120 can be polysilicon, and first grid structure is polysilicon gate; Or the material of described first grid dielectric layer 110 is high dielectric constant material, the material of described first grid electrode 120 is metal, and first grid structure is metal gate.

Described second grid structure can comprise the second gate dielectric layer 210 that is positioned at second area 200 upper surfaces and the second gate electrode 220 that is positioned at second gate dielectric layer 210 upper surfaces.Particularly, the material of described second gate dielectric layer 210 can be silica, and the material of second gate electrode 220 can be polysilicon, and second grid structure is polysilicon gate; Or the material of described second gate dielectric layer 210 is high dielectric constant material, the material of described second gate electrode 220 is metal, and second grid structure is metal gate.

In conjunction with reference to shown in figure 2; in order to protect better first grid structure and second grid structure; the present embodiment can also form at the upper surface of first grid electrode 120 the first hard mask layer 130, and forms the second hard mask layer 230 at the upper surface of second gate electrode 220.

Particularly, described the first hard mask layer 130 and the second hard mask layer 230 can be the silicon nitride layer that utilizes chemical vapor deposition method to form.

It should be noted that, the present embodiment can be save the step that forms the first hard mask layer 130 and the second hard mask layer 230, and it does not limit the scope of the invention.

In conjunction with reference to shown in figure 2, the present embodiment can also form in the side of first grid structure and the first hard mask layer 130 the first skew clearance wall (offset spacer) 140, and in the side of second grid structure and the second hard mask layer 230, forms the second skew clearance wall 240.

The material of described the first skew clearance wall 140 or the second skew clearance wall 240 can be a kind of in silica, silicon nitride, silicon oxynitride or they combine arbitrarily, for a person skilled in the art, the formation technique of skew clearance wall is known, therefore do not repeat them here.

It should be noted that, when not forming the first hard mask layer 130 and the second hard mask layer 230, described the first skew clearance wall 140 is only positioned at the side of first grid structure, and the second skew clearance wall 240 is only positioned at the side of second grid structure.

The present embodiment, after forming the first skew clearance wall 140, can carry out light dope Implantation in the substrate of the first skew clearance wall 140 and first grid structure both sides, forms the first light doping section (not shown); And after forming the second skew clearance wall 240, in the substrate of the second skew clearance wall 240 and second grid structure both sides, carry out light dope Implantation, form the second light doping section (not shown).

Described the first light doping section and the second light doping section can suppress respectively nmos pass transistor and the transistorized hot carrier injection effect of PMOS.

It should be noted that, the present embodiment can also omit the step that forms the first skew clearance wall 140, second skew clearance wall 240, the first light doping section and the second light doping section, and it does not limit the scope of the invention.

In order to improve the adhesiveness between interface, in conjunction with reference to shown in figure 3, the present embodiment can first form spacer medium layer 400 at the structure upper surface shown in Fig. 2 (being substrate top surface, the first skew clearance wall 140 upper surfaces, the first hard mask layer 130 upper surfaces, the second skew clearance wall 240 upper surfaces and the second hard mask layer 230 upper surfaces).

The material of described spacer medium layer 400 can comprise: silica.

The thickness range of described spacer medium layer 400 can comprise:

It should be noted that, the present embodiment can also be save the step that forms spacer medium layer 400, and it does not affect protection scope of the present invention.

In conjunction with reference to shown in figure 3, follow the upper surface formation tension stress layer 500 at spacer medium layer 400.

The material of described tension stress layer 500 can comprise: silicon nitride.The thickness range of described tension stress layer 500 can comprise:

Described tension stress layer 500 can adopt chemical vapor deposition (CVD) method to form, and does not repeat them here.

Owing to now also not forming the side wall of first grid structure and second grid structure, therefore, distance between first grid structure and second grid structure is larger, thereby can not produce cavity or void defects when forming spacer medium layer 400 and tension stress layer 500.

Then, at described tension stress layer 500 upper surfaces, form photoresist layer, and remove the photoresist layer corresponding with second area 200 by photoetching process.In conjunction with reference to shown in figure 4, remaining photoresist layer 600 only covers the tension stress layer corresponding with first area 100 500.

Then, carry out Implantation.Because the tension stress layer corresponding with first area 100 500 covered by photoresist layer 600, therefore, be equivalent to only in the tension stress layer 500 of second area 200 correspondences, carry out Implantation.

The ion injecting in the present embodiment can comprise: boron ion, germanium ion or its combination; Ion dose scope can comprise: 1E15/cm 3~ 1E16/cm 3; Ion implantation energy is determined by the thickness of tension stress layer 500.

By injecting the tensile stress that ion can be removed this part tension stress layer 500 in the tension stress layer 500 in second area 200 correspondences.

Then, remove described photoresist layer 600, and carry out annealing in process.

By described annealing in process, the effect that only makes the tension stress layer corresponding with first area 100 500 performances improve carrier mobility, on 500 not impacts of all the other tension stress layer.

Described annealing in process can comprise a kind of or combination in any in thermal annealing, spike annealing and laser annealing.

Particularly, the temperature range of described thermal annealing can comprise: 600 ℃ ~ 800 ℃; The temperature range of described spike annealing can comprise: 800 ℃ ~ 1100 ℃; The temperature range of described laser annealing can comprise: 1000 ℃ ~ 1300 ℃.

In conjunction with reference to shown in figure 5, adopt side wall technique, tension stress layer 500 and spacer medium layer 400 described in etching successively, make tension stress layer 510 and the common side wall as first grid structure of spacer medium layer 410, the tension stress layer 520 after etching and the common side wall as second grid structure of spacer medium layer 420 after etching.

The present embodiment is fully in conjunction with side wall technique and strain memory technique, in the tensile stress of removing the tension stress layer corresponding with second area 200, and after the tensile stress of the tension stress layer that performance is corresponding with first area 100, material layer using tension stress layer now as side wall, thereby both without removing tension stress layer, save again and deposited new spacer material layer, finally, when improving nmos pass transistor electron mobility, realized the object of saving technique, reducing costs.

The present embodiment, after forming described side wall, can also carry out heavy doping ion injection, in the substrate of first grid structure and corresponding side wall both sides, carries out heavy doping ion injection, forms the first source/drain region (not shown); And in the substrate of second grid structure and corresponding side wall both sides, carry out heavy doping ion injection, form the second source/drain region (not shown), it is known for those skilled in the art, does not repeat them here.

Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.

Claims (18)

1. the transistorized manufacture method of CMOS, is characterized in that, comprising:
Substrate is provided, and described substrate comprises the first area corresponding with nmos pass transistor and second area corresponding to PMOS transistor;
At described first area upper surface, form first grid structure, and form second grid structure at described second area upper surface;
In described first grid structure, second grid structure and substrate top surface, form tension stress layer;
In tension stress layer corresponding to second area, carry out Implantation;
Carry out annealing in process;
Tension stress layer described in etching, the tension stress layer after etching is as the side wall of first grid structure and the side wall of second grid structure.
2. the transistorized manufacture method of CMOS as claimed in claim 1, is characterized in that, also comprises: before forming described tension stress layer, in described first grid structure, second grid structure and substrate top surface, form spacer medium layer.
3. the transistorized manufacture method of CMOS as claimed in claim 2, is characterized in that, the material of described spacer medium layer comprises: silica.
4. the transistorized manufacture method of CMOS as claimed in claim 2, is characterized in that, the thickness range of described spacer medium layer comprises:
5. the transistorized manufacture method of CMOS as claimed in claim 1, is characterized in that, the material of described tension stress layer comprises: silicon nitride.
6. the transistorized manufacture method of CMOS as claimed in claim 1, is characterized in that, the thickness range of described tension stress layer comprises:
7. the transistorized manufacture method of CMOS as claimed in claim 1, is characterized in that, described annealing in process comprises a kind of or combination in any in thermal annealing, spike annealing and laser annealing.
8. the transistorized manufacture method of CMOS as claimed in claim 7, is characterized in that, the temperature range of described thermal annealing comprises: 600 ℃ ~ 800 ℃.
9. the transistorized manufacture method of CMOS as claimed in claim 7, is characterized in that, the temperature range of described spike annealing comprises: 800 ℃ ~ 1100 ℃.
10. the transistorized manufacture method of CMOS as claimed in claim 7, is characterized in that, the temperature range of described laser annealing comprises: 1000 ℃ ~ 1300 ℃.
The transistorized manufacture method of 11. CMOS as claimed in claim 1, it is characterized in that, also comprise: before forming described tension stress layer, in the side of described first grid structure, form the first skew clearance wall, and in the side of described second grid structure, form the second skew clearance wall.
The transistorized manufacture method of 12. CMOS as claimed in claim 11, it is characterized in that, also comprise: after forming the first skew clearance wall, in the substrate of the first skew clearance wall and first grid structure both sides, carry out light dope Implantation, form the first light doping section; And after forming the second skew clearance wall, in the substrate of the second skew clearance wall and second grid structure both sides, carry out light dope Implantation, form the second light doping section.
The transistorized manufacture method of 13. CMOS as claimed in claim 1, is characterized in that, also comprises: before forming described tension stress layer, at the upper surface of described first grid structure, form the first hard mask layer; And the upper surface in described second grid structure forms the second hard mask layer.
The transistorized manufacture method of 14. CMOS as claimed in claim 1, is characterized in that, described first grid structure or described second grid structure comprise gate dielectric layer and gate electrode from bottom to up successively.
The transistorized manufacture method of 15. CMOS as claimed in claim 14, is characterized in that, the material of described gate dielectric layer is silica, and the material of described gate electrode is polysilicon; Or the material of described gate dielectric layer is high dielectric constant material, the material of described gate electrode is metal.
The transistorized manufacture method of 16. CMOS as claimed in claim 1, is characterized in that, the ion injecting in tension stress layer corresponding to second area comprises: boron ion or germanium ion.
The transistorized manufacture method of 17. CMOS as claimed in claim 16, is characterized in that, the ion dose scope of injecting in tension stress layer corresponding to second area comprises: 1E15/cm3 ~ 1E16/cm3.
The transistorized manufacture method of 18. CMOS as claimed in claim 1, it is characterized in that, also comprise: after forming described side wall, carry out heavy doping ion injection, in the substrate of first grid structure and corresponding side wall both sides, carry out heavy doping ion injection, form the first source/drain region; And in the substrate of second grid structure and corresponding side wall both sides, carry out heavy doping ion injection, form the second source/drain region.
CN201210241827.2A 2012-07-12 2012-07-12 Production method of Complementary Metal-Oxide-Semiconductor (CMOS) transistor CN103545257A (en)

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Cited By (1)

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CN105575902A (en) * 2014-10-17 2016-05-11 中芯国际集成电路制造(上海)有限公司 Semiconductor device, manufacture method thereof and electronic device

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Application publication date: 20140129