CN103531542B - Reduce the cmos device manufacture method of Negative Bias Temperature Instability - Google Patents
Reduce the cmos device manufacture method of Negative Bias Temperature Instability Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 230000008021 deposition Effects 0.000 claims abstract description 4
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 230000009467 reduction Effects 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910015900 BF3 Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical group FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- DYCJFJRCWPVDHY-LSCFUAHRSA-N NBMPR Chemical compound O[C@@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C2=NC=NC(SCC=3C=CC(=CC=3)[N+]([O-])=O)=C2N=C1 DYCJFJRCWPVDHY-LSCFUAHRSA-N 0.000 description 24
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- 230000000694 effects Effects 0.000 description 11
- 230000008569 process Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 5
- YZCKVEUIGOORGS-IGMARMGPSA-N Protium Chemical compound [1H] YZCKVEUIGOORGS-IGMARMGPSA-N 0.000 description 5
- 241000720974 Protium Species 0.000 description 5
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 5
- 230000007850 degeneration Effects 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 230000005527 interface trap Effects 0.000 description 4
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 description 3
- 229910052805 deuterium Inorganic materials 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000005445 isotope effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Reduce a cmos device manufacture method for Negative Bias Temperature Instability, comprising: first step, carry out trap in the substrate and inject formation P type trap and N-type trap; Second step, makes grid oxic horizon at substrate surface; Third step, carries out the deposit of grid layer on grid oxic horizon surface; 4th step, carries out photoetching to grid layer and forms PMOS grid to be formed on P type trap, N-type trap is formed NMOS grid; 5th step, makes grid curb wall one respectively at the side of PMOS grid and NMOS grid; 6th step, carries out light dope and is infused in P type trap and forms PMOS lightly-doped source drain structure, and in N-type trap, form NMOS lightly-doped source drain structure; 7th step, at device surface deposition silicon nitride film; 8th step, utilizes UV light to irradiate silicon chip; 9th step, makes at grid curb wall one side and forms side wall two; Tenth step, carries out source and drain and injects formation, thus in P type trap, form PMOS source drain electrode, forms NMOS source-drain electrode in N-type trap.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of cmos device manufacture method reducing Negative Bias Temperature Instability (NBTI:NegativeBiasTemperatureInstability).
Background technology
Along with developing rapidly of very large scale integration technology, the size of MOSFET element is in continuous reduction.Due to the sharply reduction of mosfet transistor size, it is even thinner that the thickness of gate oxide is decreased to 2nm.While the scaled size of MOS device, operating voltage is correspondingly equal proportion reduction not, and this makes the raceway groove electric field of MOS device and electric field across oxide significantly increase, and the degeneration that NBTI effect causes is day by day remarkable.NBTI, i.e. Negative Bias Temperature Instability, be often referred to PMOS and show to obtain device performance degeneration under high temperature, the effect of high field minus gate voltage.Electrical temperature in the scope of 80-250 degree, as shown in Figure 1.The off-state current (Ioff) that NBTI degeneration shows as device increases, and threshold voltage (Vth) negative sense drifts about, and mutual conductance (Gm) and leakage current (Ids) reduce.In addition, in order to improve transistor performance, reduce the leakage current of gate oxide, in gate oxide, introduce atom N has become a kind of technological standards, but being introduced in of atom N exacerbates device NBTI to a certain extent and degenerate.
In the research to NBTI degradation mechanism, generally believe it is SiO
2the dangling bonds of Si that/Si interface occurs cause.In NBTI stress path, Fixed oxide charge and the interface trap (Si3 Ξ Si) produced because surface voids participates in are the main causes causing NBTI effect.And Si-H key all plays crucial effect in the NBTI effect caused at fixed charge and interface trap.Under NBTI stress condition, hole can make Si-H key decompose under the effect of electric field, thus forms interface trap, as shown in Figure 2 A and 2 B, causes the degeneration of device.Reaction equation is as follows:
Interface falls into spells Si
3≡ SiH → Si
3≡ Si ten H
0
Si
3≡ SiH ten H+ → Si
3→ Si ten H
2
Oxide trapped charge O
3→ SiH → O
3≡ Si ten H
0
O
3three S's iH ten H+ → O
3≡ Si ten H
2
But, in cmos device gate oxide H as fixed charge and Si in interface trap main become key material, be the most common and inevitable impurity, and play a major role in NBTI course of reaction.In present cmos process flow, take related measure to suppress NBTI effect.Such as at SiO
2/ Si interface, by the defect passivation of deuterium (D), has great advantage in raising device reliability.Because according to kinetic isotope effect, break the Si-D key that formed with deuterium more difficult than the Si-H key formed with hydrogen.But realize in process also there is important problem in this passivation.On existing production line, normally carried out the deuterate at interface by the deuterium annealing after through hole formation, but the deuterate at execution interface, production line posterior segment.Another method is, reduces SiO by the introducing reducing H in device making technics
2the Si-H number of keys of/Si interface also can significantly improve the NBTI performance of device.But due in the manufacturing process of device, there is hydrogen in such as film deposit, etching, ion implantation and cleaning etc. in much technique, these hydrogen, under the driving of heat budget, can be diffused into SiO
2/ Si interface, is combined with Si dangling bonds and forms Si-H key, thus exacerbate NBTI effect
Therefore, how to provide a kind of process that can reduce to introduce in MOS device manufacturing process hydrogen, thus reduce SiO
2the number of/Si interface Si-H key, and then can improve NBTI performance, has become an important problem.
Summary of the invention
Technical problem to be solved by this invention is for there is above-mentioned defect in prior art, provides a kind of cmos device manufacture method that can reduce Negative Bias Temperature Instability.
In order to realize above-mentioned technical purpose, according to the present invention, provide a kind of cmos device manufacture method reducing Negative Bias Temperature Instability, it comprises:
First step, carries out trap in the substrate and injects formation P type trap and N-type trap;
Second step, makes grid oxic horizon at substrate surface;
Third step, carries out the deposit of grid layer on grid oxic horizon surface;
4th step, carries out photoetching to grid layer and forms NMOS grid to be formed on P type trap, N-type trap is formed PMOS grid;
5th step, makes grid curb wall one respectively at the side of PMOS grid and NMOS grid;
6th step, carries out light dope and is infused in P type trap and forms NMOS lightly-doped source drain structure, and in N-type trap, form PMOS lightly-doped source drain structure;
7th step, at device surface deposition silicon nitride film;
8th step, utilizes UV light to irradiate silicon chip;
9th step, makes at grid curb wall one side and forms side wall two;
Tenth step, carries out source and drain and injects formation, thus form NMOS source-drain electrode in P type trap, forms PMOS source drain electrode in N-type trap.
Preferably, the cmos device manufacture method of described reduction Negative Bias Temperature Instability also comprises: the 11 step, for making pre-metal dielectric, through hole, metal plug and metal level.
Preferably, in a first step, form N trap by phosphorus doping, form P trap by B doping.
Preferably, in third step, the material of the grid layer of deposit is polysilicon.
Preferably, in the 5th step, the formation of grid curb wall one comprises the oxidation of polysilicon gate and the deposit of SiN.
Preferably, in the 6th step, light dope impurity is boron fluoride.
Preferably, utilize UV light to be 450-480 DEG C to the temperature that silicon chip irradiates in the 8th step, irradiation time is 100-150S.
Preferably, in the 9th step, the formation of side wall two comprises the deposit of oxide, the deposit of SiN and the etching of SiN.
Preferably, in the tenth step, inject by the doping of P type the source-drain electrode forming P type, described P type is doped to boron doping.
This method provides a kind of a kind of new technique of semiconductor integrated circuit technique in order to improve the NBTI effect of MOS device.By in traditional semiconductor MOS device fabrication processes, before dry etching forms second silicon nitride spacer and after silicon nitride film deposit, with UV light, wafer is irradiated to some the residual hydrogen atoms removed in silicon nitride film, hydrogen molecule and steam, the protium in the silicon nitride spacer avoided the formation of is diffused into grid oxic horizon lower surface SiO
2/ Si interface is combined with the Si dangling bonds of interface, reaches and reduces SiO
2/ Si interface Si-H number of keys, thus improve the NBTI performance in MOS device, and then improve cmos device performance.Compared with improving technique with the NBTI of traditional technique, this technique have technique simple, be easy to the features such as realization.
Accompanying drawing explanation
By reference to the accompanying drawings, and by reference to detailed description below, will more easily there is more complete understanding to the present invention and more easily understand its adjoint advantage and feature, wherein:
Fig. 1 schematically shows NBTI effect.
Fig. 2 A and Fig. 2 B schematically shows Si/SiO
2the one-tenth bond structure at interface.
Fig. 3 schematically shows the flow chart of the cmos device manufacture method reducing Negative Bias Temperature Instability according to the preferred embodiment of the invention.
Fig. 4-Figure 14 schematically shows the device sectional view of each step of the cmos device manufacture method reducing Negative Bias Temperature Instability according to the preferred embodiment of the invention.
It should be noted that, accompanying drawing is for illustration of the present invention, and unrestricted the present invention.Note, represent that the accompanying drawing of structure may not be draw in proportion.Further, in accompanying drawing, identical or similar element indicates identical or similar label.
Embodiment
In order to make content of the present invention clearly with understandable, below in conjunction with specific embodiments and the drawings, content of the present invention is described in detail.
Fig. 3 schematically shows the flow chart of the cmos device manufacture method reducing Negative Bias Temperature Instability according to the preferred embodiment of the invention.
As shown in Figure 3, the cmos device manufacture method reducing Negative Bias Temperature Instability according to the preferred embodiment of the invention comprises:
First carry out first step S0, carry out trap in the substrate and inject formation P type trap 100 and N-type trap 200.In the present embodiment, N trap 200 is formed by phosphorus doping; P trap 100 is formed, as shown in Figure 4 by B doping.
Then carry out second step S1, make grid oxic horizon 300 at substrate surface, as shown in Figure 5.
Then continue third step S2, carry out the deposit of grid layer 400 on grid oxic horizon 300 surface, such as, the material of the grid layer 400 of deposit is polysilicon, as shown in Figure 6.
Then continue the 4th step S3, photoetching is carried out to grid layer 400 and forms NMOS grid 401 to be formed on P type trap 100, N-type trap 200 forms PMOS grid 402, as shown in Figure 7.
Then continue the 5th step S4, make grid curb wall one 11,21 respectively at the side of NMOS grid 401 and PMOS grid 402; Such as, the formation of grid curb wall one 11,12 comprises the oxidation of polysilicon gate and the deposit of SiN, as shown in Figure 8.
Then continue the 6th step S5, carry out light dope and be infused in P type trap 100 and form NMOS lightly-doped source drain structure 12 and 13, and in N-type trap 200, form PMOS lightly-doped source drain structure 22 and 23, as shown in Figure 9.In the present embodiment, described light dope impurity is boron fluoride.
Then the 7th step S6 is continued, at device surface deposition silicon nitride film 500, as shown in Figure 10
Then continue the 8th step S7, utilize UV light (ultraviolet light) to irradiate silicon chip, as shown in figure 11.In this example, by the UV light irradiate wafer of proper temperature and appropriate time in order to remove some hydrogen atoms, hydrogen molecule and steam residual in silicon nitride film growth course.Wherein the appropraite condition of UV light is extremely important, and preferably, temperature 450-480 DEG C, the time, 100-150S was proper.Too low temperature is not enough to drive protium and steam: too high temperature is again than the activation and the diffusion that are easier to the ion that trap injects and light dope source and drain is injected affected in previous process.The UV illumination of above-mentioned condition is penetrated and effectively can be removed hydrogen atom in silicon nitride film and hydrogen molecule, avoids silicon nitride spacer to form rear protium and is diffused into grid oxic horizon lower surface SiO
2/ Si interface is combined with the Si dangling bonds of interface, reaches and reduces SiO
2/ Si interface Si-H number of keys, thus improve the NBTI performance in MOS device, and then improve cmos device performance.
Then continue the 9th step S8, make at grid curb wall one 11,21 side and form side wall 2 14,14, as shown in figure 12.Such as, the formation of side wall two comprises the deposit of oxide, the deposit of SiN and the etching of SiN.
Then continue the tenth step S9, carry out source and drain and inject formation, thus form NMOS source-drain electrode 15,16 in P type trap 100, in N-type trap 200, form PMOS source drain electrode 25,26, as shown in figure 13.In the present embodiment, inject by the doping of P type the source-drain electrode forming P type, described P type is doped to boron doping.
Then the 11 step S10 be can continue, finally pre-metal dielectric 600, through hole 700, metal plug and metal level (not shown) etc. made, as shown in figure 14.
In the metal-oxide-semiconductor manufacture method of above-mentioned improved NBTI, the light-struck temperature and time of UV in the 8th step S7 is extremely important: general temperature 450-480 DEG C, the time, 100-150S was proper.This condition both there will not be can not drive away protium and steam, also there will not be too high temperature can affect activation and the diffusion of the ion that trap (Well) injects and light dope source and drain (LDD) is injected in previous process.
This method provides a kind of a kind of new technique of semiconductor integrated circuit technique in order to improve the NBTI effect of MOS device.By in traditional semiconductor MOS device fabrication processes, before dry etching forms second silicon nitride spacer and after silicon nitride film deposit, with UV light, wafer is irradiated to some the residual hydrogen atoms removed in silicon nitride film, hydrogen molecule and steam, the protium in the silicon nitride spacer avoided the formation of is diffused into grid oxic horizon lower surface SiO
2/ Si interface is combined with the Si dangling bonds of interface, reaches and reduces SiO
2/si interface Si-H number of keys, thus improve the NBTI performance in MOS device, and then improve cmos device performance.Compared with improving technique with the NBTI of traditional technique, this technique have technique simple, be easy to the features such as realization.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the term " first " in specification, " second ", " the 3rd " etc. describe only for distinguishing each assembly, element, step etc. in specification, instead of for representing logical relation between each assembly, element, step or ordinal relation etc.
Be understandable that, although the present invention with preferred embodiment disclose as above, but above-described embodiment and be not used to limit the present invention.For any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the technology contents of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (8)
1. reduce a cmos device manufacture method for Negative Bias Temperature Instability, it is characterized in that comprising:
First step, carries out trap in the substrate and injects formation P type trap and N-type trap;
Second step, makes grid oxic horizon at substrate surface;
Third step, carries out the deposit of grid layer on grid oxic horizon surface;
4th step, carries out photoetching to grid layer and forms NMOS grid to be formed on P type trap, N-type trap is formed PMOS grid;
5th step, makes grid curb wall one respectively at the side of PMOS grid and NMOS grid;
6th step, carries out light dope and is infused in P type trap and forms NMOS lightly-doped source drain structure, and in N-type trap, form PMOS lightly-doped source drain structure;
7th step, at device surface deposition silicon nitride film;
8th step, utilizes UV light to irradiate silicon chip, and utilize UV light to be 450-480 DEG C to the temperature that silicon chip irradiates, irradiation time is 100-150S;
9th step, makes at grid curb wall one side and forms side wall two;
Tenth step, carries out source and drain and injects formation, thus form NMOS source-drain electrode in P type trap, forms PMOS source drain electrode in N-type trap.
2. the cmos device manufacture method of reduction Negative Bias Temperature Instability according to claim 1, characterized by further comprising: the 11 step, for making pre-metal dielectric, through hole, metal plug and metal level.
3. the cmos device manufacture method of reduction Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in a first step, forms N trap by phosphorus doping, forms P trap by B doping.
4. the cmos device manufacture method of reduction Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in third step, the material of the grid layer of deposit is polysilicon.
5. the cmos device manufacture method of reduction Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in the 5th step, the formation of grid curb wall one comprises the oxidation of polysilicon gate and the deposit of SiN.
6. the cmos device manufacture method of reduction Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in the 6th step, light dope impurity is boron fluoride.
7. the cmos device manufacture method of reduction Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in the 9th step, the formation of side wall two comprises the deposit of oxide, the deposit of SiN and the etching of SiN.
8. the cmos device manufacture method of reduction Negative Bias Temperature Instability according to claim 1 and 2, is characterized in that, in the tenth step, inject by the doping of P type the source-drain electrode forming P type, described P type is doped to boron doping.
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| CN103972109A (en) * | 2014-05-21 | 2014-08-06 | 上海华力微电子有限公司 | Method for manufacturing MOS device capable of reducing negative bias temperature instability |
| CN105895634A (en) * | 2015-01-26 | 2016-08-24 | 中芯国际集成电路制造(上海)有限公司 | Cmos device and manufacturing method thereof |
| CN107039299B (en) * | 2016-11-10 | 2019-10-18 | 中国电子产品可靠性与环境试验研究所 | Metal-oxide-semiconductor parameter degradation circuit and metal-oxide-semiconductor parameter degradation early warning circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1405866A (en) * | 2001-03-01 | 2003-03-26 | 海力士半导体有限公司 | Transistor with super-short grating characteristic and storage device unit and their producing method |
| CN102412201A (en) * | 2011-05-13 | 2012-04-11 | 上海华力微电子有限公司 | Method for improving tensile stress of silicon nitride film in semiconductor devices |
| CN102709186A (en) * | 2012-01-12 | 2012-10-03 | 上海华力微电子有限公司 | Method for reducing negative bias temperature instability effect of device and manufacturing method of device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1405866A (en) * | 2001-03-01 | 2003-03-26 | 海力士半导体有限公司 | Transistor with super-short grating characteristic and storage device unit and their producing method |
| CN102412201A (en) * | 2011-05-13 | 2012-04-11 | 上海华力微电子有限公司 | Method for improving tensile stress of silicon nitride film in semiconductor devices |
| CN102709186A (en) * | 2012-01-12 | 2012-10-03 | 上海华力微电子有限公司 | Method for reducing negative bias temperature instability effect of device and manufacturing method of device |
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