JP2001250945A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which suppresses an implanted p-type impurity for forming a pocket layer from diffusing in LDD layer ends and the LDD layer interior. SOLUTION: The semiconductor device having an LDD structure comprises a first diffused layer 4c formed with an n-type impurity at a low concentration, second diffused layers 4e, 5e formed with an n-type impurity at a high concentration, and pocket implanted layers 4d, 5d on a p-type semiconductor substrate 1. After forming gate electrodes 3, nitrogen ion implantation and heat treatment are made to introduce nitrogen, thereby forming nitride layers 4b, 5b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, elements have been rapidly miniaturized in order to achieve high integration and high speed of LSI (Large Scale Integrated Circuit). In a field-effect semiconductor device such as a field-effect transistor (hereinafter, referred to as a MOSFET) composed of a metal-oxide film-semiconductor, a leak current increases with miniaturization of an element, and deterioration of element characteristics due to hot carriers increases. ing.

In order to suppress these, LDD (Lig)
htly Doped Drain) layer or source / drain extension layer (hereinafter referred to as LDD layer).
A structure called is used. Further, in order to suppress a leak current, a structure called a pocket injection layer or a halo injection layer (hereinafter, referred to as a pocket injection layer) is used below the LDD layer.

FIG. 3 is a schematic sectional view showing the structure of a conventional N-type MOSFET using an LDD layer and a pocket injection layer.

A MOSFET having such a structure is disclosed in, for example, IEDM Tech. Dig. , 1990, pp.
215-218.

An N-type MOSFET will be described with reference to FIG. As shown in FIG. 3, a p-type single crystal silicon substrate 1
A gate oxide film 2 and a gate electrode 3 made of polysilicon are formed, and a source region 4 and a drain region 5 are formed at predetermined intervals. The region of the silicon substrate 1 between the source region 4 and the drain region 5 becomes the channel region 6. The source region 4, n ^- a layer LD
A D layer 4a, a pocket injection layer 4b made of ap ⁻ layer, and n ⁺
It is composed of a high concentration diffusion layer 4c composed of a layer. Drain region 5, and the LDD layer 5a composed of the n- layer, p ^- the pocket implantation layer 5b consisting of a layer composed of a high-concentration diffusion layer 5c made of n ⁺ layer. Note that a side wall 3a for forming the high concentration diffusion layers 4c, 5c is provided on the side wall of the gate electrode 3.

In the MOSFET of FIG. 3, when a drain voltage is applied between the drain region 5 and the source region 4, the LDD layer 5a suppresses a sharp increase in the electric field generated near the end of the drain region 5. . In particular, the LDD layer 5
By making the impurity distribution at the end of a gentle, it is possible to suppress an increase in the electric field. Thereby, suppression of hot carrier generation is realized.

The pocket injection layer 5b allows the LDD to be formed.
The spread of the layer 5a and the high concentration diffusion layer 5c is suppressed. Thereby, when a drain voltage is applied between the drain region 5 and the source region 4, the expansion of a depletion layer formed by the drain voltage is suppressed, so that a leak current can be suppressed.

[0009]

In the above-described conventional manufacturing method, the p-type impurity implanted to form the pocket injection layer diffuses into the channel region near the end of the LDD layer. As a result, the impurity distribution at the end of the LDD layer becomes steep. Therefore, there is a problem that the effect of suppressing the generation of hot carriers by forming the LDD layer cannot be sufficiently utilized.

In the above-described conventional manufacturing method, the p-type impurity implanted to form the pocket injection layer is L-type.
Since the impurity also diffuses into the DD layer, it overlaps with the n-type impurity of the LDD layer, so that the resistance of the LDD layer increases and the current flowing between the source and the drain decreases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and suppresses diffusion of a p-type impurity implanted for forming a pocket injection layer into an end portion of an LDD layer and inside the LDD layer. It is an object to provide a semiconductor device and a method for manufacturing the same.

[0012]

According to the present invention, a semiconductor device or a semiconductor layer of one conductivity type has a first diffusion layer of low concentration formed of impurities of another conductivity type and a semiconductor layer or a semiconductor layer of another conductivity type. And a high-concentration second diffusion layer, wherein a nitride layer in which nitrogen is introduced is formed on a surface of the semiconductor substrate or the semiconductor layer.

It is preferable that the nitride layer is provided so as to protrude from the low-concentration first diffusion layer side to the channel side.

Further, according to the present invention, in the above structure, the p-type semiconductor substrate or the semiconductor layer may be further provided with a pocket injection layer formed of a p-type impurity.

Further, according to a manufacturing method of the present invention, there is provided the method of manufacturing a semiconductor device according to any one of the above, wherein after forming the gate electrode, nitrogen is introduced by nitrogen ion implantation and heat treatment to form the nitride layer. It is characterized by doing.

The manufacturing method according to the present invention is the method for manufacturing a semiconductor device according to any one of the above, wherein after forming the gate electrode, a nitriding treatment is performed by heat treatment in an atmosphere containing nitrogen. Is formed.

According to the above-described structure, by forming the nitride layer into which nitrogen is introduced on the surface of the substrate or the semiconductor layer, one conductivity type (p-type) impurities and impurities implanted to form the pocket injection layer are formed. Since one conductivity type (p-type) impurity in the substrate is less likely to diffuse near the boundary between the low concentration first diffusion layer and the channel region, the impurity at the end of the low concentration first diffusion layer is sharp. Never be. This allows
A sufficient effect of suppressing the generation of hot carriers by the low concentration first diffusion layer can be obtained.

Further, by forming a nitride layer into which nitrogen is introduced on the surface of the substrate or the semiconductor layer, one conductivity type (p-type) impurities implanted to form a pocket injection layer and one conductivity type in the substrate are formed. Since the type (p-type) impurity is less likely to diffuse into the low concentration first diffusion layer, an increase in resistance of the low concentration first diffusion layer can be suppressed.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. The same parts as those of the conventional example are denoted by the same reference numerals.

(First Embodiment) FIG. 1 is a sectional view showing a method of manufacturing a MOSFET according to a first embodiment of the present invention for each process.

First, as shown in FIG. 1A, a 2-10 nm-thick gate oxide film 2 made of silicon dioxide (SiO ₂ ) is formed on a p-type silicon single crystal substrate 1 by thermal oxidation. Thereafter, a film thickness 1 of doped polysilicon doped with an impurity such as P (phosphorus) by a CVD method.
A gate electrode 3 having a thickness of 00 to 200 nm is formed. The gate length of this gate electrode is 0.1 to 0.5 μm.

Next, nitrogen implantation layers 4a and 5a are formed on the silicon substrate 1 on both sides of the gate electrode 3 by ion implantation. Nitrogen implantation energy is 0.1keV ~
50 keV, and the dose amount is 1 × 10 ¹¹ to 1 × 10 ^16.
cm ^-2 .

Further, the nitrogen injection layers 4a, 5a
It is preferable that the LDD layers 4c and 5c shown in FIG. 3C protrude toward the channel region 6 side, and nitrogen is injected in an oblique direction. The nitrogen injection from the oblique direction must be performed by rotating the wafer so that the nitrogen injection layers 4a and 5a project in the channel region side equally, and the wafer is rotated 90 degrees four times. And so on.

Next, as shown in FIG. 1 (b), by oxidizing the silicon substrate 1, the nitrogen implanted in the step of FIG. 1 (a) is diffused at the interface between the oxide film and the substrate to form a nitride layer. 4
b and 5b are formed. The oxide film thickness is 1 to 20 nm. Note that the same effect can be obtained only by performing the heat treatment without oxidizing the silicon substrate. In this case, heat treatment may be performed at 800 ° C. for one hour in a nitrogen atmosphere.

Next, as shown in FIG.
N on the silicon substrate 1 on both sides of the pole 3 ^-LDD consisting of layers
As (arsenic) is used to form layers 4c and 5c in a pocket.
B (boron) to form the injection layers 4d and 5d
Each is ion-implanted. Between the LDD layers 4c and 5c
The region becomes the channel region 6.

The implantation energy of As is 1 keV to 20
0 keV, and the dose amount is 1 × 10 ¹² to 1 × 10 ¹⁶ c
m- ² . Instead of As, P (phosphorus) and Sb (antimony) can be used.

The implantation energy of B is 0.1 ke
V to 50 keV, and are selected so as to be implanted below the LDD layers 4c and 5c. Dose amount is 1 × 10 ¹¹ to 1 × 10
¹⁵ cm ^-2 . Instead of B, In (indium) can be used.

Thereafter, as shown in FIG. 1 (d), an SiO ₂ film is deposited and formed on the entire surface of the silicon substrate 1 by a CVD method having a thickness of 50 to 300 nm, and etching is performed to thereby form both sides of the gate electrode 3. Side wall spacer 3a
To form Further, high-concentration diffusion layers 4e and 5e made of n ⁺ layers are formed in the source region 4 and the drain region 5 by As or P ion implantation.

The step of forming the sidewall spacer 3a,
In a process for electrically activating impurities implanted in the high concentration diffusion layers 4e and 5e, heat treatment is involved, so that B (boron) implanted to form the pocket injection layers 4d and 5d is removed. Diffusion occurs.

The diffusion generated in this step is mainly governed by the phenomenon of excessively accelerated diffusion. The excessively accelerated diffusion in this case is L
As a result of excessive generation of interstitial silicon atoms in the silicon substrate due to ion implantation performed to form the DD layers 4b and 5b, the pocket injection layers 4d and 5d, and the high concentration diffusion layers 4e and 5e, B This is a phenomenon in which silicon atoms diffuse in pairs. The pair of B and the interstitial silicon atom is
It diffuses from the pocket injection layers 4d and 5d into the silicon and also diffuses toward the substrate surface. When the pair of B and the interstitial silicon atoms reach the vicinity of the substrate surface, the interstitial silicon atoms bond to the substrate surface, and B separates from the interstitial silicon atoms near the substrate surface and enters the silicon lattice position. Activate. Thereby, the impurity concentration near the substrate surface increases.

In the excessively enhanced diffusion, lamp annealing is performed before the step of forming the sidewall spacers 3a, and a step of electrically activating impurities implanted in the high concentration diffusion layers 4e and 5e is performed by lamp annealing. However, it is known that the effect can be considerably suppressed, but it is not completely eliminated.

The rate at which interstitial silicon atoms bond with substrate surface atoms varies depending on the state of the substrate surface. Comparing the case where the silicon oxide film is formed on the substrate surface and the case where the nitride layer is formed, the interstitial silicon atoms and the substrate surface atoms are better when the nitride layer is formed. It is known that the bonding speed is slow. Fifty-eight
Proceedings of the Annual Meeting of Japan Society of Applied Physics p. 716, Lecture No. 2p-B-13 indicates that the pile-up amount of B (boron) changes depending on the state of the substrate surface.

In this embodiment, since the nitride layer is provided on a part of the substrate surface, the pair of interstitial silicon atoms and B is less likely to diffuse toward a region where the nitride layer exists.

After the sidewall spacers 3a and the high-concentration diffusion layers 4e and 5e have been formed in this manner, aluminum or the like is subsequently applied to the source region 4 and the drain region 5 according to a normal MOSFET manufacturing method. An electrode is formed by using this to manufacture a MOSFET.

(Embodiment 2) Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional view showing a method of manufacturing a MOSFET according to the second embodiment of the present invention for each step.

First, as shown in FIG.
As in (a), a gate oxide film 2 and a gate electrode 3 are sequentially formed on a p-type silicon single crystal substrate 1.

Next, as shown in FIG.
Nitriding by a heat treatment in a soft atmosphere
b and 5b are formed. NO or NO
Is N _TwoThe nitridation and oxidation treatment may be performed in an O atmosphere. There
Is obtained by oxidizing so that the film thickness becomes 1 to 20 nm,
O, N_TwoO, NH_ThreeHeat treatment in a nitriding atmosphere such as
No.

Next, as shown in FIG.
Similarly to (c), the LDD layers 4c and 5c and the pocket injection layers 4d and 5d are formed.

Thereafter, as shown in FIG.
Similarly to (d), a side wall spacer 3a and high concentration diffusion layers 4e and 5e are formed. At this time, as in the first embodiment, since a nitride layer is provided on a part of the substrate surface, the pair of interstitial silicon atoms and B (boron)
Diffusion towards certain regions of the nitride layer is reduced.

Further, electrodes are formed in the source region 4 and the drain region 5 using aluminum or the like to form a MOSFET.
Is prepared.

In the above embodiment, B (boron) for forming the pocket injection layer is formed in the channel region 6.
According to the present invention, the diffusion of p-type impurities contained in the p-type substrate to the vicinity of the channel region is suppressed. Therefore, even if the present invention is applied to the MOSFET having the LDD structure without the pocket injection layer, the effect can be obtained.

Further, in the above-described embodiment, N-type is used, where one conductivity type is p-type and the other conductivity type is n-type.
Although the description has been given of the channel type MOS, the same effect can be expected in the opposite case, that is, a P-channel type MOS in the case of n-type as one conductivity type and p-type as another conductivity type.

[0043]

As described above, by introducing nitrogen to the substrate surface, one conductivity type (p-type) impurity and one conductivity type (p-type) in the substrate are injected to form the pocket injection layer. Since the (p-type) impurity is less likely to diffuse near the boundary between the low-concentration first diffusion layer and the channel region, the impurity at the end of the low-concentration first diffusion layer does not become steep. Thereby, a sufficient effect of suppressing the generation of hot carriers by the LDD layer can be obtained.

Further, by introducing nitrogen into the substrate surface, one conductivity type (p-type) impurity and one conductivity type (p-type) in the substrate are injected to form the pocket injection layer.
Since the diffusion of impurities into the low concentration first diffusion layer is reduced, an increase in resistance of the low concentration first diffusion layer can be suppressed.

[Brief description of the drawings]

FIG. 1 shows a MOSFE according to a first embodiment of the present invention;
It is sectional drawing which shows the manufacturing method of T for every process.

FIG. 2 shows a MOSFET according to the first embodiment of the present invention;
It is sectional drawing which shows the manufacturing method of T for every process.

FIG. 3 is a schematic cross-sectional view showing a structure of a conventional N-type MOSFET using an LDD layer and a pocket injection layer.

[Explanation of symbols]

 Reference Signs List 1 p-type silicon single crystal substrate 2 gate oxide film 3 gate electrode 4 source region 5 drain region 4a, 5a nitrogen injection layer 4b, 5b nitride layer 4c, 5c LDD layer 4d, 5d pocket injection layer 4e, 5e high concentration diffusion layer

Claims (5)

[Claims] 1. A semiconductor substrate or semiconductor layer of one conductivity type,
A low concentration first diffusion layer formed of another conductivity type impurity;
A high-concentration second diffusion layer formed of an impurity of another conductivity type, wherein a nitride layer in which nitrogen is introduced is formed on a surface of the semiconductor substrate or the semiconductor layer. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the nitride layer is provided so as to protrude toward a channel side from a side of the low concentration first diffusion layer. 3. The semiconductor device according to claim 1, wherein the one conductivity type is p-type, and the semiconductor device includes a third diffusion layer formed of a p-type impurity in a semiconductor substrate or a semiconductor layer. . 4. The method for manufacturing a semiconductor device according to claim 1, wherein after forming a gate electrode,
A method for manufacturing a semiconductor device, comprising: introducing nitrogen by nitrogen ion implantation and heat treatment to form the nitride layer. 5. The method of manufacturing a semiconductor device according to claim 1, wherein after forming a gate electrode,
Nitriding by heat treatment in an atmosphere containing nitrogen,
A method for manufacturing a semiconductor device, comprising forming the nitride layer.