CN102543747B - Manufacturing method of MOS (Metal Oxide Semiconductor) transistor - Google Patents
Manufacturing method of MOS (Metal Oxide Semiconductor) transistor Download PDFInfo
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- CN102543747B CN102543747B CN201010620464.4A CN201010620464A CN102543747B CN 102543747 B CN102543747 B CN 102543747B CN 201010620464 A CN201010620464 A CN 201010620464A CN 102543747 B CN102543747 B CN 102543747B
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Abstract
The invention discloses a manufacturing method of an MOS (Metal Oxide Semiconductor) transistor. The method comprises the following steps of: providing a semiconductor substrate and forming a grid structure on the semiconductor substrate; performing first ion injection on the semiconductor substrate on both sides of the grid structure by adopting at least one first impurity to form a first doping region, wherein the concentration distribution curve of the first impurity in the first doping region is provided with a first peak value; performing second ion injection on the semiconductor substrate on both sides of the grid structure by adopting a second impurity to form a second doping region, wherein the concentration distribution curve of the second impurity in the second doping region is provided with a second peak value, and the second peak value is positioned below the first peak value; forming a side wall encircling the side wall of the grid structure; and forming a source/drain region. According to an MOS tube formed by using the MOS tube manufacturing method, a transient enhanced diffusion effect is reduced while a hot carrier effect is weakened, and the electric performance of the MOS tube is optimized.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of manufacture method of MOS transistor.
Background technology
Along with integrated circuit develops to very lagre scale integrated circuit (VLSIC), the current densities of IC interior is increasing, and the number of elements comprised also gets more and more.Along with further developing of semiconductor integrated circuit, the size of semiconductor element also reduces thereupon, and MOS transistor basic structure comprises three main region: source electrode (source), drain electrode (drain) and gate electrode (gate).Wherein source electrode and drain electrode are by highly doped formation, different according to type of device, N-shaped can be divided into adulterate (NMOS) and p-type doping (PMOS).
In the process that device is scaled, drain voltage does not reduce thereupon, this just causes the increase of the raceway groove electric field between source/drain, under highfield effect, electronics can accelerate to the speed of more much higher than heat movement speed times between twice collision, thus cause thermoelectronic effect (Hot Carrier Issue, HCI).Described HCI effect can cause hot electron to inject to gate dielectric layer, forms gate electrode electric current and substrate current, affects the reliability of device and circuit, even cause puncturing of device to burn.
In order to overcome described HCI, prior art has developed multiple improving one's methods to mos transistor structure, such as Dual Implantations structure, buried channel structure, discrete gate structure, buries drain structure etc.; Wherein study more and the larger one of practical value is lightly doped drain (lightly doped drain, LDD) structure.The effect of LDD structure reduces channel region electric field, and then significantly can improve thermoelectronic effect.
Referring to figs. 1 to Fig. 4, show the schematic diagram that prior art comprises metal-oxide-semiconductor manufacture method one embodiment of LDD structure.With reference to figure 1, form gate dielectric layer 110 and grid 120 successively on a semiconductor substrate 100; With reference to figure 2, lightly doped LDD injection is carried out to source region 130 and drain region 140, and by annealing process, injection ion is spread in described Semiconductor substrate 100; As shown in Figure 3, side wall 150 is formed in described grid 120 both sides; As shown in Figure 4, carry out heavily doped source/drain injection, form heavily doped region 170,180, due to the barrier effect of described side wall 150, the lightly doped region of the region below described side wall 150 still for being formed when LDD injects, forms LDD structure 130a and 140a.
But, although LDD structure has significant effect to reduction thermoelectronic effect, also there are some shortcomings.
How to optimize LDD structure, while making described LDD structure effectively improve HCI effect, avoid the decline of the performance of other electricity of metal-oxide-semiconductor, become those skilled in the art's problem demanding prompt solution.The improvement opportunity scheme of more LDD structure please refer to the U.S. Patent application etc. that publication number is US20040150014A1.
Summary of the invention
The problem that the present invention solves is to provide a kind of manufacture method of metal-oxide-semiconductor, to optimize the electrology characteristic of formed metal-oxide-semiconductor.
For solving the problem, the invention provides a kind of manufacture method of metal-oxide-semiconductor, comprising:
Semiconductor substrate is provided, forms grid structure on a semiconductor substrate;
Adopt the Semiconductor substrate of at least one first impurity to described grid structure both sides to carry out the first ion implantation, form the first doped region, in described first doped region, the concentration profile of the first impurity has the first peak value;
The Semiconductor substrate of the second impurity to described grid structure both sides is adopted to carry out the second ion implantation, form the second doped region, in described second doped region, the concentration profile of the second impurity has the second peak value, and described second peak value is positioned at the below of described first peak value;
Form the side wall surrounding described gate structure sidewall;
Form source/drain region.
Compared with prior art, the present invention has the following advantages: the metal-oxide-semiconductor that metal-oxide-semiconductor manufacture method of the present invention is formed, while weakening hot carrier's effect, also reduces Transient enhancement diffusion, optimizes the electric property of metal-oxide-semiconductor.
Accompanying drawing explanation
Fig. 1 to Fig. 4 shows the schematic diagram of prior art LDD structure making process one embodiment;
Fig. 5 shows the schematic diagram of metal-oxide-semiconductor manufacture method first execution mode of the present invention;
Fig. 6 to Figure 10 shows the schematic diagram of metal-oxide-semiconductor manufacture method first embodiment of the present invention;
Figure 11 illustrates that metal-oxide-semiconductor manufacture method intermediate ion of the present invention injects the curve chart of angle of inclination and raceway groove electric field;
Figure 12 shows the schematic diagram of metal-oxide-semiconductor manufacture method second execution mode of the present invention;
Figure 13 to Figure 14 shows the schematic diagram of metal-oxide-semiconductor manufacture method second embodiment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, therefore the present invention is not by the restriction of following public specific embodiment.
The invention provides a kind of manufacture method of metal-oxide-semiconductor.With reference to figure 5, show the schematic flow sheet of metal-oxide-semiconductor manufacture method first execution mode of the present invention, the manufacture method of described metal-oxide-semiconductor comprises the following steps:
Step S1, provides Semiconductor substrate, forms grid structure on a semiconductor substrate;
Step S2, adopt the Semiconductor substrate of at least one first impurity to described grid structure both sides to carry out the first ion implantation, form the first doped region, in described first doped region, the concentration profile of the first impurity has the first peak value;
Step S3, the Semiconductor substrate of the second impurity to described grid structure both sides is adopted to carry out the second ion implantation, form the second doped region, in described second doped region, the concentration profile of the second impurity has the second peak value, and described second peak value is positioned at the below of described first peak value;
Step S4, forms the side wall surrounding described gate structure sidewall;
Step S5, forms source/drain region.
Below in conjunction with specific embodiments and the drawings, further describe the technical scheme of metal-oxide-semiconductor manufacture method of the present invention.With reference to figure 6 to Figure 10, show the side schematic view of metal-oxide-semiconductor one embodiment that metal-oxide-semiconductor manufacture method of the present invention is formed, the present embodiment is for NMOS tube.
Perform step S1, with reference to figure 6, provide Semiconductor substrate 200, be formed with isolation structure 201 in described Semiconductor substrate 200, the region between described isolation structure 201 is active area.Described Semiconductor substrate 200 is formed with successively gate dielectric layer 202 and grid 203, described gate dielectric layer 202 forms grid structure with grid 203.
Wherein, described Semiconductor substrate 200 can be silicon (Si) or silicon-on-insulator (SOI).Described isolation structure 201 can be that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.
Semiconductor substrate 200 between described isolation structure 201 is active area.Dopant well (not shown) is also formed in described active area.Described dopant well is formed by the method for diffusion or ion implantation.The kind of the MOS transistor that the type of the Doped ions of described dopant well is to be formed with this active area is relevant, if the conducting channel of MOS transistor to be formed is N-type, then the Doped ions of described dopant well is P type, such as, can be boron ion.If the conduction type of MOS transistor to be formed is P type, then the Doped ions of described dopant well is N-type, such as, be phosphonium ion.
Described gate dielectric layer 202 can be silica (SiO
2) or silicon oxynitride (SiNO).At below 65nm process node, the characteristic size of grid is very little, and gate dielectric layer 202 is high-k (high K) material preferably.Described hafnium comprises hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc.Particularly preferably be hafnium oxide, zirconia and aluminium oxide.The formation process of gate dielectric layer 202 can adopt any prior art well known to those skilled in the art, comparative optimization be chemical vapour deposition technique, the thickness of gate dielectric 202 is 15 ~ 60
Described grid 203 can be the sandwich construction comprising semi-conducting material, such as silicon, germanium, metal or its combination.The formation process of described grid 203 can adopt any prior art well known to those skilled in the art, comparative optimization be chemical vapour deposition technique, such as low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical vapor deposition technique.The thickness of grid 203 is 800 to 3000 dusts.
Perform step S2, with reference to figure 7, adopt the Semiconductor substrate 200 of at least one first impurity to described grid structure both sides to carry out the first ion implantation, form the first doped region 204.
For the step of ion implantation, the present inventor simulates the curve chart (as shown in figure 11) of tilted ion implantation angle of the present invention and raceway groove electric field.In Figure 11, E represents raceway groove electric field, and D is the distance of channel direction, and α represents tilted ion implantation angle, and described tilted ion implantation angle is the direction of ion beam line (ion beam) and the angle in wafer normal direction.As shown in figure 11, for the same position D1 of raceway groove, when α is 0 degree, raceway groove electric field is E1; When α is 15 degree, raceway groove electric field is E2; When α is 30 degree, raceway groove electric field is E3, α when being 45 degree, and raceway groove electric field is E4, wherein E1 > E4 > E3 > E2, the mode that is selecting angle of inclination to inject can reduce raceway groove electric field.In the mode that angle of inclination of the present invention is injected, the angle of inclination of ion implantation is in the scope of 15 ~ 45 degree, and preferably, the angle of inclination of described ion implantation is in the scope of 20 ~ 25 degree.
Inventor finds to make in the second doped region of follow-up formation, second peak value of the second impurities concentration distribution is positioned at the below of the first peak value of the first impurities concentration distribution, the atomic number of described first impurity need be greater than the atomic number of described second impurity, that is the atomic mass of the first impurity is greater than the atomic mass of the second impurity, thus when carrying out ion implantation, described second impurity can form darker doped region, and the concentration profile peak value realizing the second impurity is positioned at below the concentration profile peak value of the first impurity.
In the present embodiment, described first impurity adopts the heavier V group element antimony (Sb) of atomic mass and arsenic (As), the first ion implantation is carried out by Sb and As, form the first doped region 204, particularly, the condition of described first ion implantation is: the Implantation Energy of Sb is in the scope of 5KeV ~ 30KeV, and implantation dosage is at 5E14 ~ 3E15/cm
2scope in, angle of inclination is in the scope of 15 ~ 38 °; The Implantation Energy of As is in the scope of 2KeV ~ 10KeV, and implantation dosage is at 5E14 ~ 3E15/cm
2scope in, angle of inclination is in the scope of 15 ~ 38 °.
It should be noted that, the present invention does not limit the sequencing that Sb and As carries out ion implantation.
Fig. 7 also show the first doped region 204 that Sb and As is formed, impurities concentration distribution curve L in described first doped region 204, described concentration profile has the first peak value X1, owing to adopting the ion implantation mode at angle of inclination, described first peak value X1 is positioned at the below of gate dielectric layer 202, and has the first distance Y1 with described gate dielectric layer 202.
It should be noted that, in other embodiments, described first impurity can also only select Sb element or As to carry out the first ion implantation.Or, the V group element of other atomic number comparatively large (atomic mass is heavier) can also be selected, such as bismuth (Bi) carries out the first ion implantation, or adopt Bi element and/or As to carry out the first ion implantation, wherein, the Implantation Energy of described bismuth ion is in the scope of 5KeV/ ~ 30KeV, and implantation dosage is at 5E14 ~ 3E15/cm
2scope in, angle of inclination is in the scope of 15 ~ 38 °.
Before carrying out ion implantation, need to utilize mask plate (mask), carry out photoetching process, form the photoresist of patterning on semiconductor substrate 200, described photoresist exposed portion Semiconductor substrate; Then with described photoresist for mask, the first ion implantation is carried out to the Semiconductor substrate exposed, forms the first doped region 204, similarly to the prior art, no longer describe in detail.
Step S3, adopts the Semiconductor substrate 200 of the second impurity to described grid structure both sides to carry out the second ion implantation, forms the second doped region 205, and described first doped region 204 and the second doped region 205 can form LDD structure subsequently.
The mode that described second ion implantation process adopts angle of inclination to inject equally, particularly, the angle of inclination of described ion implantation is in the scope of 15 ~ 45 degree.Preferably, the angle of inclination of described ion implantation is in the scope of 20 ~ 25 degree.
The second doped region 205 that described second ion implantation is formed is identical with the region of described first doped region 204, and preferably, described second doped region 205 surrounds described first doped region 204.
In the present embodiment, described second impurity is phosphorus (P), and the condition adopting P to carry out the second ion implantation is: the energy of ion implantation is in the scope of 2 ~ 15Kev, and implantation dosage is from 1E12 ~ 1E14/cm
2scope in, the angle of inclination of injection is in the scope of 15 ~ 38 degree.
The concentration profile M (shown in dotted line) of the second impurity P is also show in Fig. 8, the distance of the peak value X2 distance substrate surface of the concentration profile M of described second impurity P is second distance Y2, described second distance Y2 is greater than described first distance Y1, and that is the position of described second peak value X2 is positioned at the below of described first peak value X1.
Because the second peak value X2 is positioned at below the first peak value X1, so for the LDD structure having the first doped region 204 and the second doped region 205 to be formed subsequently, in LDD structure, the peak value of impurity concentration is between Y1 and Y2, that is the peak value of the impurity concentration of the LDD structure of the present invention's formation is positioned at below the peak value of the first doped region 204 first impurity concentration, this makes the distant of raceway groove electric field distance gate dielectric, hot electron can be avoided to the injection of gate dielectric layer, and then avoid the formation of grid current and substrate current;
Meanwhile, compared with the second doped region 205, the source/drain resistance that LDD structure of the present invention is formed is comparatively large, can reduce raceway groove electric field strength further, weaken HCI effect.
Perform step S4, with reference to figure 9, form the silicon nitride layer (not shown) that conformal covers described grid 203, gate dielectric layer 202, removed by etching be positioned at bottom Semiconductor substrate 200, silicon nitride layer on grid 203 surface, form the side wall 223 surrounding described grid 203 and gate dielectric layer 202.The technique of described formation side wall is same as the prior art, does not repeat them here.
Perform step S5, with reference to Figure 10, heavy doping is carried out to the substrate that side wall 223 exposes, form source/drain region 220, region below side wall 223 is the first doped region 204 and the second doped region 205 formed in step S3 and step S4, is positioned at the first doped region 204 below side wall and the second doped region 205 forms LDD structure.
The metal-oxide-semiconductor with LDD structure that the present invention is formed has good electrology characteristic, and by simulation, inventor finds that the present invention can make substrate current reduce more than 30%, reduce junction leakage.
In prior art, there have been developed bag-shaped (pocket) ion implantation technique, but, there is the metal-oxide-semiconductor of bag-shaped injection region, its Transient enhancement diffusion (Transistent Enhanced Diffusion, TED) is comparatively strong, and described Transient enhancement diffusion not only causes short-channel effect (the ShortChannel effect of transistor, and anti-short-channel effect (Reverse Short Channel Effect, RSCE) SCE).For the metal-oxide-semiconductor being formed with bag-shaped injection region, the present inventor has carried out further optimization and improvement, to solve the problem to its technical scheme.
With reference to Figure 12, show the schematic diagram of metal-oxide-semiconductor manufacture method second execution mode of the present invention, described metal-oxide-semiconductor manufacture method comprises the following steps:
Step S11, provides Semiconductor substrate, forms grid structure on a semiconductor substrate;
Step S12, adopt the Semiconductor substrate of at least one first impurity to described grid structure both sides to carry out the first ion implantation, form the first doped region, in described first doped region, the concentration profile of the first impurity has the first peak value;
Step S13, the Semiconductor substrate of the second impurity to described grid structure both sides is adopted to carry out the second ion implantation, form the second doped region, in described second doped region, the concentration profile of the second impurity has the second peak value, and described second peak value is positioned at the below of described first peak value;
Step S14, forms the defect adsorption zone surrounding described first doped region and the second doped region;
Step S15, forms the bag-shaped injection region surrounding described first doped region and the second doped region;
Step S16, forms the side wall surrounding described gate structure sidewall;
Step S17, forms source/drain region.
The something in common of present embodiment and the first execution mode repeats no more, and is described further step S14 below in conjunction with accompanying drawing to step S17.
With reference to figures 13 to Figure 14, the schematic diagram of metal-oxide-semiconductor second embodiment that metal-oxide-semiconductor manufacture method of the present invention is formed is shown.
As shown in figure 13, in Semiconductor substrate 300, define isolation structure 301, define and be positioned at gate dielectric layer 302 in Semiconductor substrate 300 and grid 303, define the first doped region 304 and the second doped region 305, perform step 14 subsequently, as shown in Figure 3, the defect adsorption zone 306 of encirclement first doped region 304 and the second doped region 305 is formed
In the present embodiment, described defect adsorption zone 306 is formed by angle of inclination ion implantation, particularly, carbon (C) ion implantation or fluorine (F) ion implantation are carried out to the Semiconductor substrate 300 of described grid structure both sides, form defect adsorption zone 306, the condition of described angle of inclination ion implantation is that ion implantation energy is in the scope of 2 ~ 15Kev, and ion implantation dosage is at 5E12 ~ 8E14/cm
2scope in, angle of inclination is in the scope of 2 ~ 35 degree.
The defect absorption that carbon ion in described defect adsorption zone 306 or fluorine ion can will be formed in Semiconductor substrate 300, cluster is formed with defect, thus defect is pricked surely around carbon ion or fluorine ion, which reduce the number of free defect, avoid the Doped ions diffusion of defect in follow-up bag-shaped injection region, reduce Transient enhancement diffusion.
Simultaneously, because defect and carbon ion or fluorine ion form cluster, the Semiconductor substrate of the local forming cluster is made to form irregular lattice arrangement, defect cannot destroy the Atomic Arrangement of Semiconductor substrate 300, thus making the Atomic Arrangement of Semiconductor substrate on the whole more regular, lattice is more orderly, and the scattering that this makes the Doped ions of bag-shaped injection region be subject to reduces, thus the diffusivity of described Doped ions reduces, and further reduces Transient enhancement diffusion.
Preferably, described defect adsorption zone 306 is identical with the position of the bag-shaped injection region of follow-up formation, or defect adsorption zone 306 surrounds the bag-shaped injection region of follow-up formation, so that carry out defect absorption better.
Perform step S16, with reference to Figure 14, after formation defect adsorption zone 306, before forming side wall, by bag-shaped injection, form the bag-shaped injection region 307 surrounding described first doped region and the second doped region; The angle of inclination of general described bag-shaped injection is 15 ~ 35 degree, in the present embodiment, and described defect adsorption zone 306 surrounds described bag-shaped injection region 307.
The metal-oxide-semiconductor that metal-oxide-semiconductor manufacture method of the present invention is formed, while weakening hot carrier's effect, also reduces Transient enhancement diffusion, optimizes the performance of metal-oxide-semiconductor.
In above-described embodiment, for NMOS tube, but the present invention is not restricted to this, can also be PMOS, those skilled in the art, can also to be out of shape accordingly, substitutions and modifications according to the description of above-described embodiment and execution mode.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (11)
1. a manufacture method for metal-oxide-semiconductor, is characterized in that, described metal-oxide-semiconductor is NMOS tube, and described manufacture method comprises:
Semiconductor substrate is provided, forms grid structure on a semiconductor substrate;
Adopt the Semiconductor substrate of at least one first impurity to described grid structure both sides to carry out the first ion implantation, form the first doped region, in described first doped region, the concentration profile of the first impurity has the first peak value;
Phosphorus is adopted to carry out the second ion implantation as the Semiconductor substrate of the second impurity to described grid structure both sides, form the second doped region, in described second doped region, the concentration profile of phosphorus has the second peak value, and described second peak value is positioned at the below of described first peak value;
Described first impurity is the V group element that atomic number is greater than described second foreign atom ordinal number;
Described first doped region and described second doped region form lightly doped drain structure;
Form the side wall surrounding described gate structure sidewall;
Form the source/drain region of N-type doping.
2. manufacture method as claimed in claim 1, it is characterized in that, the step of described formation first doped region comprises carries out the first ion implantation by antimony ion and/or arsenic ion.
3. manufacture method as claimed in claim 1, it is characterized in that, the step of described formation first doped region comprises carries out the first ion implantation by bismuth ion and/or arsenic ion.
4. manufacture method as claimed in claim 2, it is characterized in that, the Implantation Energy of described antimony ion is in the scope of 5KeV ~ 30KeV, and implantation dosage is at 5E14 ~ 3E15/cm
2scope in, angle of inclination is in the scope of 15 ~ 38 °.
5. manufacture method as claimed in claim 2 or claim 3, it is characterized in that, the Implantation Energy of arsenic ion is in the scope of 2KeV ~ 10KeV, and implantation dosage is at 5E14 ~ 3E15/cm
2scope in, angle of inclination is in the scope of 15 ~ 38 °.
6. manufacture method as claimed in claim 1, it is characterized in that, the step of carrying out the second ion implantation comprises: the Implantation Energy of described phosphonium ion is in the scope of 2KeV ~ 5KeV, and implantation dosage is at 1E12/cm
2~ 1E14/cm
2scope in, angle of inclination is in the scope of 15 ~ 38 °.
7. manufacture method as claimed in claim 3, it is characterized in that, the Implantation Energy of described bismuth ion is in the scope of 5KeV ~ 30KeV, and implantation dosage is at 5E14/cm
2~ 3E15/cm
2scope in, angle of inclination is in the scope of 15 ~ 38 °.
8. manufacture method as claimed in claim 1, is characterized in that, before forming side wall, forms the defect adsorption zone surrounding described first doped region and the second doped region after being also included in formation second doped region; After formation defect adsorption zone, before forming side wall, form the bag-shaped injection region surrounding described first doped region and the second doped region.
9. manufacture method as claimed in claim 8, is characterized in that, described defect adsorption zone or described defect adsorption zone identical with the region of bag-shaped injection region surrounds described bag-shaped injection region.
10. manufacture method as claimed in claim 8, is characterized in that, carries out ion implantation form defect adsorption zone by carbon ion or fluorine ion.
11. manufacture methods as claimed in claim 10, it is characterized in that, the ion implantation step of described carbon ion or fluorine ion comprises: the Implantation Energy of carbon ion or fluorine ion is in the scope of 2KeV ~ 15KeV, and implantation dosage is at 5E12 ~ 8E14/cm
2scope in, angle of inclination is in the scope of 2 ~ 35 °.
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| JP2001250945A (en) * | 2000-03-08 | 2001-09-14 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| CN1731588A (en) * | 2004-08-04 | 2006-02-08 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
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| JP2001250945A (en) * | 2000-03-08 | 2001-09-14 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| CN1731588A (en) * | 2004-08-04 | 2006-02-08 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
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